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Top.pwr
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-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Xilinx XPower Analyzer |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Release | 14.7 - P.20131013 (lin64) |
| Command Line | /home/user/.local/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/xpwr -intstyle ise -filter /home/user/workspace/vhdl_projects/camera2/ov7670_vga_Nexys2/iseconfig/filter.filter Top.ncd Top.pcf -o Top.pwr |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------
| Table of Contents |
--------------------------------
| 1. Settings |
| 1.1. Project |
| 1.2. Device |
| 1.3. Environment |
| 1.4. Default Activity Rates |
| 2. Summary |
| 2.1. On-Chip Power Summary |
| 2.2. Thermal Summary |
| 2.3. Power Supply Summary |
| 2.4. Confidence Level |
| 3. Detailed Reports |
| 3.1. By Hierarchy |
| 4. Warnings |
--------------------------------
1. Settings
1.1. Project
---------------------------------------
| Project |
---------------------------------------
| Design File | Top.ncd |
| Settings File | NA |
| Physical Constraints File | Top.pcf |
| Simulation Activity File | NA |
| Design Nets Matched | NA |
| Simulation Nets Matched | NA |
---------------------------------------
1.2. Device
-----------------------------------------------
| Device |
-----------------------------------------------
| Family | Spartan3e |
| Part | xc3s1200e |
| Package | fg320 |
| Temp Grade | Commercial |
| Process | Typical |
| Speed Grade | -4 |
| Characterization | PRODUCTION,v1.2,06-23-09 |
-----------------------------------------------
1.3. Environment
---------------------------
| Environment |
---------------------------
| Ambient Temp (C) | 25.0 |
| Use custom TJA? | No |
| Custom TJA (C/W) | NA |
| Airflow (LFM) | 0 |
---------------------------
1.4. Default Activity Rates
----------------------------------
| Default Activity Rates |
----------------------------------
| FF Toggle Rate (%) | 12.5 |
| I/O Toggle Rate (%) | 12.5 |
| Output Load (pF) | 5.0 |
| I/O Enable Rate (%) | 100.0 |
| BRAM Write Rate (%) | 50.0 |
| BRAM Enable Rate (%) | 50.0 |
----------------------------------
2. Summary
2.1. On-Chip Power Summary
-----------------------------------------------------------------------------
| On-Chip Power Summary |
-----------------------------------------------------------------------------
| On-Chip | Power (mW) | Used | Available | Utilization (%) |
-----------------------------------------------------------------------------
| Clocks | 0.00 | 7 | --- | --- |
| Logic | 0.00 | 945 | 17344 | 5 |
| Signals | 0.00 | 1096 | --- | --- |
| IOs | 0.00 | 80 | 250 | 32 |
| BRAMs | 0.00 | 16 | 28 | 57 |
| Static Power | 158.43 | | | |
| Total | 158.43 | | | |
-----------------------------------------------------------------------------
2.2. Thermal Summary
------------------------------
| Thermal Summary |
------------------------------
| Effective TJA (C/W) | 23.0 |
| Max Ambient (C) | 81.4 |
| Junction Temp (C) | 28.6 |
------------------------------
2.3. Power Supply Summary
----------------------------------------------------------
| Power Supply Summary |
----------------------------------------------------------
| | Total | Dynamic | Static Power |
----------------------------------------------------------
| Supply Power (mW) | 158.43 | 0.00 | 158.43 |
----------------------------------------------------------
---------------------------------------------------------------------------------------------------------------
| Power Supply Currents |
---------------------------------------------------------------------------------------------------------------
| Supply Source | Supply Voltage | Total Current (mA) | Dynamic Current (mA) | Quiescent Current (mA) |
---------------------------------------------------------------------------------------------------------------
| Vccint | 1.200 | 52.86 | 0.00 | 52.86 |
| Vccaux | 2.500 | 35.00 | 0.00 | 35.00 |
| Vcco25 | 2.500 | 3.00 | 0.00 | 3.00 |
---------------------------------------------------------------------------------------------------------------
2.4. Confidence Level
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Confidence Level |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| User Input Data | Confidence | Details | Action |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Design implementation state | High | Design is completely routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
3. Details
3.1. By Hierarchy
-----------------------------------------------------------------------------------------------------------------------------------------------------
| By Hierarchy | Power (mW) | Logic Power (mW) | Signal Power (mW) | # FFs | # LUTs | # BRAMs |
-----------------------------------------------------------------------------------------------------------------------------------------------------
| Hierarchy total | 0.00 | 0.00 | 0.00 | 646 | 763 | 32 |
| Top | 0.00 | 0.00 | 0.00 | 0 / 646 | 1 / 763 | 0 / 32 |
| inst_vgatiming | 0.00 | 0.00 | 0.00 | 23 | 31 | 0 |
| inst_ov7670contr4 | 0.00 | 0.00 | 0.00 | 0 / 95 | 0 / 155 | 0 |
| SCCB | 0.00 | 0.00 | 0.00 | 73 | 79 | 0 |
| Registers | 0.00 | 0.00 | 0.00 | 22 | 76 | 0 |
| Mrom_cmd_reg_rom000014_f6 | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 |
| inst_ov7670contr3 | 0.00 | 0.00 | 0.00 | 0 / 95 | 0 / 155 | 0 |
| SCCB | 0.00 | 0.00 | 0.00 | 73 | 79 | 0 |
| Registers | 0.00 | 0.00 | 0.00 | 22 | 76 | 0 |
| Mrom_cmd_reg_rom000014_f6 | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 |
| inst_ov7670contr2 | 0.00 | 0.00 | 0.00 | 0 / 95 | 0 / 155 | 0 |
| SCCB | 0.00 | 0.00 | 0.00 | 73 | 79 | 0 |
| Registers | 0.00 | 0.00 | 0.00 | 22 | 76 | 0 |
| Mrom_cmd_reg_rom000014_f6 | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 |
| inst_ov7670contr1 | 0.00 | 0.00 | 0.00 | 0 / 95 | 0 / 155 | 0 |
| SCCB | 0.00 | 0.00 | 0.00 | 73 | 79 | 0 |
| Registers | 0.00 | 0.00 | 0.00 | 22 | 76 | 0 |
| Mrom_cmd_reg_rom000014_f6 | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 |
| inst_ov7670capt4 | 0.00 | 0.00 | 0.00 | 35 | 10 | 0 |
| inst_ov7670capt3 | 0.00 | 0.00 | 0.00 | 35 | 10 | 0 |
| inst_ov7670capt2 | 0.00 | 0.00 | 0.00 | 35 | 10 | 0 |
| inst_ov7670capt1 | 0.00 | 0.00 | 0.00 | 35 | 10 | 0 |
| inst_imagegen | 0.00 | 0.00 | 0.00 | 6 | 10 | 0 |
| inst_framebuffer4 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| U0 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| xst_blk_mem_generator | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| gnativebmg.native_blk_mem_gen | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| valid.cstr | 0.00 | 0.00 | 0.00 | 0 / 3 | 2 / 6 | 0 / 8 |
| has_mux_b.B | 0.00 | 0.00 | 0.00 | 3 | 4 | 0 |
| ramloop[0].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[1].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[2].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[3].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| inst_framebuffer3 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| U0 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| xst_blk_mem_generator | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| gnativebmg.native_blk_mem_gen | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| valid.cstr | 0.00 | 0.00 | 0.00 | 0 / 3 | 2 / 6 | 0 / 8 |
| has_mux_b.B | 0.00 | 0.00 | 0.00 | 3 | 4 | 0 |
| ramloop[0].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[1].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[2].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[3].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| inst_framebuffer2 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| U0 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| xst_blk_mem_generator | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| gnativebmg.native_blk_mem_gen | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| valid.cstr | 0.00 | 0.00 | 0.00 | 0 / 3 | 2 / 6 | 0 / 8 |
| has_mux_b.B | 0.00 | 0.00 | 0.00 | 3 | 4 | 0 |
| ramloop[0].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[1].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[2].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[3].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| inst_framebuffer1 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| U0 | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| xst_blk_mem_generator | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| gnativebmg.native_blk_mem_gen | 0.00 | 0.00 | 0.00 | 0 / 3 | 0 / 6 | 0 / 8 |
| valid.cstr | 0.00 | 0.00 | 0.00 | 0 / 3 | 2 / 6 | 0 / 8 |
| has_mux_b.B | 0.00 | 0.00 | 0.00 | 3 | 4 | 0 |
| ramloop[0].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[1].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[2].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| ramloop[3].ram.r | 0.00 | 0.00 | 0.00 | 0 | 0 | 0 / 2 |
| s3_init.ram | 0.00 | 0.00 | 0.00 | 0 | 0 | 2 |
| inst_debounce | 0.00 | 0.00 | 0.00 | 25 | 9 | 0 |
| inst_addrgen4 | 0.00 | 0.00 | 0.00 | 15 | 7 | 0 |
| inst_addrgen3 | 0.00 | 0.00 | 0.00 | 15 | 7 | 0 |
| inst_addrgen2 | 0.00 | 0.00 | 0.00 | 15 | 7 | 0 |
| inst_addrgen1 | 0.00 | 0.00 | 0.00 | 15 | 7 | 0 |
-----------------------------------------------------------------------------------------------------------------------------------------------------
4. Warnings
--------------------------------------------------------------------------------
WARNING:PowerEstimator:270 - Power estimate is considered inaccurate. To see details, generate an advanced report with the "-v" switch.
WARNING:Power:1337 - Clock frequency for clock net "clk50_BUFGP" is zero.
WARNING:Power:1337 - Clock frequency for clock net "clk50_BUFGP/IBUFG" is zero.
WARNING:Power:1337 - Clock frequency for clock net "inst_clk25/clk25" is zero.
WARNING:Power:1337 - Clock frequency for clock net "inst_clk25/clkbuf" is zero.
WARNING:Power:1337 - Clock frequency for clock net "inst_imagegen/o_or0000" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk1_BUFGP" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk1_BUFGP/IBUFG" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk2_BUFGP" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk2_BUFGP/IBUFG" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk3_BUFGP" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk3_BUFGP/IBUFG" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk4_BUFGP" is zero.
WARNING:Power:1337 - Clock frequency for clock net "ov7670_pclk4_BUFGP/IBUFG" is zero.
WARNING:Power:1369 - Clock frequency for one or more clocks was not found through
timing constraints (PCF file) or simulation data. Without knowing the
clock frequency of all clocks, dynamic power information for those clock
domains will default to zero which may under-estimate the power for this
design. To avoid this warning, provide at least one of the following:
1. The proper timing constraints (PERIOD) for clocks (re-implement design
and load the newly generated PCF file into XPower Analyzer)
2. A post PAR simulation-generated VCD or SAIF file indicating clock
frequencies
3. The clock frequency for clocks in the "By Type -> Clocks" view in the
XPower Analyzer GUI and then applying "Update Power Analysis"
--------------------------------------------------------------------------------
Analysis completed: Sat Jul 23 23:50:15 2022
----------------------------------------------------------------