forked from analogdevicesinc/msdk
-
Notifications
You must be signed in to change notification settings - Fork 0
/
ov5640.c
1454 lines (1256 loc) · 35.7 KB
/
ov5640.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/******************************************************************************
*
* Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
* Analog Devices, Inc.),
* Copyright (C) 2023-2024 Analog Devices, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include "mxc_delay.h"
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mipi_camera.h"
#include "sccb.h"
#include "ov5640_regs.h"
// clang-format off
#define cambus_write(addr, x) sccb_write_reg16(g_slv_addr, addr, x)
#define cambus_read(addr, x) sccb_read_reg16(g_slv_addr, addr, x)
#define cambus_writeb(addr, x) sccb_write_byt(g_slv_addr, addr, x)
#define cambus_readb(addr, x) sccb_read_byt(g_slv_addr, addr, x)
#ifdef OV5640_DVP
static struct camera_reg default_regs[] = {
// power down
{0x3008, 0x42},
//# enable pll
{0x3103, 0x03},
// io direction
{0x3017, 0xFF},
{0x3018, 0xFF},
{0x302C, 0xC3},
{0x4740, 0x20}, // VSYNC = active low, HREF= active low, PCLK=high
{0x4713, 0x06}, // JPEG mode select
// sys reset
{0x3000, 0x00}, // enable all blocks
{0x3002, 0x1C}, // reset jfifo, sfifo, jpg, fmux, avg
// clock enable
{0x3004, 0xFF},
{0x3006, 0xC3},
{0x3034, 0x1a}, // PLL, 10-bit
{0x3037, 0x12}, // PLL
{0x3108, 0x01}, // clock divider
{0x3039, 0x0},
//{0x3034, 0x1A},
{0x3035, 0x11},
{0x3036, 0x20},
//{0x3037, 0x1A},
//{0x3108, 0x1},
{0x3824, 0x1},
// ISP control
{0x5000, 0xA7},
{0x5001, 0xa3}, // ISP Control: turn color matrix, awb, SDE and scaling
{0x5003, 0x04}, // bin enable
{0x370C, 0x02},
{0x3634, 0x40},
// AEC/AGC
{0x3A02, 0x03},
{0x3A03, 0xD8},
{0x3A08, 0x01},
{0x3A09, 0x27},
{0x3A0A, 0x00},
{0x3A0B, 0xF6},
{0x3A0D, 0x04},
{0x3A0E, 0x03},
{0x3A0F, 0x30}, // ae_level
{0x3A10, 0x28}, // ae_level
{0x3A11, 0x60}, // ae_level
{0x3A13, 0x43},
{0x3A14, 0x03},
{0x3A15, 0xD8},
{0x3A18, 0x00}, // gainceiling
{0x3A19, 0xF8}, // gainceiling
{0x3A1B, 0x30}, // ae_level
{0x3A1E, 0x26}, // ae_level
{0x3A1F, 0x14}, // ae_level
// vcm debug
{0x3600, 0x08},
{0x3601, 0x33},
// 50/60Hz
{0x3C01, 0xA4},
{0x3C04, 0x28},
{0x3C05, 0x98},
{0x3C06, 0x00},
{0x3C07, 0x08},
{0x3C08, 0x00},
{0x3C09, 0x1C},
{0x3C0A, 0x9C},
{0x3C0B, 0x40},
{0x460C, 0x24}, // disable JPEG footer
// BLC
{0x4001, 0x02},
{0x4004, 0x02},
// AWB0
{0x5180, 0xFF},
{0x5181, 0xF2},
{0x5182, 0x00},
{0x5183, 0x14},
{0x5184, 0x25},
{0x5185, 0x24},
{0x5186, 0x09},
{0x5187, 0x09},
{0x5188, 0x09},
{0x5189, 0x75},
{0x518A, 0x54},
{0x518B, 0xE0},
{0x518C, 0xB2},
{0x518D, 0x42},
{0x518E, 0x3D},
{0x518F, 0x56},
{0x5190, 0x46},
{0x5191, 0xF8},
{0x5192, 0x04},
{0x5193, 0x70},
{0x5194, 0xF0},
{0x5195, 0xF0},
{0x5196, 0x03},
{0x5197, 0x01},
{0x5198, 0x04},
{0x5199, 0x12},
{0x519A, 0x04},
{0x519B, 0x00},
{0x519C, 0x06},
{0x519D, 0x82},
{0x519E, 0x38},
// color matrix (Saturation)
{0x5381, 0x1E},
{0x5382, 0x5B},
{0x5383, 0x08},
{0x5384, 0x0A},
{0x5385, 0x7E},
{0x5386, 0x88},
{0x5387, 0x7C},
{0x5388, 0x6C},
{0x5389, 0x10},
{0x538A, 0x01},
{0x538B, 0x98},
// CIP control (Sharpness)
{0x5300, 0x10}, //# sharpness
{0x5301, 0x10}, //# sharpness
{0x5302, 0x18}, //# sharpness
{0x5303, 0x19}, //# sharpness
{0x5304, 0x10},
{0x5305, 0x10},
{0x5306, 0x08}, //# denoise
{0x5307, 0x16},
{0x5308, 0x40},
{0x5309, 0x10}, //# sharpness
{0x530A, 0x10}, //# sharpness
{0x530B, 0x04}, //# sharpness
{0x530C, 0x06}, //# sharpness
// GAMMA 1
{0x5480, 0x01},
{0x5481, 0x00},
{0x5482, 0x1E},
{0x5483, 0x3B},
{0x5484, 0x58},
{0x5485, 0x66},
{0x5486, 0x71},
{0x5487, 0x7D},
{0x5488, 0x83},
{0x5489, 0x8F},
{0x548A, 0x98},
{0x548B, 0xA6},
{0x548C, 0xB8},
{0x548D, 0xCA},
{0x548E, 0xD7},
{0x548F, 0xE3},
{0x5490, 0x1D},
// Special Digital Effects (SDE) (UV adjust)
{0x5580, 0x06}, // enable brightness and contrast
{0x5583, 0x40}, // special_effect
{0x5584, 0x10}, // special_effect
{0x5586, 0x20}, // contrast
{0x5587, 0x00}, // brightness
{0x5588, 0x00}, // brightness
{0x5589, 0x10},
{0x558A, 0x00},
{0x558B, 0xF8},
{0x501D, 0x40}, // enable manual offset of contrast
{0x501F, 0x01}, // RGB
{0x4300, 0x61}, // RGB565 (BGR)
{0x3002, 0x1C}, // reset jfifo, sfifo, jpg, fmux, avg
{0x3006, 0xC3}, // reset to how it was before (no jpg clock)
{0x3800, 0x0 }, // XSTART=0
{0x3801, 0x0},
{0x3802, 0x0 }, // YSTART=0
{0x3803, 0x0 },
{0x3804, 0xa }, // XEND=2623
{0x3805, 0x3f},
{0x3806, 0x7 }, // YEND=1951
{0x3807, 0x9f},
{0x3808, 0x1 }, // out width=320
{0x3809, 0x40},
{0x380a, 0x0 }, // out height=240
{0x380b, 0xf0},
{0x380c, 0x8 }, // Total HSIZE=2060
{0x380d, 0x0c},
{0x380e, 0x3 }, // Total VSIZE=984
{0x380f, 0xd8},
{0x3810, 0x00}, // X offset
{0x3811, 0x10},
{0x3812, 0x00}, // Y offset
{0x3813, 0x08},
{0x4520, 0x0B},
{0x3814, 0x31}, // timing X inc
{0x3815, 0x31}, // timing Y inc
{0x3820, 0x06},
{0x3821, 0x00},
{0x4514, 0xBB},
// {0x503d, 0x80}, // Test pattern: Color bar
{0x503d, 0x00}, // No test pattern
{0x4741, 0x00},
{0x503e, 0x00},
{0x3008, 0x02}, // wake up from software power down
// Delay
{0xffff, 150},
// End
{0, 0}
};
#else
static struct camera_reg default_regs[] = {
// Reset
{0x3102, 0x11},
{0x3008, 0x82},
{0xffff, 150},
{0x3008, 0x02},
{0xffff, 150},
{0x3008, 0x82},
{0xffff, 150},
// SCCB Control
{0x3103, 0x03},
// SC Pad Out Enable
{0x3017, 0xe0},
{0x3018, 0x00},
// SC PLL Control
// {0x3034, 0x1a}, // 10-bit RAW mode
{0x3034, 0x18}, // 8-bit RAW mode
{0x3008, 0x02},
{0x3035, 0x14},
{0x3036, 0x00},
{0x3037, 0x10},
// SCCB Pad Clock Divide
{0x3108, 0x01},
{0x3630, 0x36},
{0x3631, 0x0e},
{0x3632, 0xe2},
{0x3633, 0x12},
{0x3621, 0xe0},
{0x3704, 0xa0},
{0x3703, 0x5a},
{0x3715, 0x78},
{0x3717, 0x01},
{0x370b, 0x60},
{0x3705, 0x1a},
{0x3905, 0x02},
{0x3906, 0x10},
{0x3901, 0x0a},
{0x3731, 0x12},
{0x3600, 0x08},
{0x3601, 0x33},
{0x302d, 0x60},
{0x3620, 0x52},
{0x371b, 0x20},
{0x471c, 0x50},
// AEC Control
{0x3a13, 0x43},
{0x3a18, 0x00},
{0x3a19, 0xf8},
{0x3635, 0x13},
{0x3636, 0x03},
{0x3634, 0x40},
{0x3622, 0x01},
// 5060Hz Control
{0x3c01, 0x34},
{0x3c04, 0x28},
{0x3c05, 0x98},
{0x3c06, 0x00},
{0x3c07, 0x00},
{0x3c08, 0x01},
{0x3c09, 0x2c},
{0x3c0a, 0x9c},
{0x3c0b, 0x40},
{0x3820, 0x06},
{0x3821, 0x00},
// Active pixel array is 2592x1944
// TIMING HS, X_ADDR_ST, X address start [11:8]
{0x3800, 0x01},
// TIMING HS, X_ADDR_ST, X address start [7:0]
{0x3801, 0x5a},
// TIMING VS, Y_ADDR_ST, Y address start [11:8]
{0x3802, 0x00},
// TIMING VS, Y_ADDR_ST, Y address start [7:0]
{0x3803, 0x16},
// TIMING HW, X_ADDR_END, X address end [11:8]
{0x3804, 0x08},
// TIMING HW, X_ADDR_END, X address end [7:0]
{0x3805, 0xc6},
// TIMING VH, Y_ADDR_END, Y address end [11:8]
{0x3806, 0x07},
// TIMING VH, Y_ADDR_END, Y address end [7:0]
{0x3807, 0x82},
// X_OUPUT_SIZE
{0x3808, 0x00},
{0x3809, 0x20},
// Y_OUTPUT_SIZE
{0x380a, 0x00},
{0x380b, 0x20},
// TIMING HTS, Total horizontal size [11:8]
{0x380c, 0x0f},
// TIMING HTS, Total horizontal size [7:0]
{0x380d, 0xff},
// TIMING VTS, Total vertical size [11:8]
{0x380e, 0x04},
// TIMING VTS, Total vertical size [7:0]
{0x380f, 0xd8},
{0x3810, 0x00},
{0x3811, 0x04},
{0x3812, 0x00},
{0x3813, 0x04},
{0x3618, 0x00},
{0x3612, 0x29},
{0x3708, 0x64},
{0x3709, 0x52},
{0x370c, 0x03},
// AEC/AGC Power Down Domain Control
{0x3a02, 0x03},
{0x3a03, 0xd8},
{0x3a08, 0x01},
{0x3a09, 0x27},
{0x3a0a, 0x00},
{0x3a0b, 0xf6},
{0x3a0e, 0x03},
{0x3a0d, 0x04},
{0x3a14, 0x03},
{0x3a15, 0xd8},
// BLC Control
{0x4001, 0x02},
{0x4004, 0x02},
// System Control
{0x3000, 0x00},
{0x3002, 0x1c},
{0x3004, 0xff},
{0x3006, 0xc3},
{0x300e, 0x58},
{0x302e, 0x00},
{0x4740, 0x22},
// Format Control
{0x4300, 0x61}, // RGB565 ({r[4:0]g[5:3]},{g[2:0],b[4:0]})
// ISP Top Control
{0x501f, 0x01},
// DVP Control
{0x4713, 0x03},
// JPEG Control
{0x4407, 0x04},
{0x440e, 0x00},
// VFIFO Control
{0x460b, 0x35},
{0x460c, 0x23},
// MIPI Transmitter Control
{0x3824, 0x02},
// ISP Top Control
{0x5000, 0xa7},
{0x5001, 0xa3},
// AWB Control
{0x5180, 0xff},
{0x5181, 0xf2},
{0x5182, 0x00},
{0x5184, 0x25},
// 4-3-2023: Settings below removed. AWB seems better without them.
// {0x5183, 0x14},
// {0x5185, 0x24},
// {0x5186, 0x09},
// {0x5187, 0x09},
// {0x5188, 0x09},
// {0x5189, 0x88},
// {0x518a, 0x54},
// {0x518b, 0xee},
// {0x518c, 0xb2},
// {0x518d, 0x50},
// {0x518e, 0x34},
// {0x518f, 0x6b},
// {0x5190, 0x46},
// {0x5191, 0xf8},
// {0x5192, 0x04},
// {0x5193, 0x70},
// {0x5194, 0xf0},
// {0x5195, 0xf0},
// {0x5196, 0x03},
// {0x5197, 0x01},
// {0x5198, 0x04},
// {0x5199, 0x6c},
// {0x519a, 0x04},
// {0x519b, 0x00},
// {0x519c, 0x09},
// {0x519d, 0x2b},
// {0x519e, 0x38},
// CMX Control
{0x5381, 0x1e},
{0x5382, 0x5b},
{0x5383, 0x08},
{0x5384, 0x0a},
{0x5385, 0x7e},
{0x5386, 0x88},
{0x5387, 0x7c},
{0x5388, 0x6c},
{0x5389, 0x10},
{0x538a, 0x01},
{0x538b, 0x98},
// CIP Control
{0x5300, 0x08},
{0x5301, 0x30},
{0x5302, 0x10},
{0x5303, 0x00},
{0x5304, 0x08},
{0x5305, 0x30},
{0x5306, 0x08},
{0x5307, 0x16},
{0x5309, 0x08},
{0x530a, 0x30},
{0x530b, 0x04},
{0x530c, 0x06},
// Gamma Control
{0x5480, 0x01},
{0x5481, 0x08},
{0x5482, 0x14},
{0x5483, 0x28},
{0x5484, 0x51},
{0x5485, 0x65},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x87},
{0x5489, 0x91},
{0x548a, 0x9a},
{0x548b, 0xaa},
{0x548c, 0xb8},
{0x548d, 0xcd},
{0x548e, 0xdd},
{0x548f, 0xea},
{0x5490, 0x1d},
// SDE Control
{0x5580, 0x02},
{0x5583, 0x40},
{0x5584, 0x10},
{0x5589, 0x10},
{0x558a, 0x00},
{0x558b, 0xf8},
// LENC Control
// 4-3-2023: Settings below removed. They seemed to have no performance
// impact at all
// {0x5800, 0x23},
// {0x5801, 0x14},
// {0x5802, 0x0f},
// {0x5803, 0x0f},
// {0x5804, 0x12},
// {0x5805, 0x26},
// {0x5806, 0x0c},
// {0x5807, 0x08},
// {0x5808, 0x05},
// {0x5809, 0x05},
// {0x580a, 0x08},
// {0x580b, 0x0d},
// {0x580c, 0x08},
// {0x580d, 0x03},
// {0x580e, 0x00},
// {0x580f, 0x00},
// {0x5810, 0x03},
// {0x5811, 0x09},
// {0x5812, 0x07},
// {0x5813, 0x03},
// {0x5814, 0x00},
// {0x5815, 0x01},
// {0x5816, 0x03},
// {0x5817, 0x08},
// {0x5818, 0x0d},
// {0x5819, 0x08},
// {0x581a, 0x05},
// {0x581b, 0x06},
// {0x581c, 0x08},
// {0x581d, 0x0e},
// {0x581e, 0x29},
// {0x581f, 0x17},
// {0x5820, 0x11},
// {0x5821, 0x11},
// {0x5822, 0x15},
// {0x5823, 0x28},
// {0x5824, 0x46},
// {0x5825, 0x26},
// {0x5826, 0x08},
// {0x5827, 0x26},
// {0x5828, 0x64},
// {0x5829, 0x26},
// {0x582a, 0x24},
// {0x582b, 0x22},
// {0x582c, 0x24},
// {0x582d, 0x24},
// {0x582e, 0x06},
// {0x582f, 0x22},
// {0x5830, 0x40},
// {0x5831, 0x42},
// {0x5832, 0x24},
// {0x5833, 0x26},
// {0x5834, 0x24},
// {0x5835, 0x22},
// {0x5836, 0x22},
// {0x5837, 0x26},
// {0x5838, 0x44},
// {0x5839, 0x24},
// {0x583a, 0x26},
// {0x583b, 0x28},
// {0x583c, 0x42},
// {0x583d, 0xce},
// {0x5025, 0x00},
// AEC/AGC Power Down Domain Control
{0x3a0f, 0x30},
{0x3a10, 0x28},
{0x3a1b, 0x30},
{0x3a1e, 0x26},
{0x3a11, 0x60},
{0x3a1f, 0x14},
// 50/60Hz Detector Control
{0x3c00, 0x04},
{0xffff, 150},
// Software power down
{0x3008, 0x42},
// Enable all blocks
{0x3000, 0x00},
// Enable FIFOs and JPEG
{0x3002, 0x1c},
// Enable clocks
{0x3004, 0xff},
{0x3006, 0xc3},
// Pad out enables
{0x3017, 0xe0},
{0x3018, 0x00},
// Autofocus Mode
{0x3022, 0x0d},
// MIPI control, 2 lane
{0x4800, 0x24},
{0x300e, 0x45},
{0x302e, 0x08},
// SCLK divider
{0x3108, 0x02},
// PLL multiplier/divider
{0x303d, 0x20},
{0x303b, 0x1e},
{0x501f, 0x01},
// Format control (RGB Type)
{0x3630, 0x2e},
{0x3632, 0xe2},
{0x3633, 0x23},
{0x3704, 0xa0},
{0x3703, 0x5a},
{0x3715, 0x78},
{0x3717, 0x01},
{0x370b, 0x60},
{0x3705, 0x1a},
{0x3905, 0x02},
{0x3906, 0x10},
{0x3901, 0x0a},
{0x3731, 0x12},
// Sensor VFLIP
{0x3820, 0x42},
// ISP Control
{0x5001, 0xa7},
// Horizontal odd/even increment
{0x3814, 0x31},
// Vertical odd/even increment
{0x3815, 0x31},
{0x3821, 0x00},
{0x3618, 0x00},
{0x3612, 0x29},
{0x3708, 0x64},
{0x3709, 0x52},
{0x370c, 0x03},
{0x3008, 0x02},
// Delay
{0xffff, 150},
// End
{0, 0}
};
#endif
//clang-format on
static int g_slv_addr;
static mipi_camera_settings_t g_camera_settings;
/******************************** Static Functions ***************************/
static int init(void)
{
int ret = 0;
g_slv_addr = 0x3C;
return ret;
}
static int get_slave_address(void)
{
return g_slv_addr;
}
static int get_product_id(int* id)
{
int ret = 0;
uint8_t id_high;
uint8_t id_low;
ret |= cambus_read(CHIPID_H, &id_high);
ret |= cambus_read(CHIPID_L, &id_low);
*id = (int)(id_high << 8) + id_low;
return ret;
}
static int get_manufacture_id(int* id)
{
int ret = 0;
uint8_t rev;
ret |= cambus_read(CHIPREV, &rev);
*id = rev;
return ret;
}
static int dump_registers(void)
{
return E_NOT_SUPPORTED;
}
static int reset(void)
{
int ret = 0;
uint8_t value;
ret = cambus_read(SYS_CTRL0, &value);
value |= 0x82; // Software reset
ret |= cambus_write(SYS_CTRL0, value);
MXC_Delay(10000);
value &= ~0x80;
ret |= cambus_write(SYS_CTRL0, value);
// Write default registers
for (int i = 0; (default_regs[i].addr != 0); i++) {
if (default_regs[i].addr == 0xFFFF) {
MXC_Delay(MSEC(default_regs[i].val));
} else {
ret |= cambus_write(default_regs[i].addr, (uint8_t)default_regs[i].val);
#ifdef VERIFY_STARTUP_SETTINGS
// Read back and check for value mismatches. Used for troubleshooting
ret |= cambus_read(default_regs[i].addr, &value);
if (value != default_regs[i].val && default_regs[i].addr != 0x3102 && default_regs[i].addr != 0x3008) { // Skip validation of reset registers
printf("Mismatch at 0x%x! Expected 0x%x but read 0x%x\n", default_regs[i].addr, default_regs[i].val, value);
}
#endif
}
}
return ret;
}
static int sleep(int sleep)
{
int ret = 0;
ret = cambus_write(OV5640_SYSTEM_CTROL0, sleep ? 0x42 : 0x02);
return ret;
}
static int read_reg(uint16_t reg_addr, uint8_t* reg_data)
{
*reg_data = 0xff;
if (cambus_read(reg_addr, reg_data) != 0) {
return -1;
}
return 0;
}
static int write_reg(uint16_t reg_addr, uint8_t reg_data)
{
return cambus_write(reg_addr, reg_data);
}
// Convert the given format to the correct output sequence value
// to write to the FORMAT_CTRL register
static uint8_t _camera_format_to_out_seq(pixel_order_t pixel_order)
{
switch (pixel_order){
default:
return 0;
case PIXEL_ORDER_RAW_BGGR:
return 0x0;
case PIXEL_ORDER_RAW_GBRG:
return 0x1;
case PIXEL_ORDER_RAW_GRBG:
return 0x2;
case PIXEL_ORDER_RAW_RGGB:
return 0x3;
case PIXEL_ORDER_RGB565_BGR:
return 0x0;
case PIXEL_ORDER_RGB565_RGB:
return 0x1;
case PIXEL_ORDER_RGB565_GRB:
return 0x2;
case PIXEL_ORDER_RGB565_BRG:
return 0x3;
case PIXEL_ORDER_RGB565_GBR:
return 0x4;
case PIXEL_ORDER_RGB565_RBG:
return 0x5;
}
}
static int set_pixformat(mipi_camera_format_t camera_format)
{
int ret = 0;
uint8_t current_pll_ctrl = 0; // A field in SC_PLL_CTRL is used to set RAW8/RAW10
g_camera_settings.camera_format = camera_format;
ret |= cambus_write(FORMAT_MUX_CTRL, 1); // Enable ISP RGB
uint8_t out_seq = _camera_format_to_out_seq(camera_format.pixel_order);
switch (camera_format.pixel_format) {
case PIXEL_FORMAT_RAW8:
ret |= cambus_read(SC_PLL_CTRL0, ¤t_pll_ctrl);
ret |= cambus_write(SC_PLL_CTRL0, (current_pll_ctrl & (~0xF)) | 0x8); // 8-bit mode
ret |= cambus_write(FORMAT_CTRL00h, (0x00 << 4) | out_seq);
break;
case PIXEL_FORMAT_RAW10:
ret |= cambus_read(SC_PLL_CTRL0, ¤t_pll_ctrl);
ret |= cambus_write(SC_PLL_CTRL0, (current_pll_ctrl & (~0xF)) | 0xA); // 10-bit mode
ret |= cambus_write(FORMAT_CTRL00h, (0x00 << 4) | out_seq);
break;
case PIXEL_FORMAT_YUV422:
ret |= cambus_write(FORMAT_CTRL00h, (0x03 << 4) | out_seq);
break;
case PIXEL_FORMAT_YUV420:
ret |= cambus_write(FORMAT_CTRL00h, (0x04 << 4) | out_seq);
break;
case PIXEL_FORMAT_RGB444: // Assume RGB444 format 1
ret |= cambus_write(FORMAT_CTRL00h, (0x09 << 4) | out_seq);
break;
case PIXEL_FORMAT_RGB555: // Assume RGB555 format 1
ret |= cambus_write(FORMAT_CTRL00h, (0x07 << 4) | out_seq);
break;
case PIXEL_FORMAT_RGB565:
#if defined(OV5640_DVP)
out_seq = 1;
#endif
ret |= cambus_write(FORMAT_CTRL00h, (0x06 << 4) | out_seq);
break;
case PIXEL_FORMAT_RGB888:
ret |= cambus_write(FORMAT_CTRL00h, (0x02 << 4) | out_seq);
break;
case PIXEL_FORMAT_BYPASS:
ret |= cambus_write(FORMAT_CTRL00h, (0x0f << 4) | out_seq);
break;
default:
ret = E_NOT_SUPPORTED;
break;
}
return ret;
}
static int get_pixformat(mipi_camera_format_t* camera_format)
{
*camera_format = g_camera_settings.camera_format;
return E_NO_ERROR;
}
static int set_framesize(int width, int height)
{
int ret = 0;
// Software power down before updating settings
ret |= cambus_write(SYS_CTRL0, 0x42);
// Image typically outputs one line short, add a line to account.
//height = height + 1;
// Apply passed in resolution as output resolution.
ret |= cambus_write(TIMING_DVPHO_0, (width >> 8) & 0xff);
ret |= cambus_write(TIMING_DVPHO_1, (width >> 0) & 0xff);
ret |= cambus_write(TIMING_DVPVO_0, (height >> 8) & 0xff);
ret |= cambus_write(TIMING_DVPVO_1, (height >> 0) & 0xff);
if ((width * height) > (320 * 320)) {
/*
Divide PLL Clk for higher resolutions. This reduces framerate,
but increases the bandwith we have to process the incoming data.
TODO: There has to be some way to modify the horizontal/vertical
blanking to preserve framerate, but the documentation on the HTS/VTS
registers is non-existent... The drivers may also need to discard
the dummy pixels (?)
*/
ret |= write_reg(0x3035, 0x44);
}
// Software power up
ret |= cambus_write(SYS_CTRL0, 0x02);
return ret;
}
static int set_windowing(int width, int height, int start_x, int start_y, int hsize, int vsize)
{
/* Note: width and height is used to control scaling size of the image
width: horizontal input size
height: vertical input size
hsize: horizontal size of cropped image
vsize: vertical size of cropped image
*/
int ret = 0;
if (width < hsize || height < vsize) {
ret = -1;
}
// Software power down before updating settings
ret |= cambus_write(SYS_CTRL0, 0x42);
// Apply passed in resolution as input resolution.
ret |= cambus_write(TIMING_HTS_0, (width >> 8) & 0xff);
ret |= cambus_write(TIMING_HTS_1, (width >> 0) & 0xff);
ret |= cambus_write(TIMING_VTS_0, (height >> 8) & 0xff);
ret |= cambus_write(TIMING_VTS_1, (height >> 0) & 0xff);
// Apply passed in hsize & vsize as output resolution.
ret |= cambus_write(TIMING_DVPHO_0, (hsize >> 8) & 0xff);
ret |= cambus_write(TIMING_DVPHO_1, (hsize >> 0) & 0xff);
ret |= cambus_write(TIMING_DVPVO_0, (vsize >> 8) & 0xff);
ret |= cambus_write(TIMING_DVPVO_1, (vsize >> 0) & 0xff);
// set window start position
ret |= cambus_write(TIMING_HS_0, (start_x >> 8) & 0xff);
ret |= cambus_write(TIMING_HS_1, (start_x >> 0) & 0xff);
ret |= cambus_write(TIMING_VS_0, (start_y >> 8) & 0xff);
ret |= cambus_write(TIMING_VS_1, (start_y >> 0) & 0xff);
// set window size
ret |= cambus_write(TIMING_HW_0, (hsize >> 8) & 0xff);
ret |= cambus_write(TIMING_HW_1, (hsize >> 0) & 0xff);
ret |= cambus_write(TIMING_VH_0, (vsize >> 8) & 0xff);
ret |= cambus_write(TIMING_VH_1, (vsize >> 0) & 0xff);
// Enable ISP vertical and horizontal scale
ret |= cambus_write(ISP_CTRL01h, 0xa3);
// Software power up
ret |= cambus_write(SYS_CTRL0, 0x02);
return ret;
}
static int set_contrast(int level)
{
int ret = 0;
// Software power down before updating settings
ret |= cambus_write(SYS_CTRL0, 0x42);
switch (level) {
case -4:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);
ret |= cambus_write(0x5587, 0x10);
ret |= cambus_write(0x5588, 0x10);
ret |= cambus_write(0x558a, 0x00);
break;
case -3:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);
ret |= cambus_write(0x5587, 0x14);
ret |= cambus_write(0x5588, 0x14);
ret |= cambus_write(0x558a, 0x00);
break;
case -2:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);
ret |= cambus_write(0x5587, 0x18);
ret |= cambus_write(0x5588, 0x18);
ret |= cambus_write(0x558a, 0x00);
break;
case -1:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);
ret |= cambus_write(0x5587, 0x1C);
ret |= cambus_write(0x5588, 0x1C);
ret |= cambus_write(0x558a, 0x1C);
break;
case 0:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);
ret |= cambus_write(0x5587, 0x20);
ret |= cambus_write(0x5588, 0x20);
ret |= cambus_write(0x558a, 0x00);
break;
case 1:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);
ret |= cambus_write(0x5587, 0x24);
ret |= cambus_write(0x5588, 0x24);
ret |= cambus_write(0x558a, 0x00);
break;
case 2:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);
ret |= cambus_write(0x5587, 0x28);
ret |= cambus_write(0x5588, 0x28);
ret |= cambus_write(0x558a, 0x00);
break;
case 3:
ret |= cambus_write(0x5001, 0xff);
ret |= cambus_write(0x5580, 0x04);