diff --git a/Transmit_Multiple/C_RAM_control.v b/Transmit_Multiple/C_RAM_control.v
new file mode 100644
index 0000000..ef002c2
--- /dev/null
+++ b/Transmit_Multiple/C_RAM_control.v
@@ -0,0 +1,81 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/13/2019 02:14:12 AM
+// Design Name: 
+// Module Name: C_RAM_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module C_RAM_control #(
+    parameter DATAWIDTH = 8,
+    parameter DATADEPTH = 16
+)
+(
+    input clk,
+    input rst,
+    input write_ram,
+    input read_ram_1,
+    input read_ram_2,
+    input [20:0] write_address, read_address_1, read_address_2,
+    output reg [20:0] op_address,
+    output reg ram_en,              // Take care here if reg is a problem or not
+    output reg ram_w_or_r           // Just follow register in register out rules
+    );
+    
+always @(posedge clk or posedge rst)
+begin
+    if(rst) begin
+        ram_en <= 1'b0;
+        ram_w_or_r <= 1'b0;
+        op_address <= 0;
+    end
+    else begin
+        if(write_ram) begin
+            ram_en <= 1'b1;
+            ram_w_or_r <= 1'b1;
+            if(write_address == 0) begin
+                op_address <= DATADEPTH -1;
+            end
+            else begin
+                op_address <= write_address - 1;
+            end
+        end
+        else begin
+            if(read_ram_1) begin
+                ram_en <= 1'b1;
+                ram_w_or_r <= 1'b0;
+                if(read_address_1 == 0) begin
+                    op_address <= DATADEPTH - 1;
+                end
+                else begin
+                    op_address <= read_address_1 - 1;
+                end
+            end
+            else begin
+                if(read_ram_2) begin
+                    ram_en <= 1'b1;
+                    ram_w_or_r <= 1'b0;
+                    op_address <= read_address_2;
+                end
+                else begin
+                    ram_en <= 1'b0;
+                end
+            end
+        end
+    end
+end
+endmodule
diff --git a/Transmit_Multiple/PushButton_Left.v b/Transmit_Multiple/PushButton_Left.v
new file mode 100644
index 0000000..9fc2caf
--- /dev/null
+++ b/Transmit_Multiple/PushButton_Left.v
@@ -0,0 +1,161 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/09/2019 09:41:59 PM
+// Design Name: 
+// Module Name: PushButton_Left
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module PushButton_Left
+# ( 
+    // parameters
+    parameter DATAWIDTH = 8,
+    parameter DATADEPTH = 16
+)
+(
+    input btn_clk,          // Button Clock
+    input clk,              // Main Clock
+    input rst,              // Reset
+    input btn,              // Button input 
+    output reg [DATAWIDTH - 1:0]ciphertext_reg,
+    output reg [20:0]address = 0,
+    output reg ready = 0,
+    output [15:0] dataout_d_debug
+//    output calculating_flag_debug,
+//    output [2:0] counter_debug
+    );
+
+reg         btn_flag = 1'b0;
+reg         rom_en = 1'b0, encrypt_en = 1'b0;
+wire [DATAWIDTH - 1:0]  dataout_d;
+reg  [DATAWIDTH - 1:0]  dataout_q;
+wire [DATAWIDTH - 1:0]  ciphertext;
+reg         i = 1'b0;
+reg         calculating_flag = 1'b0;
+reg  [2:0]  counter = 3'b000;
+reg         address_add_flag = 1'b0;    // Flag to avoid address add twice, 0 is no adding, 1 is already added.
+reg         btn_once_flag = 1'b0;       // Flag to make sure the button only work once                  
+wire        cal_done;                   // Shown calculation done
+
+//assign rom_en_debug = rom_en; 
+//assign counter_debug = counter;
+//assign calculating_flag_debug = calculating_flag;
+
+always @(posedge btn_clk or posedge rst)
+begin
+    if(rst) begin
+        btn_flag <= 1'b0;
+    end
+    else if(btn) begin
+        btn_flag <= 1'b1;
+    end
+//    else if(ready) begin
+    else begin
+        btn_flag <= 1'b0;
+    end
+end
+
+always @(posedge clk or posedge rst)
+begin
+    if(rst) begin
+        rom_en <= 1'b0;
+        encrypt_en <= 1'b0;
+        address <= 0;
+        address_add_flag <= 1'b0;
+        ready <= 1'b0;
+    end
+    else begin
+        if(btn_flag) begin
+            if(~btn_once_flag) begin
+                if(~calculating_flag) begin
+                    btn_once_flag <= 1'b1;
+                    counter <= 2'b00;
+                    calculating_flag <= 1'b1;
+                    rom_en <= 1'b1;
+                    address_add_flag <= 1'b0;
+                // Two clock delay for ROM latency
+                end
+            end
+        end
+        else begin
+            btn_once_flag <= 1'b0;            
+        end
+        if(calculating_flag) begin
+            counter <= counter + 1;
+            if(counter == 3'b101) begin
+            dataout_q <= dataout_d;
+            end
+            if(counter == 3'b111) begin
+                rom_en <= 1'b0;
+                encrypt_en <= 1'b1;
+            end
+        end
+        if(cal_done) begin
+            ready <= 1'b1;
+            ciphertext_reg <= ciphertext;
+            encrypt_en <= 1'b0;
+            calculating_flag <= 1'b0;
+            if(~address_add_flag) begin  
+                address_add_flag <= 1'b1;
+                if(address >= DATADEPTH - 1) begin
+                    address <= 0;
+                end
+                else begin
+                    address <= address + 1;
+                end
+            end
+        end
+        else begin
+            ready <= 1'b0;
+        end
+    end
+//    else if(ready) begin
+//        ciphertext_reg <= ciphertext;
+//        encrypt_en <= 1'b0;
+//        i = ~i;
+//        calculating_flag = 1'b0;
+//        i = ~i;
+//    end
+end
+
+// Instantiate ROM module
+Plaintext_ROM P_ROM (
+    .clka(clk),    // input wire clka
+    .ena(rom_en),      // input wire ena
+    .addra(address),  // input wire [3 : 0] addra
+    .douta(dataout_d)  // output wire [7 : 0] douta
+);
+
+// Instantiate encrpytion module
+encrpytion
+#(
+    .k(DATAWIDTH)
+) encrypt 
+(
+    .clk(clk),
+    .rst(rst),
+    .en(encrypt_en),
+    .a(dataout_q),
+    .n(1763),
+    .e(83),
+    .cipher(ciphertext),
+    .ready_flag(cal_done),
+    .debug_1(dataout_d_debug),
+    .debug_2(debug_2)
+);
+
+endmodule
diff --git a/Transmit_Multiple/PushButton_Right.v b/Transmit_Multiple/PushButton_Right.v
new file mode 100644
index 0000000..d655b3d
--- /dev/null
+++ b/Transmit_Multiple/PushButton_Right.v
@@ -0,0 +1,232 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/25/2019 05:15:28 PM
+// Design Name: 
+// Module Name: PushButton_Right
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module PushButton_Right #(
+parameter DATAWIDTH = 8,
+parameter DATADEPTH = 16
+)
+(
+    input btn_clk,          // Button Clock
+    input clk,              // Main Clock
+    input rst,              // Reset
+    input btn,              // Button input 
+    input [DATAWIDTH-1:0] data_in,      // Transfered data
+    output TxD,             // TxD signal
+    output reg load_data = 0,            // Signal to notice RAM to load a new number to transfer. Active high. 
+    output reg [20:0] address = 0,    // Address of the load number. 21 bits address could handle upto a memory blobk with 2097152 numbers
+    output reg [7:0] debug1=0, debug2       // Debug signal
+    );
+    
+// Local Parameter Declare 
+parameter ONE   = 8'b00110001;
+parameter ZERO  = 8'b00110000;
+parameter SPACE = 8'b00100000;
+parameter UNDERLINE = 8'b01011111;
+
+
+reg btn_flag = 1'b0;                // Button Flag indicated the button pressed, active high.
+reg [12:0] bitcounter = 0;          // Counter to indicate currently bit of data that is transferring, 13 bit counter could handle upto 8096 bits data
+reg btn_once_flag = 1'b0;           // Flag to avoid button debounce
+reg ready = 0;                      // Flag to indicate the transfer process is done
+reg [2:0] counter = 0;              // Counter to set a two clock delay for the RAM latency
+reg transmit = 1'b0;                // Enable signal for transmitter module, active high
+reg [2:0] p_state, n_state;         // Present state and Next state
+reg [DATAWIDTH-1:0] data;           // Temporary registers to hold the transferred data
+reg [7:0] data_trans;               // Registers to hold a bit of transferred data in ASCII code
+wire [7:0] data_trans_q;            // Output nets of data_trans  
+reg update = 0;                     // Flag to indicate the previous bit transfer is done, going next one.
+reg addr_update_flag;               // Flag to indicated the address of load data need to be update, active high
+
+reg debug_flag_2 = 0;     // Debug flag
+wire clear;                         // Clear signal from transmitter module, showing that the data has transferred.
+
+
+assign data_trans_q = data_trans;
+
+always @(posedge btn_clk or posedge rst)
+begin
+    if(rst) begin
+        btn_flag <= 1'b0;
+    end
+    else begin
+        if(btn) begin
+            btn_flag <= 1'b1;
+        end
+        else if(ready) begin
+                btn_flag <= 1'b0;
+        end
+    end
+end
+
+always @(posedge clk or posedge rst)
+begin
+    if(rst) begin
+        address <= 4'b0000;
+        n_state <= 2'b00;
+        load_data <= 1'b0;
+        ready <= 1'b0;
+        transmit <= 1'b0;
+        bitcounter <= 0;
+        addr_update_flag <= 0;
+    end
+    else begin
+        if(btn_flag) begin
+            debug1 <= bitcounter; 
+            debug2[1] <= update;
+            if(clear) begin
+                if(~debug_flag_2) update <= 1;
+                else update <=0;
+            end
+            else update <= 0;
+            case(p_state)
+                3'b000: begin
+                    if(~btn_once_flag) begin
+                        btn_once_flag <= 1'b1;
+                        ready <= 1'b0;
+                        load_data <= 1'b1;
+                        counter <= 0;
+                        address <= 4'b0000;
+                        bitcounter <= 0;
+                        addr_update_flag <=0;      
+                        n_state <= 3'b001;  
+                    end
+                    else begin
+                        n_state <= 3'b000;
+                    end
+                end
+                3'b001: begin
+                    addr_update_flag <= 0;
+                    case(counter)
+                        2: begin
+                            data <= data_in;
+                            counter <= counter + 1;
+                            n_state <= 3'b001;
+                        end
+                        3: begin
+                            counter <= 0;
+                            n_state <= 3'b010;                    
+                        end
+                        default: begin
+                            counter <= counter + 1;
+                            n_state <= 3'b001;
+                        end
+                    endcase
+                end
+                3'b010: begin
+                    if(bitcounter == DATAWIDTH) begin
+                        data_trans <= SPACE;
+                    end
+                    else begin
+                        if(data[DATAWIDTH-1]) begin
+                            data_trans <= ONE;
+                        end
+                        else begin
+                            data_trans <= ZERO;
+                        end
+                    end
+                    n_state <= 3'b011;
+                end
+                3'b011: begin
+                    if(address >= DATADEPTH) begin
+                        n_state <= 3'b100;
+                    end
+//                    if(address >= 15) begin
+//                        transmit <= 0;
+//                        ready <= 1;
+//                        n_state <= 3'b100;
+//                    end
+//                    else begin
+//                        transmit <= 1;
+                       else if(update) begin
+                            if(bitcounter > DATAWIDTH-1) begin
+                                debug_flag_2 <= 1;
+                                transmit <= 0;
+                                bitcounter <= 0;
+                                counter <= 0;
+                                address <= address + 1;
+                                n_state <= 3'b101;
+                                addr_update_flag <= 1;
+                            end
+                            else begin
+                                debug_flag_2 <= 1;
+                                transmit <= 0;
+                                bitcounter <= bitcounter + 1;
+                                data <= data << 1;
+                                n_state <= 3'b101;
+                            end
+                        end
+                        else begin
+                            transmit <= 1;
+                            n_state <= 3'b011;
+                        end
+                    end
+//                end
+                3'b100: begin
+                    transmit <= 0;
+                    address <= 0;
+                    n_state <= 3'b100;
+                    ready <= 1;                  
+                end
+                3'b101: begin
+                    if(~clear) begin
+                        debug_flag_2 <= 0;
+                        if(addr_update_flag) begin
+                            n_state <= 3'b001;
+                        end
+                        else begin
+                            n_state <= 3'b010;
+                        end
+                    end
+                    else begin
+                        n_state <= 3'b101;
+                    end
+                end
+                default: n_state <= 3'b000;
+            endcase
+        end
+        else begin
+            btn_once_flag <= 1'b0;
+            n_state <= 3'b000;
+        end
+    end
+end
+
+always @(posedge clk or posedge rst)
+begin
+    if(rst) begin
+        p_state <= 3'b000;
+    end
+    else begin
+        p_state <= n_state; //previous state change to next state
+    end
+end
+
+transmitter trans_1 (
+    .clk(clk),
+    .reset(rst),
+    .transmit(transmit),
+    .data(data_trans_q),
+    .clear(clear),
+    .TxD(TxD)
+);
+
+endmodule
diff --git a/Transmit_Multiple/PushButton_Up.v b/Transmit_Multiple/PushButton_Up.v
new file mode 100644
index 0000000..67a3a19
--- /dev/null
+++ b/Transmit_Multiple/PushButton_Up.v
@@ -0,0 +1,84 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/13/2019 05:19:53 PM
+// Design Name: 
+// Module Name: PushButton_Up
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module PushButton_Up #(
+    parameter DATAWIDTH = 8,
+    parameter DATADEPTH = 16
+)
+( 
+    input btn_clk,          // Button Clock
+    input clk,              // Main Clock
+    input rst,              // Reset
+    input btn,              // Button input 
+    output reg [20:0] address = 0, // address - 1 is the real address for the operation
+    output reg operation                // if operation is 1, take the action
+    ); 
+
+reg     btn_flag;
+reg     btn_once_flag = 1'b0;       // Flag to make sure the button only work once 
+   
+always @(posedge btn_clk or posedge rst) 
+begin 
+    if(rst) begin 
+        btn_flag <= 1'b0; 
+    end 
+    else begin 
+        if(btn) begin 
+            btn_flag <= 1'b1; 
+        end 
+        else begin 
+            btn_flag <= 1'b0; 
+        end 
+    end
+end 
+
+
+always @(posedge clk or posedge rst) 
+begin 
+    if(rst) begin 
+        address <= 0; 
+        operation <= 1'b0;
+        btn_once_flag <= 1'b0;
+    end 
+    else begin 
+        if(btn_flag) begin 
+            if(~btn_once_flag) begin 
+                btn_once_flag <= 1'b1;
+                if(address >= DATADEPTH -1) begin
+                    address <= 0;
+                end
+                else begin
+                    address <= address + 1;
+                end
+                operation <= 1'b1;              // operation is 1, take the action
+            end
+            else begin
+                address <= address;
+            end
+        end
+        else begin
+            btn_once_flag <= 1'b0;
+            operation <= 1'b0;                  // operation is 0, disable
+        end
+    end
+end
+
+endmodule 
\ No newline at end of file
diff --git a/Transmit_Multiple/Top.v b/Transmit_Multiple/Top.v
new file mode 100644
index 0000000..bccb68d
--- /dev/null
+++ b/Transmit_Multiple/Top.v
@@ -0,0 +1,237 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/09/2019 08:24:23 PM
+// Design Name: 
+// Module Name: Top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module Top (
+	input 				clk,                 	// 100MHz clock from on-board oscillator
+	input				btnCpuReset,			// red pushbutton input 
+	input               btnL, btnU, btnR,
+	output 	[6:0]		seg,					// Seven segment display cathode pins
+	output              dp,
+	output	[7:0]	    an,						// Seven segment display anode pins	
+	output  [15:0]      led,
+    output              uart_rtl_txd
+); 
+
+	// parameter
+	parameter SIMULATE = 0;
+    parameter DATAWIDTH = 12;
+    parameter DATADEPTH = 16;
+	// internal variables
+	wire				sysclk;							// 100MHz clock from on-board oscillator	
+	wire				sysreset;						// system reset signal - asserted high to force reset
+	
+	wire	[7:0]		segs_int;						// seven segment display segments
+	wire				clk_1Hz,clk_10Hz;				// 1HZ clock to drive the counter. 4HZ clock to drive the button
+	wire    [7:0]       count_out;                      // 4-bit decade counter output
+    wire    [20:0]       din_address, dout_dis_address, dout_trans_address, ram_address;
+	wire 	[7:0]		decpts = {7'b0000000, clk_1Hz};	// dp0 is toggled by clk_100Hz 
+//    wire    [7:0]       rom_draw_out;
+//    wire                seg_update_flag;
+//    wire                read_enable, write_enable, ram_enable;
+//    wire                re_flag, we_flag, we_signal;
+    wire    [DATAWIDTH - 1:0]       encrypted_data, ram_dout, display_data;
+    
+    wire                ram_r_en_dis, ram_r_en_trans, ram_write_en;
+    wire                ram_en, ram_write_or_read;              // Enable signal for RAM
+
+	// global assigns
+	assign	sysclk = clk;
+	assign 	sysreset = ~btnCpuReset;					// btnCpuReset is asserted low	
+	assign dp = segs_int[7];							// multiplexed decimal points and segments
+	assign seg = segs_int[6:0];							// produced by the Seven Segment display driver
+//    assign we_signal = re_flag | we_flag;               // write signal depend on both read flag and write flag
+//    assign ram_enable = read_enable | write_enable;     // enable signal for RAM
+
+    
+    // instantiate the clock divider
+   clk_divider
+     #(
+        .CLK_INPUT_FREQ_HZ(32'd100_000_000),
+        .TICK_OUT_FREQ_HZ(1),
+        . SIMULATE(SIMULATE)
+     ) CLKDIV1
+     (
+        .clk(sysclk),
+        .reset(sysreset),
+        .tick_out(clk_1Hz) 
+     );
+     
+   clk_divider
+    #(
+        .CLK_INPUT_FREQ_HZ(32'd100_000_000),
+        .TICK_OUT_FREQ_HZ(10),
+        . SIMULATE(SIMULATE)
+    ) CLKDIV2
+    (
+        .clk(sysclk),
+        .reset(sysreset),
+        .tick_out(clk_10Hz) 
+    );
+   
+    
+    // Instantiate Left PushButton module
+    PushButton_Left #(
+        .DATAWIDTH(DATAWIDTH),
+        .DATADEPTH(DATADEPTH)
+    ) pushbtn_l
+    (
+        .btn_clk(clk_10Hz),
+        .clk(sysclk),
+        .rst(sysreset),
+        .btn(btnL),
+        .ciphertext_reg(encrypted_data),
+        .address(din_address),
+        .ready(ram_write_en),
+        .dataout_d_debug(led[11:0])
+    );
+    
+    PushButton_Up #(
+        .DATAWIDTH(DATAWIDTH),
+        .DATADEPTH(DATADEPTH)
+    ) pushbtn_u
+    (
+        .btn_clk(clk_10Hz),
+        .clk(sysclk),
+        .rst(sysreset),
+        .btn(btnU),
+        .address(dout_dis_address),
+        .operation(ram_r_en_dis)
+    );
+    
+    PushButton_Right #(
+        .DATAWIDTH(DATAWIDTH),
+        .DATADEPTH(DATADEPTH)
+    ) pushbtn_r
+    (
+        .btn_clk(clk_10Hz),
+        .clk(sysclk),
+        .rst(sysreset),
+        .btn(btnR),
+        .data_in(ram_dout),
+        .TxD(uart_rtl_txd),
+        .load_data(ram_r_en_trans),
+        .address(dout_trans_address),
+        .debug1(),
+        .debug2()
+    );
+    
+    // Instantiate RAM IP and its enable control module
+    C_RAM_control #(
+        .DATAWIDTH(DATAWIDTH),
+        .DATADEPTH(DATADEPTH)
+    ) c_ram_control
+    (
+        .clk(sysclk),
+        .rst(sysreset),
+        .write_ram(ram_write_en),
+        .read_ram_1(ram_r_en_dis),
+        .read_ram_2(ram_r_en_trans),
+        .write_address(din_address),
+        .read_address_1(dout_dis_address),
+        .read_address_2(dout_trans_address),
+        .op_address(ram_address),
+        .ram_en(ram_en),
+        .ram_w_or_r(ram_write_or_read)
+    );
+    
+    Ciphertext_RAM C_RAM (
+        .clka(sysclk),    // input wire clka
+        .ena(ram_en),      // input wire ena
+        .wea(ram_write_or_read),      // input wire [0 : 0] wea
+        .addra(ram_address),  // input wire [3 : 0] addra
+        .dina(encrypted_data),    // input wire [7 : 0] dina
+        .douta(ram_dout)  // output wire [7 : 0] douta
+    );
+    
+//    // Instantiate Data address module
+//    ReadData (
+//        .clk(clk_4Hz),
+//        .rst(sysreset),
+//        .btn_u(btnU),
+//        .address(rom_address),
+//        .update_flag_1(we_flag),   // Write flag to RAM
+//        .update_flag_2(write_enable) // Write enable flag to RAM
+//    );   
+    
+//    // Instantiate Button 2 module
+//    button2 (
+//        .clk(clk_4Hz),
+//        .rst(sysreset),
+//        .btn(btnD),
+//        .update_flag_1(re_flag),   // Read flag to RAM
+//        .update_flag_2(read_enable) // Read enable flag to RAM
+//    );
+   
+    
+//    // Instantiate Memory
+//    dist_mem_gen_0 DMemory (
+//      .a(rom_address),      // input wire [3 : 0] a
+//      .spo(rom_draw_out)  // output wire [7 : 0] spo
+//    );
+    
+
+    // instatiate the display content
+    display_control #(
+        .DATAWIDTH(DATAWIDTH),
+        .DATADEPTH(DATADEPTH)
+    ) dis_control 
+    (
+        .clk(sysclk),
+        .cal_en(ram_write_en),
+        .read_en(ram_r_en_dis),
+        .cal_result(encrypted_data),
+        .ram_dout(ram_dout),
+        .display(display_data)
+    );
+    
+
+	// instantiate the 7-segment, 8-digit display
+	sevensegment
+	#(
+		.RESET_POLARITY_LOW(0),
+		.SIMULATE(SIMULATE)
+	) SSB
+	(
+		// inputs for control signals
+		// 5'b11111 is the code for blank
+		.d0({4'b0000, display_data[0]}),
+		.d1({4'b0000, display_data[1]}),
+ 		.d2({4'b0000, display_data[2]}),
+		.d3({4'b0000, display_data[3]}),
+		.d4({4'b0000, display_data[4]}),
+		.d5({4'b0000, display_data[5]}),
+		.d6({4'b0000, display_data[6]}),
+		.d7({4'b0000, display_data[7]}),
+		.dp(decpts),
+		
+		// outputs to seven segment display
+		.seg(segs_int),			
+		.an(an),
+		
+		// clock and reset signals (100 MHz clock, active high reset)
+		.clk(sysclk),
+		.reset(sysreset),
+		
+		// ouput for simulation only
+		.digits_out()
+	);
+	
+	endmodule
diff --git a/Transmit_Multiple/clk_divider.v b/Transmit_Multiple/clk_divider.v
new file mode 100644
index 0000000..4a32540
--- /dev/null
+++ b/Transmit_Multiple/clk_divider.v
@@ -0,0 +1,55 @@
+// clk_divider.v - parameterized clock divider
+//
+// Roy Kravitz
+// 28-Sep-2016
+//
+// Description:
+// ------------
+// Implements a clock divider that can be used to generate a slow(er) clock from the system clock.
+// The module is parameterized so that the clock divider can generate a range of clock outputs.
+// The output clock "tick" is single cycle pulse so that it is usable as an enable in clocked sequential
+// logic.
+//
+module clk_divider
+#(
+	parameter		CLK_INPUT_FREQ_HZ = 32'd100_000_000,		// clock input frequencey in HZ, defaults to 100MHz
+	parameter		TICK_OUT_FREQ_HZ = 32'd100_000,				// clock output frequency in HZ, defaults to 100KHz
+	parameter		SIMULATE = 0								// simulation or hardware, default to hardware
+																// if SIMULATE is asserted the clock timeout period is shortened
+)
+(
+	input wire		clk,										// input clock
+	input wire		reset,										// reset signal, asserted high to reset the circuit
+	output reg		tick_out									// output clock pulse.  1 cycle pulse at output frequency
+);
+
+// local parameters to calculate divider counter parameters
+localparam	[31:0]		CLK_COUNTS = CLK_INPUT_FREQ_HZ / TICK_OUT_FREQ_HZ;		// Top count for clock counter is Input Freq/Output Freq
+																				// For example, using the default case CLK_COUNT is 1000
+																				
+localparam	[31:0]		clk_top_count = SIMULATE ? 32'd5 : (CLK_COUNTS - 1);	// top count for clock divider counter
+																				// subtract 1 from the count because the timer starts at 0
+
+// internal variables
+reg			[31:0]		clk_div_counter;										// clock divider
+
+
+// implement the clock divider
+// Use a synchronous reset because Cumming/Mills recommend it as a way to avoid issues when the circuit
+// comes out of reset
+always @(posedge clk) begin
+	if (reset)  begin
+		clk_div_counter <= 32'd0;
+		tick_out <= 1'b0;
+	end // reset case
+	else if (clk_div_counter == clk_top_count) begin
+		clk_div_counter <= 32'd0;
+		tick_out <= 1'b1;
+	end // top count case
+	else begin
+		clk_div_counter <= clk_div_counter + 32'd1;
+		tick_out <= 1'b0;
+	end // increment clock divider count
+end // always
+
+endmodule
diff --git a/Transmit_Multiple/display_control.v b/Transmit_Multiple/display_control.v
new file mode 100644
index 0000000..926bfa4
--- /dev/null
+++ b/Transmit_Multiple/display_control.v
@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/13/2019 04:47:11 PM
+// Design Name: 
+// Module Name: display_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module display_control #(         // Module for display control. Shown calculate results or data stored in RAM.
+    parameter DATAWIDTH = 8,
+    parameter DATADEPTH = 16
+)
+(
+    input clk,
+    input cal_en,
+    input read_en,
+    input [DATAWIDTH - 1:0] cal_result,
+    input [DATAWIDTH - 1:0] ram_dout,
+    output reg [DATAWIDTH -1:0]display
+    );
+    
+    
+always @(posedge clk)
+begin
+    if(cal_en) begin
+        display <= cal_result;
+    end
+    else begin
+        if(read_en) begin
+            display <= ram_dout;
+        end
+    end
+end
+    
+endmodule
diff --git a/Transmit_Multiple/encryption.v b/Transmit_Multiple/encryption.v
new file mode 100644
index 0000000..2625f19
--- /dev/null
+++ b/Transmit_Multiple/encryption.v
@@ -0,0 +1,189 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/09/2019 08:54:57 PM
+// Design Name: 
+// Module Name: encryption
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module encrpytion       //	Modular Exponentiation
+    # (parameter k = 8)(
+    input clk,              // Clock for the module
+    input rst,              // Reset Signal
+    input en,               // Enable Signal
+    input [k-1:0]a,         // The plaintext
+    input [63:0]n,       // The modulus
+    input [k-1:0]e,           // The exponentiation number
+    output reg [k-1:0]cipher = 0,   // Output - Ciphertext
+    output reg ready_flag = 1'b0,   // Flag to indicate the calculation is done, ready for be updated to a higher level module or next module
+    output [k-1:0]debug_1,debug_2   // Output signal only for debugging
+    );
+
+reg [2*k-1:0]   a1 = 0;         // A factor variable for calculation 
+reg [63:0]   n1 = 0;         // A copy of modulus
+reg [2*k-1:0]   c = 0;          // A middle stage variable to save the temporal calculate result
+reg [2*k-1:0]   b = 0;          // A factor variable for calculation, start with a duplicate of a
+reg [2*k-1:0]   x = 0;          // Duplicate of m2
+reg [2*k-1:0]   y = 0;          // Duplicate of a
+
+reg [k:0]       i;
+reg [3:0]       p_state = 3'b000, n_state = 3'b000;
+reg [1:0]       counter = 0;
+reg             update_flag = 1'b0;     // Flag for update, finite-state machine only update state when flag set to 1
+
+// Debug Part
+integer kk, gg;     // Debug counter
+integer g = 0;      // Debug integer
+reg [7:0]debug = 0;
+assign debug_1 = cipher;
+assign debug_2 = debug;
+//for(kk=0;kk<10;kk=kk+1) begin
+//    gg = gg+1;
+//end
+
+
+always @(posedge clk or posedge rst)	
+begin
+    if(rst) begin           // Reset all variable when reset input goes high
+        ready_flag = 1'b0;
+        c = 0;
+        a1 = 0;
+        n1 = 0;
+        x = 0;
+        y = 0;
+        b = 0;
+        i = 0;
+        n_state = 3'b000;
+    end
+    else if(en) begin
+        if(update_flag) begin
+            case(p_state)
+                3'b000: begin			    // Initializing temporory variables
+                        debug = 0;
+                        g = 0;
+                        a1 = a;
+                        gg = 0;
+                        n1 = n;
+                        y = a1;	// $display("Message M is %d", y);
+                        b = a1;
+                        i = ((e-1)/2);
+                        n_state = 3'b001;
+                        end
+                3'b001: begin               // Check what stage the calculation in is now. (End, or processing)
+                            if(b > 0) begin
+                                n_state = 3'b011;
+                                debug[g] = 1'b1;
+                                g = g+1;
+                            end
+                            else begin   
+                                if(i==0) begin
+                                    n_state = 3'b100;        ////    we got the result here    ////
+                                end
+                                else begin
+                                    i = i-1;
+                                    n_state = 3'b010;
+                                end
+                            end
+                        end
+                3'b010: begin	             // Check if the calculation is on the second i, the last i or the rest i
+                        if(i==0) begin
+                            a1=y;
+                            b=c;
+                            n_state = 3'b001;
+    //                        c = 0;
+                        end
+                        else begin
+                            if(i == (((e-1)/2)-1)) begin
+                                x=c;
+                                a1=c;
+                                b=c;
+    //                            c=0;
+                                n_state = 3'b001;
+                            end
+                            else begin
+                                a1=x;
+                                b=c;
+    //                            c=0;
+                                n_state = 3'b001;
+                            end
+                        end	
+                        c = 0;
+                        end
+                3'b011: begin 			       // Modular Multiplication Logic
+                        if((b & 1)!=0) begin				
+                            c = c + a1;
+                            if(c >= n1) begin
+                                c = c - n1;
+                            end 		
+                        end
+                        a1 = a1 << 1;
+                        if(a1 >= n1) begin
+                            a1 = a1 - n1;
+                        end
+                        b = b >> 1; 
+                        n_state = 3'b001;					
+                        end	
+                3'b100: begin                   // End state, assign value to output cipher, active the ready flag
+                        cipher = c; // $display("Cipher text C is %d", c);
+                        ready_flag = 1'b1;
+                        end
+        
+                default: n_state = 3'b000;
+            endcase
+        end
+    end
+    else begin          // Initialize all variable when enable signal goes low
+        ready_flag = 1'b0;
+        c = 0;
+        a1 = 0;
+        n1 = 0;
+        x = 0;
+        y = 0;
+        b = 0;
+        i = 0;
+        n_state = 3'b000;
+    end
+end
+
+// State machine, setup the counter to avoid mistake (long calculating process may cost more than one clock cycle)
+always @(posedge clk or posedge rst)
+begin
+	if(rst) begin
+	   p_state <= 3'b000;
+	end
+	else begin
+        if(counter == 1) begin
+            p_state <= n_state;
+            counter <= 0;
+            update_flag <= 1'b1;        // Flag for update, finite-state machine only update state when flag set to 1
+        end
+        else begin
+            counter <= counter + 1;
+            update_flag <= 1'b0;        // Flag for update, finite-state machine only update state when flag set to 1
+        end
+    end
+end			
+
+endmodule
+
+
+	
+
+
+
+
+
+
diff --git a/Transmit_Multiple/n4DDRfpga.xdc b/Transmit_Multiple/n4DDRfpga.xdc
new file mode 100644
index 0000000..282c59f
--- /dev/null
+++ b/Transmit_Multiple/n4DDRfpga.xdc
@@ -0,0 +1,271 @@
+## This is the constraints file for the Digital Scoreboard demo.  The design is targeted
+## to the Digilent Nexys4 DDR board.
+## Modified by Roy Kravitz 06-Ict-2015
+##
+## This file is a general .xdc for the Nexys4 DDR Rev. C
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+ set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
+
+
+##Switches
+
+# set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+# set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+# set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+# set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+# set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+# set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+# set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+# set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+# set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS33 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
+# set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS33 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
+# set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+# set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+# set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
+# set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+# set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+# set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+
+
+# LEDs
+
+ set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+ set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+ set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
+ set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
+ set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
+ set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+ set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+ set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+ set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
+ set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
+ set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
+ set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
+ set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
+ set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
+ set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
+ set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
+
+##RGB LEDs
+
+# set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { RGB1_Blue }]; #IO_L5P_T0_D06_14 Sch=led16_b
+# set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { RGB1_Green }]; #IO_L10P_T1_D14_14 Sch=led16_g
+# set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { RGB1_Red }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+# set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { RGB2_Blue }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
+# set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { RGB2_Green }]; #IO_0_14 Sch=led17_g
+# set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { RGB2_Red }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
+
+
+##7 segment display
+
+ set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { seg[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+ set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { seg[1] }]; #IO_25_14 Sch=cb
+ set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { seg[2] }]; #IO_25_15 Sch=cc
+ set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { seg[3] }]; #IO_L17P_T2_A26_15 Sch=cd
+ set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { seg[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
+ set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { seg[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+ set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { seg[6] }]; #IO_L4P_T0_D04_14 Sch=cg
+
+ set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
+
+ set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+ set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+ set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+ set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+ set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+ set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+ set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
+ set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+
+
+##Buttons
+# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnU_IBUF]
+
+ set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { btnCpuReset }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
+# set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { btnC }]; #IO_L9P_T1_DQS_14 Sch=btnc
+ set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { btnU }]; #IO_L4N_T0_D05_14 Sch=btnu
+ set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { btnL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
+ set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { btnR }]; #IO_L10N_T1_D15_14 Sch=btnr
+# set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { btnD }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+
+
+##Pmod Headers
+
+
+##Pmod Header JA
+
+# set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+# set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+# set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+# set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+# set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
+# set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
+# set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
+# set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
+
+
+##Pmod Header JB
+
+# set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+# set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+# set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+# set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+# set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
+# set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
+# set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[6] }]; #IO_0_15 Sch=jb[9]
+# set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
+
+
+##Pmod Header JC
+
+# set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { JC[0] }]; #IO_L23N_T3_35 Sch=jc[1]
+# set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
+# set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L22N_T3_35 Sch=jc[3]
+# set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L19P_T3_35 Sch=jc[4]
+# set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L6P_T0_35 Sch=jc[7]
+# set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { JC[5] }]; #IO_L22P_T3_35 Sch=jc[8]
+# set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { JC[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
+# set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
+
+
+##Pmod Header JD
+
+# set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { JD[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
+# set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L17P_T2_35 Sch=jd[2]
+# set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17N_T2_35 Sch=jd[3]
+# set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L20N_T3_35 Sch=jd[4]
+# set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
+# set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { JD[5] }]; #IO_L20P_T3_35 Sch=jd[8]
+# set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { JD[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
+# set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
+
+
+##Pmod Header JXADC
+
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVDS     } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVDS     } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVDS     } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVDS     } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVDS     } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVDS     } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVDS     } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVDS     } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
+
+
+##VGA Connector
+
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
+
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
+
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
+
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
+
+
+##Micro SD Connector
+
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RE#set }]; #IO_L14P_T2_SRCC_35 Sch=sd_re#set
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
+
+
+##Accelerometer
+
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
+
+
+##Temperature Sensor
+
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
+
+##Omnidirectional Microphone
+
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
+
+
+##PWM Audio Amplifier
+
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+
+
+##USB-RS232 Interface
+
+# set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { uart_rtl_rxd }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
+ set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { uart_rtl_txd }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
+# set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
+# set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
+
+##USB HID (PS/2)
+
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
+
+
+##SMSC Ethernet PHY
+
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
+
+
+##Quad SPI Flash
+
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Transmit_Multiple/sevensegment.v b/Transmit_Multiple/sevensegment.v
new file mode 100644
index 0000000..3acc31f
--- /dev/null
+++ b/Transmit_Multiple/sevensegment.v
@@ -0,0 +1,273 @@
+// sevensegment.v - -8 digit 7-segment display controller
+//
+// Copyright Roy Kravitz, 2014, 2015
+// 
+// Created By:		Roy Kravitz, David Glover, Caren Zgheib
+// Last Modified:	20-Aug-2014 (RK)
+//
+// Revision History:
+// -----------------
+// Apr-2013		DG		Created this module for the Digilent Nexys 3
+// Dec-2014		RK		Cleaned up the formatting.  No functional changes
+// Mar-2014		CZ		Formatted this module for the Digilent Nexys 4
+// Aug-2014		RK		Parameterized module.  Modified for Vivado and Nexys4
+//
+// Description:
+// ------------
+// This module controls the 8-digit 7-segment display found on
+// the Nexys4 FPGA board.  The eight digits can be displayed as
+// hex digits or as special characters for blanking the digit or
+// displaying a single segment.  The decimal points (dots) between
+// each digit are also controlled.  Each digit is displayed
+// according to the following code.	
+// 
+//   Value			Displays
+//  0 - 9		Characters 0 to 9
+//  10 - 15     Characters A to F
+//  16 - 22     Single segments a - g
+//  23 			Blank (Off)
+//  24 - 28		Uppercase H, R, L and lower case r, l
+//  29 - 31     Blank (Off)
+//
+//	The decimal points are on or off for each digit according to input dp
+// 
+///////////////////////////////////////////////////////////////////////////
+module sevensegment
+#(
+	// parameters
+	parameter integer	CLK_FREQUENCY_HZ		= 100000000, 
+	parameter integer	REFRESH_FREQUENCY_HZ	= 500,
+	parameter integer	RESET_POLARITY_LOW		= 1,
+	parameter integer 	CNTR_WIDTH 				= 32,
+	
+	parameter integer	SIMULATE				= 0,
+	parameter integer	SIMULATE_FREQUENCY_CNT	= 5
+)
+(
+	// ports
+	input 				clk,												// system clock
+	input 				reset,												// system reset signal
+
+	input		[4:0]	d0, d1, d2, d3, d4, d5, d6, d7,						// digits to be displayed
+	input		[7:0]	dp,													// decimal points to be displayed
+
+	output reg	[7:0]	seg = 8'b11111111,									// output to seven segment display cathode
+	output reg	[7:0]	an = 8'b11111110,									// output to seven segment display anode
+	
+	output	reg [63:0]	digits_out = 64'b0									// for simulation only
+);
+
+	// internal variables
+	
+	// reset - asserted high
+	wire reset_in = RESET_POLARITY_LOW ? ~reset : reset;
+	
+	// clock divider 
+	reg			[CNTR_WIDTH-1:0] clk_cnt;
+	wire		[CNTR_WIDTH-1:0] top_cnt = SIMULATE ? SIMULATE_FREQUENCY_CNT : ((CLK_FREQUENCY_HZ / REFRESH_FREQUENCY_HZ) - 1);
+
+	// cathode outputs for each digit
+	wire [7:0]		dig0, dig1, dig2, dig3, dig4, dig5, dig6, dig7;	
+	
+	// anode outputs for each digit
+	localparam digit1 = 8'b11111110;
+	localparam digit2 = 8'b11111101;
+	localparam digit3 = 8'b11111011;
+	localparam digit4 = 8'b11110111;
+	localparam digit5 = 8'b11101111;
+	localparam digit6 = 8'b11011111;
+	localparam digit7 = 8'b10111111;
+	localparam digit8 = 8'b01111111;
+
+	// clock divider counter
+	always @ (posedge clk) begin
+		if (reset_in) begin
+			clk_cnt <= 0;
+		end
+		else if(clk_cnt == top_cnt) begin
+			clk_cnt <= 1'b0;
+		end
+		else begin
+			clk_cnt <= clk_cnt + 1'b1;
+		end
+	end  // clock divider counter
+
+	// anode control
+	always @ (posedge clk) begin
+		if (reset_in) begin
+			an <= digit1;
+		end
+		else if (clk_cnt == top_cnt) begin
+			case (an)
+				digit1: an <= digit2;
+				digit2: an <= digit3;
+				digit3: an <= digit4;
+				digit4: an <= digit5;
+				digit5: an <= digit6;
+				digit6: an <= digit7;
+				digit7: an <= digit8;
+				digit8: an <= digit1;
+				
+				default: an <= digit1;
+			endcase
+		end
+		else begin
+			an <= an;
+		end
+	end  //anode control
+
+	// cathode control
+	always @ (posedge clk) begin
+		case (an) 
+			digit1: seg <= dig0;
+			digit2: seg <= dig1;
+			digit3: seg <= dig2;
+			digit4: seg <= dig3;
+			digit5: seg <= dig4;
+			digit6: seg <= dig5;
+			digit7: seg <= dig6;
+			digit8: seg <= dig7;
+			
+			default: seg <= 8'b0;
+		endcase
+	end
+
+// Instantiate the 7-segment decoder for each digit	
+Digit Digit0 (
+	.clk(clk),
+	.d(d0),
+	.dp(dp[0]),
+	.seg(dig0)
+);
+
+Digit Digit1 (
+	.clk(clk),
+	.d(d1),
+	.dp(dp[1]),
+	.seg(dig1)
+);
+
+Digit Digit2 (
+	.clk(clk),
+	.d(d2),
+	.dp(dp[2]),
+	.seg(dig2)
+);
+
+Digit Digit3 (
+	.clk(clk),
+	.d(d3),
+	.dp(dp[3]),
+	.seg(dig3)
+);
+
+Digit Digit4 (
+	.clk(clk),
+	.d(d4),
+	.dp(dp[4]),
+	.seg(dig4)
+);
+
+Digit Digit5 (
+	.clk(clk),
+	.d(d5),
+	.dp(dp[5]),
+	.seg(dig5)
+);
+
+Digit Digit6 (
+	.clk(clk),
+	.d(d6),
+	.dp(dp[6]),
+	.seg(dig6)
+);
+
+Digit Digit7 (
+	.clk(clk),
+	.d(d7),
+	.dp(dp[7]),
+	.seg(dig7)
+);
+
+endmodule  // seven segemnt
+
+
+// 7-segment decoder
+module Digit (
+	input 				clk,
+	input 		[4:0]	d,			// digit code to be displayed
+	input				dp,			// decimal point to be displayed
+
+	output reg	[7:0]	seg 		// output to seven segment display cathode
+);
+
+localparam zero	= 7'b1000000;
+localparam one	= 7'b1111001;
+localparam two	= 7'b0100100;
+localparam three = 7'b0110000;
+localparam four = 7'b0011001;
+localparam five = 7'b0010010;
+localparam six = 7'b0000010;
+localparam seven = 7'b1111000;
+localparam eight = 7'b0000000;
+localparam nine = 7'b0010000;
+localparam A = 7'b0001000;
+localparam B = 7'b0000011;
+localparam C = 7'b1000110;
+localparam D = 7'b0100001;
+localparam E = 7'b0000110;
+localparam F = 7'b0001110;
+localparam seg_a = 7'b1111110;
+localparam seg_b = 7'b1111101;
+localparam seg_c = 7'b1111011;
+localparam seg_d = 7'b1110111;
+localparam seg_e = 7'b1101111;
+localparam seg_f = 7'b1011111;
+localparam seg_g = 7'b0111111;
+
+localparam upH = 7'b0001001;
+localparam upL = 7'b1000111;
+localparam upR = 7'b0001000;
+localparam lol = 7'b1001111;
+localparam lor = 7'b0101111;
+
+localparam  blank = 7'b1111111;
+
+
+always @ (posedge clk) begin
+	case (d)
+		5'd00: seg <= {~dp,zero};
+		5'd01: seg <= {~dp,one};
+		5'd02: seg <= {~dp,two};
+		5'd03: seg <= {~dp,three};
+		5'd04: seg <= {~dp,four};
+		5'd05: seg <= {~dp,five};
+		5'd06: seg <= {~dp,six};
+		5'd07: seg <= {~dp,seven};
+		5'd08: seg <= {~dp,eight};
+		5'd09: seg <= {~dp,nine};
+		5'd10: seg <= {~dp,A};
+		5'd11: seg <= {~dp,B};
+		5'd12: seg <= {~dp,C};
+		5'd13: seg <= {~dp,D};
+		5'd14: seg <= {~dp,E};
+		5'd15: seg <= {~dp,F};
+		5'd16: seg <= {~dp,seg_a};
+		5'd17: seg <= {~dp,seg_b};
+		5'd18: seg <= {~dp,seg_c};
+		5'd19: seg <= {~dp,seg_d};
+		5'd20: seg <= {~dp,seg_e};
+		5'd21: seg <= {~dp,seg_f};
+		5'd22: seg <= {~dp,seg_g};
+		5'd24: seg <= {~dp,upH};
+		5'd25: seg <= {~dp,upL};
+		5'd26: seg <= {~dp,upR};
+		5'd27: seg <= {~dp,lol};
+		5'd28: seg <= {~dp,lor};
+		
+		default: seg <= {~dp,blank};
+	endcase
+end
+
+endmodule  // Digit 7-segment decoder
+	
diff --git a/Transmit_Multiple/testfile1.coe b/Transmit_Multiple/testfile1.coe
new file mode 100644
index 0000000..739aead
--- /dev/null
+++ b/Transmit_Multiple/testfile1.coe
@@ -0,0 +1,19 @@
+; Test file for ROM_7Segment display
+memory_initialization_radix=2;
+memory_initialization_vector=
+00000010,
+00001010,
+00000011,
+00000100,
+00000101,
+00000111,
+00001000,
+00010001,
+00110110,
+01010010,
+00100011,
+10110000,
+00011000,
+11001100,
+00010110,
+11111111;
diff --git a/Transmit_Multiple/transmitter.v b/Transmit_Multiple/transmitter.v
new file mode 100644
index 0000000..032a917
--- /dev/null
+++ b/Transmit_Multiple/transmitter.v
@@ -0,0 +1,121 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/25/2019 05:36:19 PM
+// Design Name: 
+// Module Name: transmitter
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module transmitter(
+    input clk, //UART input clock
+    input reset, // reset signal
+    input transmit, //btn signal to trigger the UART communication
+    input [7:0] data, // data transmitted
+    output reg clear,
+//    output reg loadnext, // flag to inform data read from RAM in advanced
+    output reg TxD // Transmitter serial output. TxD will be held high during reset, or when no transmissions aretaking place. 
+    );
+
+//internal variables
+reg [3:0] bitcounter; //4 bits counter to count up to 10
+reg [13:0] counter; //14 bits counter to count the baud rate, counter = clock / baud rate
+reg state,nextstate; // initial & next state variable
+// 10 bits data needed to be shifted out during transmission.
+//The least significant bit is initialized with the binary value "0" (a start bit) A binary value "1" is introduced in the most significant bit 
+reg [9:0] rightshiftreg; 
+reg shift; //shift signal to start bit shifting in UART
+reg load; //load signal to start loading the data into rightshift register and add start and stop bit
+//reg clear; //clear signal to start reset the bitcounter for UART transmission
+//reg loadnext;
+//UART transmission logic
+always @ (posedge clk) 
+begin 
+    if (reset) 
+	   begin // reset is asserted (reset = 1)
+        state <=0; // state is idle (state = 0)
+        counter <=0; // counter for baud rate is reset to 0 
+        bitcounter <=0; //counter for bit transmission is reset to 0
+       end
+    else begin
+         counter <= counter + 1; //counter for baud rate generator start counting 
+            if (counter >= 10415) //if count to 10416 (from 0 to 10415)
+               begin 
+                  state <= nextstate; //previous state change to next state
+                  counter <=0; // reset couter to 0
+            	  if (load) rightshiftreg <= {1'b1,data,1'b0}; //load the data if load is asserted
+		          if (clear) bitcounter <=0; // reset the bitcounter if clear is asserted
+                  if (shift) 
+                     begin // if shift is asserted
+                        rightshiftreg <= rightshiftreg >> 1; //right shift the data as we transmit the data from lsb
+                        bitcounter <= bitcounter + 1; //count the bitcounter
+                     end
+               end
+         end
+end 
+
+//state machine
+
+always @ (posedge clk) //trigger by positive edge of clock, 
+//always @ (state or bitcounter or transmit)
+begin
+    load <=0; // set load equal to 0 at the beginning
+//    load_next <=0; //
+    shift <=0; // set shift equal to 0 at the beginning
+    clear <=0; // set clear equal to 0 at the beginning
+    TxD <=1; // set TxD equals to during no transmission
+    case (state)
+        0: begin // idle state
+            if (transmit) begin // assert transmit input
+            nextstate <= 1; // Move to transmit state
+            load <=1; // set load to 1 to prepare to load the data
+            shift <=0; // set shift to 0 so no shift ready yet
+            clear <=0; // set clear to 0 to avoid clear any counter
+//            load_next <= 0;
+            end 
+		else begin // if transmit not asserted
+            nextstate <= 0; // next state is back to idle state
+            TxD <= 1; 
+            end
+        end
+        1: begin  // transmit state
+            if (bitcounter >=10) begin // check if transmission is complete or not. If complete
+                nextstate <= 0; // set nextstate back to 0 to idle state
+                clear <=1; // set clear to 1 to clear all counters
+            end 
+            else begin // if transmisssion is not complete 
+                nextstate <= 1; // set nextstate to 1 to stay in transmit state
+                TxD <= rightshiftreg[0]; // shift the bit to output TxD
+                shift <=1; // set shift to 1 to continue shifting the data
+                end
+            end
+        default: nextstate <= 0;                      
+    endcase
+end
+
+//always @(posedge clk)
+//begin
+////    if(loadnext) begin
+////        if(~in) begin
+////            update <= 1'b1;
+////        end
+////    end
+////    else begin
+////        update <= 1'b0;
+////    end
+//end
+
+endmodule
\ No newline at end of file