diff --git a/arch/arm64/arch.c b/arch/arm64/arch.c
index 91ead7b2a..5aef7c3fc 100644
--- a/arch/arm64/arch.c
+++ b/arch/arm64/arch.c
@@ -31,12 +31,6 @@ static void arm64_cpu_early_init(void) {
     /* set the vector base */
     ARM64_WRITE_SYSREG(VBAR_EL1, (uint64_t)&arm64_exception_base);
 
-    /* switch to EL1 */
-    unsigned int current_el = ARM64_READ_SYSREG(CURRENTEL) >> 2;
-    if (current_el > 1) {
-        arm64_el3_to_el1();
-    }
-
     arch_enable_fiqs();
 }
 
diff --git a/arch/arm64/asm.S b/arch/arm64/asm.S
index 500412071..a5dd607ac 100644
--- a/arch/arm64/asm.S
+++ b/arch/arm64/asm.S
@@ -43,37 +43,6 @@ FUNCTION(arm64_context_switch)
 
     ret
 
-FUNCTION(arm64_el3_to_el1)
-    /* set EL2 to 64bit */
-    mrs x0, scr_el3
-    orr x0, x0, #(1<<10)
-    msr scr_el3, x0
-
-    /* set EL1 to 64bit */
-    mov x0, #(1<<31)
-    msr hcr_el2, x0
-
-    /* disable EL2 coprocessor traps */
-    mov x0, #0x33ff
-    msr cptr_el2, x0
-
-    /* disable EL1 FPU traps */
-    mov x0, #(0b11<<20)
-    msr cpacr_el1, x0
-
-    /* set up the EL1 bounce interrupt */
-    mov x0, sp
-    msr sp_el1, x0
-
-    adr x0, .Ltarget
-    msr elr_el3, x0
-
-    mov x0, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
-    msr spsr_el3, x0
-    isb
-
-    eret
-
     /* drop from whatever EL we may already be in to EL1.
      * carefully avoids using x0-x3 since this is called from start.S
      * which is trying to preserve them.
diff --git a/arch/arm64/include/arch/arm64.h b/arch/arm64/include/arch/arm64.h
index fefcbd16e..2ae974992 100644
--- a/arch/arm64/include/arch/arm64.h
+++ b/arch/arm64/include/arch/arm64.h
@@ -58,7 +58,6 @@ struct arm64_stackframe {
 
 struct thread;
 extern void arm64_exception_base(void);
-void arm64_el3_to_el1(void);
 void arm64_fpu_exception(struct arm64_iframe_long *iframe);
 void arm64_fpu_save_state(struct thread *thread);