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chipyard.patch
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chipyard.patch
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diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index a91fa479..2666daea 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink._
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
- with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register
+// with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index 6660d159..e73303c4 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -13,7 +13,8 @@ import freechips.rocketchip.config.{Config}
class AbstractConfig extends Config(
// The HarnessBinders control generation of hardware in the TestHarness
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
- new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
+// new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled // SoC.One 2022/09/24
+ new chipyard.harness.WithSimAXIMem++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled // SoC.One 2022/09/24
new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM
new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
@@ -30,26 +31,26 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
new chipyard.iobinders.WithNICIOPunchthrough ++
- new chipyard.iobinders.WithSerialTLIOCells ++
+// new chipyard.iobinders.WithSerialTLIOCells ++
new chipyard.iobinders.WithDebugIOCells ++
- new chipyard.iobinders.WithUARTIOCells ++
+// new chipyard.iobinders.WithUARTIOCells ++
new chipyard.iobinders.WithGPIOCells ++
- new chipyard.iobinders.WithUARTIOCells ++
- new chipyard.iobinders.WithSPIIOCells ++
+// new chipyard.iobinders.WithUARTIOCells ++
+// new chipyard.iobinders.WithSPIIOCells ++
new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithExtInterruptIOCells ++
- new chipyard.iobinders.WithCustomBootPin ++
+// new chipyard.iobinders.WithCustomBootPin ++
- new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
+// new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
new chipyard.config.WithBootROM ++ // use default bootrom
- new chipyard.config.WithUART ++ // add a UART
- new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
+// new chipyard.config.WithUART ++ // add a UART
+// new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus
- new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
- new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
+// new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
+// new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
index 9e1f558a..ba29cbc0 100644
--- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -1,6 +1,7 @@
package chipyard
import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.rocket.{DCacheParams}
// ---------------------
// BOOM Configs
@@ -43,3 +44,95 @@ class DromajoBoomConfig extends Config(
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNSmallBooms(1) ++
new chipyard.config.AbstractConfig)
+
+class LitexSmallBoomConfig extends Config(
+ new boom.common.WithNSmallBooms(1) ++ // small boom config
+ new freechips.rocketchip.subsystem.WithLitexMemPort() ++
+ new freechips.rocketchip.subsystem.WithLitexMMIOPort() ++
+ new freechips.rocketchip.subsystem.WithLitexSlavePort ++
+ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(8) ++
+ new chipyard.config.AbstractConfig)
+
+class LitexBaseBoomConfig extends Config(
+ new freechips.rocketchip.subsystem.WithLitexMemPort() ++
+ new freechips.rocketchip.subsystem.WithLitexMMIOPort() ++
+ new freechips.rocketchip.subsystem.WithLitexSlavePort ++
+ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(8) ++
+ new chipyard.config.AbstractConfig
+)
+
+class LitexBoomConfig extends Config(
+ new boom.common.WithNSmallBooms(1) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexBoomTraceConfig extends Config(
+ new boom.common.WithNSmallBooms(1) ++
+ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
+ new LitexBaseBoomConfig
+)
+
+
+class LitexLinuxBoomConfig extends Config(
+ new boom.common.WithNMediumBooms(1) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinux4BoomConfig extends Config(
+ new boom.common.WithNMediumBooms(4) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinuxDBoomConfig extends Config(
+ new boom.common.WithNMediumBooms(1) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(128) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinux2DBoomConfig extends Config(
+ new boom.common.WithNMediumBooms(2) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(128) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinuxQBoomConfig extends Config(
+ new boom.common.WithNMediumBooms(1) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(256) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinux2QBoomConfig extends Config(
+ new boom.common.WithNMediumBooms(2) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(256) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinuxFullBoomConfig extends Config(
+ new boom.common.WithNLargeBooms(1) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinuxFullDBoomConfig extends Config(
+ new boom.common.WithNLargeBooms(1) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(128) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinuxFull4DBoomConfig extends Config(
+ new boom.common.WithNLargeBooms(4) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(128) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinuxFullQBoomConfig extends Config(
+ new boom.common.WithNLargeBooms(1) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(256) ++
+ new LitexBaseBoomConfig
+)
+
+class LitexLinuxFull4QBoomConfig extends Config(
+ new boom.common.WithNLargeBooms(4) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(256) ++
+ new LitexBaseBoomConfig
+)
+
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 96257838..5f3498e3 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -240,3 +240,19 @@ class MulticlockAXIOverSerialConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new chipyard.config.AbstractConfig)
// DOC include end: MulticlockAXIOverSerialConfig
+//
+class BaseLitexRocketConfig extends Config(
+ new freechips.rocketchip.subsystem.WithLitexMemPort() ++
+ new freechips.rocketchip.subsystem.WithLitexMMIOPort() ++
+ new freechips.rocketchip.subsystem.WithLitexSlavePort ++
+ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(8) ++
+ new freechips.rocketchip.system.BaseConfig
+// new chipyard.TraceGenConfig
+)
+
+class LitexRocketConfig extends Config(
+ new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
+ new freechips.rocketchip.subsystem.WithMemoryDataBits(64) ++
+ new BaseLitexRocketConfig
+)
+
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index 3f9e27d1..b399f53e 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -14,6 +14,7 @@ class AbstractTraceGenConfig extends Config(
new chipyard.config.WithMemoryBusFrequency(100.0) ++
new chipyard.config.WithPeripheryBusFrequency(100.0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+ new chipyard.config.WithBootROM ++ // use default bootrom
new freechips.rocketchip.groundtest.GroundTestBaseConfig)