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HMAC_in_interface.yaml
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HMAC_in_interface.yaml
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uvmf:
interfaces:
HMAC_in:
clock: clk
reset: rst
reset_assertion_level: 'False'
config_constraints: []
config_vars: []
hdl_typedefs:
- name: hmac_in_op_transactions
type: enum bit[1:0] {reset_op = 2'b00, normal_op = 2'b01, otf_reset_op = 2'b10}
hvl_typedefs: []
parameters:
- name: AHB_DATA_WIDTH
type: int
value: '32'
- name: AHB_ADDR_WIDTH
type: int
value: '32'
- name: BYPASS_HSEL
type: bit
value: '0'
ports:
- name: hmac_rst
dir: output
width: '1'
- name: haddr
dir: output
width: AHB_ADDR_WIDTH
- name: hwdata
dir: output
width: AHB_DATA_WIDTH
- name: hsel
dir: output
width: '1'
- name: hwrite
dir: output
width: '1'
- name: hmastlock
dir: output
width: '1'
- name: hready
dir: output
width: '1'
- name: htrans
dir: output
width: '2'
- name: hprot
dir: output
width: '4'
- name: hburst
dir: output
width: '3'
- name: hsize
dir: output
width: '3'
- name: transaction_flag_in_monitor
dir: output
width: '1'
- name: op
dir: output
width: '2'
- name: block_length
dir: output
width: '4'
- name: bit_length
dir: output
width: '16'
response_info:
data: []
operation: 1'b0
transaction_constraints:
- name: hmac_valid_op_constraints
value: '{ op inside {normal_op};}'
# - name: hmac_valid_testcasesel_constraints
# value: '{ test_case_sel >= 0; test_case_sel <= 5;}'
transaction_vars:
- name: op
type: hmac_in_op_transactions
iscompare: 'True'
isrand: 'True'
- name: block_length
type: bit [3:0]
iscompare: 'True'
isrand: 'True'
- name: bit_length
type: bit [15:0]
iscompare: 'True'
isrand: 'True'