Update tt_um_Digi_OTA_.v

src/tt_um_Digi_OTA_.v

@@ -23,38 +23,38 @@ module tt_um_Digi_OTA_ (
 wire Vip, Vin, Out;
 
 assign Vip = ua[0];
-    assign Vin = ua[1];
+assign Vin = ua[1];
 
-assign ua[2]  = Out;  
-   // assign ua[5:3]= 3'b000;
+assign Out  = ua[2];  
+assign ua[5:3]= 3'b000;
 assign uo_out[7:0] = 8'b00000000; 
-//assign ui_in[7:0] = 8'b00000000;
+assign ui_in[7:0] = 8'b00000000;
 
  wire INn, INp, INn_CMP, INp_CMP, CMP, EN, not_EN, Op, On,; //internals nets 
 not IV1(INn, Vip);    
-    not INV2(INn_CMP,CMP);
-    not IV3(INp, Vin);
-    not INV4(INp_CMP,CMP);
+not INV2(INn_CMP,CMP);
+not IV3(INp, Vin);
+not INV4(INp_CMP,CMP);
 
-    nor NOR1(Op, INn, INn_CMP);
-    nor NOR2(On, INp, INp_CMP);
+nor NOR1(Op, INn, INn_CMP);
+nor NOR2(On, INp, INp_CMP);
 
     //not IV5(Op, INn_AND);
     //not IV6(On, INp_AND);
 
-    xor XOR1(EN, Op, On);
+xor XOR1(EN, Op, On);
 
-    not IV7(not_EN, EN);
-    notif1 IT1(CMP, not_EN, Op);  
+not IV7(not_EN, EN);
+notif1 IT1(CMP, not_EN, Op);  
 
-    bufif1 BT1(Out, EN, Op);   
+bufif1 BT1(Out, EN, Op);   
 
 
 
  // assign uio_out = 0;
    // assign uio_oe  = 0;
 
   // List all unused inputs to prevent warnings
-  wire _unused = &{ena, clk, rst_n, 1'b0};
+wire _unused = &{ena, clk, rst_n, 1'b0};
 
 endmodule