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max10_8.qsf
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max10_8.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.0.2 Build 209 09/17/2014 SJ Web Edition
# Date created = 10:11:43 April 16, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# max10_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08SAE144C8GES
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:11:43 APRIL 16, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_location_assignment PIN_141 -to FTDI_BD0
set_location_assignment PIN_140 -to FTDI_BD1
set_location_assignment PIN_138 -to FTDI_BD2
set_location_assignment PIN_136 -to FTDI_BD3
set_location_assignment PIN_26 -to CLK100MHZ
set_location_assignment PIN_129 -to KEY0
set_location_assignment PIN_25 -to KEY1
set_location_assignment PIN_27 -to SDRAM_DQ[15]
set_location_assignment PIN_28 -to SDRAM_DQ[14]
set_location_assignment PIN_29 -to SDRAM_DQ[13]
set_location_assignment PIN_30 -to SDRAM_DQ[12]
set_location_assignment PIN_32 -to SDRAM_DQ[11]
set_location_assignment PIN_33 -to SDRAM_DQ[10]
set_location_assignment PIN_38 -to SDRAM_DQ[9]
set_location_assignment PIN_39 -to SDRAM_DQ[8]
set_location_assignment PIN_66 -to SDRAM_DQ[7]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_70 -to SDRAM_DQ[5]
set_location_assignment PIN_74 -to SDRAM_DQ[4]
set_location_assignment PIN_75 -to SDRAM_DQ[3]
set_location_assignment PIN_76 -to SDRAM_DQ[2]
set_location_assignment PIN_77 -to SDRAM_DQ[1]
set_location_assignment PIN_78 -to SDRAM_DQ[0]
set_location_assignment PIN_57 -to SDRAM_A[0]
set_location_assignment PIN_58 -to SDRAM_A[1]
set_location_assignment PIN_59 -to SDRAM_A[2]
set_location_assignment PIN_60 -to SDRAM_A[3]
set_location_assignment PIN_44 -to SDRAM_A[4]
set_location_assignment PIN_45 -to SDRAM_A[5]
set_location_assignment PIN_46 -to SDRAM_A[6]
set_location_assignment PIN_47 -to SDRAM_A[7]
set_location_assignment PIN_48 -to SDRAM_A[8]
set_location_assignment PIN_50 -to SDRAM_A[9]
set_location_assignment PIN_56 -to SDRAM_A[10]
set_location_assignment PIN_52 -to SDRAM_A[11]
set_location_assignment PIN_65 -to SDRAM_LDQM
set_location_assignment PIN_41 -to SDRAM_UDQM
set_location_assignment PIN_54 -to SDRAM_BA0
set_location_assignment PIN_55 -to SDRAM_BA1
set_location_assignment PIN_61 -to SDRAM_RAS
set_location_assignment PIN_62 -to SDRAM_CAS
set_location_assignment PIN_64 -to SDRAM_WE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_79 -to LED[7]
set_location_assignment PIN_80 -to LED[6]
set_location_assignment PIN_81 -to LED[5]
set_location_assignment PIN_84 -to LED[4]
set_location_assignment PIN_85 -to LED[3]
set_location_assignment PIN_86 -to LED[2]
set_location_assignment PIN_87 -to LED[1]
set_location_assignment PIN_88 -to LED[0]
set_location_assignment PIN_131 -to TMDS[7]
set_location_assignment PIN_130 -to TMDS[6]
set_location_assignment PIN_127 -to TMDS[5]
set_location_assignment PIN_124 -to TMDS[4]
set_location_assignment PIN_123 -to TMDS[3]
set_location_assignment PIN_122 -to TMDS[2]
set_location_assignment PIN_121 -to TMDS[1]
set_location_assignment PIN_120 -to TMDS[0]
set_location_assignment PIN_17 -to FTD[0]
set_location_assignment PIN_135 -to FTD[1]
set_location_assignment PIN_132 -to FTD[2]
set_location_assignment PIN_134 -to FTD[3]
set_location_assignment PIN_24 -to FTD[4]
set_location_assignment PIN_22 -to FTD[5]
set_location_assignment PIN_21 -to FTD[6]
set_location_assignment PIN_15 -to FTD[7]
set_location_assignment PIN_14 -to FTC[0]
set_location_assignment PIN_13 -to FTC[1]
set_location_assignment PIN_12 -to FTC[2]
set_location_assignment PIN_11 -to FTC[3]
set_location_assignment PIN_10 -to FTC[4]
set_location_assignment PIN_8 -to FTC[5]
set_location_assignment PIN_7 -to FTC[6]
set_location_assignment PIN_6 -to FTC[7]
set_location_assignment PIN_89 -to IO[0]
set_location_assignment PIN_90 -to IO[1]
set_location_assignment PIN_91 -to IO[2]
set_location_assignment PIN_92 -to IO[3]
set_location_assignment PIN_93 -to IO[4]
set_location_assignment PIN_96 -to IO[5]
set_location_assignment PIN_97 -to IO[6]
set_location_assignment PIN_98 -to IO[7]
set_location_assignment PIN_99 -to IO[8]
set_location_assignment PIN_100 -to IO[9]
set_location_assignment PIN_101 -to IO[10]
set_location_assignment PIN_102 -to IO[11]
set_location_assignment PIN_105 -to IO[12]
set_location_assignment PIN_106 -to IO[13]
set_location_assignment PIN_110 -to IO[14]
set_location_assignment PIN_111 -to IO[15]
set_location_assignment PIN_112 -to IO[16]
set_location_assignment PIN_113 -to IO[17]
set_location_assignment PIN_119 -to IO[18]
set_location_assignment PIN_118 -to IO[19]
set_location_assignment PIN_114 -to RESERVED
set_location_assignment PIN_126 -to BOOT_SEL
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ENABLE_OCT_DONE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BOOT_SEL
set_global_assignment -name QIP_FILE mypll.qip
set_global_assignment -name CDF_FILE output_files/Chain2.cdf
set_global_assignment -name CDF_FILE output_files/Chain3.cdf
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_FILE serial.v
set_global_assignment -name SIGNALTAP_FILE output_files/stp2.stp
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY1
set_instance_assignment -name IO_STANDARD "2.5 V SCHMITT TRIGGER" -to KEY0
set_instance_assignment -name IO_STANDARD "2.5 V SCHMITT TRIGGER" -to KEY1
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_instance_assignment -name FAST_INPUT_REGISTER ON -to IO[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to IO[6]
set_instance_assignment -name IO_STANDARD "2.5 V SCHMITT TRIGGER" -to IO[7]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top