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a314d.cc
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a314d.cc
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/*
* Copyright (c) 2018-2023 Niklas Ekström
*/
#include <arpa/inet.h>
#include <linux/spi/spidev.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <netinet/in.h>
#include <netinet/tcp.h>
#include <sys/epoll.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <sys/socket.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <ctype.h>
#include <errno.h>
#include <fcntl.h>
#include <signal.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
#include <algorithm>
#include <list>
#include <string>
#include <vector>
#if !defined(MODEL_TD) && !defined(MODEL_FE) && !defined(MODEL_CP)
#error Need to define MODEL_TD, MODEL_FE or MODEL_CP
#elif defined(MODEL_TD) && defined(MODEL_FE) || defined(MODEL_TD) && defined(MODEL_CP) || defined(MODEL_FE) && defined(MODEL_CP)
#error The MODEL_XX flags cannot be combined
#endif
#define LOGLEVEL_TRACE 10
#define LOGLEVEL_DEBUG 20
#define LOGLEVEL_INFO 30
#define LOGLEVEL_WARNING 40
#define LOGLEVEL_ERROR 50
static int loglevel = LOGLEVEL_INFO;
#define logger_trace(...) do { if (loglevel <= LOGLEVEL_TRACE) fprintf(stdout, __VA_ARGS__); } while (0)
#define logger_debug(...) do { if (loglevel <= LOGLEVEL_DEBUG) fprintf(stdout, __VA_ARGS__); } while (0)
#define logger_info(...) do { if (loglevel <= LOGLEVEL_INFO) fprintf(stdout, __VA_ARGS__); } while (0)
#define logger_warning(...) do { if (loglevel <= LOGLEVEL_WARNING) fprintf(stdout, __VA_ARGS__); } while (0)
#define logger_error(...) do { if (loglevel <= LOGLEVEL_ERROR) fprintf(stderr, __VA_ARGS__); } while (0)
// Packets that are communicated across physical channels (A2R and R2A).
#define PKT_CONNECT 4
#define PKT_CONNECT_RESPONSE 5
#define PKT_DATA 6
#define PKT_EOS 7
#define PKT_RESET 8
// Valid responses for PKT_CONNECT_RESPONSE.
#define CONNECT_OK 0
#define CONNECT_UNKNOWN_SERVICE 3
// Messages that are communicated between driver and client.
#define MSG_REGISTER_REQ 1
#define MSG_REGISTER_RES 2
#define MSG_DEREGISTER_REQ 3
#define MSG_DEREGISTER_RES 4
#define MSG_READ_MEM_REQ 5
#define MSG_READ_MEM_RES 6
#define MSG_WRITE_MEM_REQ 7
#define MSG_WRITE_MEM_RES 8
#define MSG_CONNECT 9
#define MSG_CONNECT_RESPONSE 10
#define MSG_DATA 11
#define MSG_EOS 12
#define MSG_RESET 13
#define MSG_SUCCESS 1
#define MSG_FAIL 0
#define R2A_TAIL_UPDATED 1
#define A2R_HEAD_UPDATED 2
// TODO: These constants should be the same for both TD/FE and CP.
// Need to update a314.device in order to change these.
#if defined(MODEL_TD)
// Offset relative to communication area for queue pointers.
#define A2R_TAIL_OFFSET 0
#define R2A_HEAD_OFFSET 1
#define R2A_TAIL_OFFSET 2
#define A2R_HEAD_OFFSET 3
// Addresses of fixed data structures in shared memory.
#define CAP_BASE 0
#define A2R_BASE 4
#define R2A_BASE 260
#elif defined(MODEL_FE)
// Offset relative to communication area for queue pointers.
#define A2R_TAIL_OFFSET 0
#define R2A_HEAD_OFFSET 1
#define R2A_TAIL_OFFSET 2
#define A2R_HEAD_OFFSET 3
// Addresses of fixed data structures in shared memory.
#define HANDSHAKE_BASE 0
#define CAP_BASE 4
#define A2R_BASE 8
#define R2A_BASE 264
#elif defined(MODEL_CP)
// Offset relative to communication area for queue pointers.
#define R2A_TAIL_OFFSET 0
#define A2R_HEAD_OFFSET 1
#define A2R_TAIL_OFFSET 2
#define R2A_HEAD_OFFSET 3
// Addresses of fixed data structures in shared memory.
#define A2R_BASE 0
#define R2A_BASE 256
#define CAP_BASE 512
#endif
#if defined(MODEL_TD)
#define IRQ_GPIO 25
#define IRQ_GPIO_EDGE GPIO_V2_LINE_FLAG_EDGE_RISING | GPIO_V2_LINE_FLAG_EDGE_FALLING
#elif defined(MODEL_FE)
#define IRQ_GPIO 23
#define IRQ_GPIO_EDGE GPIO_V2_LINE_FLAG_EDGE_RISING
#elif defined(MODEL_CP)
#define IRQ_GPIO 2
#define IRQ_GPIO_EDGE GPIO_V2_LINE_FLAG_EDGE_RISING
#endif
#if defined(MODEL_TD)
// SPI commands.
#define READ_SRAM_CMD 0
#define WRITE_SRAM_CMD 1
#define READ_CMEM_CMD 2
#define WRITE_CMEM_CMD 3
#define SPI_PROTO_VER_CMD 255
#define READ_SRAM_HDR_LEN 4
// Addresses to variables in CMEM.
#define BASE_ADDRESS_LEN 6
#define R_EVENTS_ADDRESS 12
#define R_ENABLE_ADDRESS 13
#define A_EVENTS_ADDRESS 14
#define A_ENABLE_ADDRESS 15
// Events that are communicated via IRQ from Amiga to Raspberry.
#define R_EVENT_A2R_TAIL 1
#define R_EVENT_R2A_HEAD 2
#define R_EVENT_BASE_ADDRESS 4
// Events that are communicated from Raspberry to Amiga.
#define A_EVENT_R2A_TAIL 1
#define A_EVENT_A2R_HEAD 2
#elif defined(MODEL_FE)
#define PIN_D(x) (4 + x)
#define PIN_WR 20
#define PIN_REQ 21
#define PIN_ACK 22
#define PIN_IRQ 23
#define PIN_A(x) (24 + x)
#define GPIO_DIR_0_MASK 0x3ffff000
#define GPIO_DIR_0_DIN 0x00000000
#define GPIO_DIR_0_DOUT 0x09249000
#define GPIO_DIR_1_MASK 0x3fffffff
#define GPIO_DIR_1_DIN 0x00000000
#define GPIO_DIR_1_DOUT 0x09249249
#define GPIO_DIR_2_MASK 0x00ffffff
#define GPIO_DIR_2 0x00249009
#define GPIO_PULL_NONE 0
#define GPIO_PULL_DOWN 1
#define GPIO_PULL_UP 2
#define REG_SRAM_BYTE 0
#define REG_SRAM_WORD 1
#define REG_ADDR_LO 2
#define REG_ADDR_HI 3
#define REG_INT_REQ 4
#define REG_INT_ENA 5
#define REG_CA_BASE_ADDR 6
#define IRQ_SET 0x8000
#define IRQ_CLR 0x0000
#define IRQ_R2A_TAIL 0x0001
#define IRQ_A2R_HEAD 0x0002
#define IRQ_A2R_TAIL 0x0004
#define IRQ_R2A_HEAD 0x0008
#define IRQ_BASE_ADDRESS 0x0010
#elif defined(MODEL_CP)
#define PIN_IRQ 2
#define PIN_CLK 4
#define PIN_REQ 14
#define PIN_ACK 15
#define PIN_D(x) (16 + x)
#define PIN_A(x) (24 + x)
#define PIN_WR 27
#define PINS_OUT ((0xff << PIN_D(0)) | (3 << PIN_A(0)) | (1 << PIN_WR) | (1 << PIN_REQ))
#define PINS_OUT_NOT_WR ((0xff << PIN_D(0)) | (3 << PIN_A(0)) | (1 << PIN_REQ))
#define GPIO_DIR_0 0x08004000
#define GPIO_DIR_0_MASK 0x3f0071c0
#define GPIO_DIR_1_DIN 0x00001009
#define GPIO_DIR_1_DOUT 0x09241009
#define GPIO_DIR_2_DIN 0x08209000
#define GPIO_DIR_2_DOUT 0x08209249
#define GPIO_PULL_NONE 0
#define GPIO_PULL_DOWN 1
#define GPIO_PULL_UP 2
#define REG_SRAM 0
#define REG_IRQ 1
#define REG_ADDR_LO 2
#define REG_ADDR_HI 3
#define REG_IRQ_SET 0x80
#define REG_IRQ_CLR 0x00
#define REG_IRQ_PI 0x02
#define REG_IRQ_CP 0x01
#endif
// Global variables.
static sigset_t original_sigset;
static uint8_t tx_buf[65536];
static uint8_t rx_buf[65536];
static volatile unsigned int *gpio;
#if defined(MODEL_TD)
static uint8_t mode = SPI_CS_HIGH;
static uint8_t bits = 8;
static uint32_t speed = 67000000;
static int spi_fd = -1;
static int spi_proto_ver = 0;
#elif defined(MODEL_FE)
static unsigned int current_address;
static int current_dir = 0; // 0 = input, 1 = output.
#elif defined(MODEL_CP)
static unsigned short current_address;
static int current_dir = 0; // 0 = input, 1 = output.
static bool read_a314_magic = false;
static int restart_counter;
#endif
static int gpio_irq_fd = -1;
static bool auto_clear_irq = false;
static time_t auto_clear_irq_after;
static int server_socket = -1;
static int epfd = -1;
static bool have_base_address = false;
static unsigned int base_address = 0;
#if defined(MODEL_TD) || defined(MODEL_FE)
#define BASE_ADDRESS base_address
#elif defined(MODEL_CP)
#define BASE_ADDRESS 0
#endif
static uint8_t channel_status[4];
static uint8_t channel_status_updated = 0;
static uint8_t recv_buf[256];
static uint8_t send_buf[256];
struct LogicalChannel;
struct ClientConnection;
#pragma pack(push, 1)
struct MessageHeader
{
uint32_t length;
uint32_t stream_id;
uint8_t type;
}; //} __attribute__((packed));
#pragma pack(pop)
struct MessageBuffer
{
int pos;
std::vector<uint8_t> data;
};
struct RegisteredService
{
std::string name;
ClientConnection *cc;
};
struct PacketBuffer
{
int type;
std::vector<uint8_t> data;
};
struct ClientConnection
{
int fd;
int next_stream_id;
int bytes_read;
MessageHeader header;
std::vector<uint8_t> payload;
std::list<MessageBuffer> message_queue;
std::list<LogicalChannel*> associations;
};
struct LogicalChannel
{
int channel_id;
ClientConnection *association;
int stream_id;
bool got_eos_from_ami;
bool got_eos_from_client;
std::list<PacketBuffer> packet_queue;
};
static void remove_association(LogicalChannel *ch);
static void clear_packet_queue(LogicalChannel *ch);
static void create_and_enqueue_packet(LogicalChannel *ch, uint8_t type, uint8_t *data, uint8_t length);
static std::list<ClientConnection> connections;
static std::list<RegisteredService> services;
static std::list<LogicalChannel> channels;
static std::list<LogicalChannel*> send_queue;
struct OnDemandStart
{
std::string service_name;
std::string program;
std::vector<std::string> arguments;
};
std::vector<OnDemandStart> on_demand_services;
static void load_config_file(const char *filename)
{
FILE *f = fopen(filename, "rt");
if (f == nullptr)
return;
char line[256];
std::vector<char *> parts;
while (fgets(line, 256, f) != nullptr)
{
char org_line[256];
strcpy(org_line, line);
bool in_quotes = false;
int start = 0;
for (int i = 0; i < 256; i++)
{
if (line[i] == 0)
{
if (start < i)
parts.push_back(&line[start]);
break;
}
else if (line[i] == '"')
{
line[i] = 0;
if (in_quotes)
parts.push_back(&line[start]);
in_quotes = !in_quotes;
start = i + 1;
}
else if (isspace(line[i]) && !in_quotes)
{
line[i] = 0;
if (start < i)
parts.push_back(&line[start]);
start = i + 1;
}
}
if (parts.size() >= 2)
{
on_demand_services.emplace_back();
auto &e = on_demand_services.back();
e.service_name = parts[0];
e.program = parts[1];
for (int i = 1; i < parts.size(); i++)
e.arguments.push_back(std::string(parts[i]));
}
else if (parts.size() != 0)
logger_warning("Invalid number of columns in configuration file line: %s\n", org_line);
parts.clear();
}
fclose(f);
if (on_demand_services.empty())
logger_warning("No registered services\n");
}
#if defined(MODEL_TD)
static int init_spi()
{
spi_fd = open("/dev/spidev0.0", O_RDWR | O_CLOEXEC);
if (spi_fd < 0)
return -1;
int ret = ioctl(spi_fd, SPI_IOC_WR_MODE, &mode);
ret |= ioctl(spi_fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
ret |= ioctl(spi_fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
if (ret != 0)
return ret;
return 0;
}
static void shutdown_spi()
{
if (spi_fd != -1)
close(spi_fd);
}
static int check_spidev_bufsiz()
{
int fd = open("/sys/module/spidev/parameters/bufsiz", O_RDONLY);
if (fd == -1)
return -1;
char buf[32];
auto actual = read(fd, buf, strlen(buf));
close(fd);
if (strncmp(buf, "65536", actual) != 0)
return -2;
return 0;
}
static int spi_transfer(int len)
{
struct spi_ioc_transfer tr =
{
.tx_buf = (uintptr_t)tx_buf,
.rx_buf = (uintptr_t)rx_buf,
.len = (uint32_t)len,
.speed_hz = speed,
.delay_usecs = 0,
.bits_per_word = bits,
.cs_change = 0,
};
return ioctl(spi_fd, SPI_IOC_MESSAGE(1), &tr);
}
static int spi_protocol_version()
{
tx_buf[0] = (uint8_t)SPI_PROTO_VER_CMD;
tx_buf[1] = 0;
spi_transfer(2);
logger_trace("SPI protocol version = %d\n", rx_buf[1]);
return (int)rx_buf[1];
}
static void spi_read_shm_rxbuf(unsigned int address, unsigned int length)
{
logger_trace("SPI read mem address = %d length = %d\n", address, length);
unsigned int header;
if (spi_proto_ver == 1)
header = (READ_SRAM_CMD << 21) | (address & 0x1fffff);
else
header = (READ_SRAM_CMD << 20) | (address & 0xfffff);
tx_buf[0] = (uint8_t)((header >> 16) & 0xff);
tx_buf[1] = (uint8_t)((header >> 8) & 0xff);
tx_buf[2] = (uint8_t)(header & 0xff);
tx_buf[3] = 0;
spi_transfer(length + 4);
}
static void spi_read_shm(unsigned char *data, unsigned int address, unsigned int length)
{
spi_read_shm_rxbuf(address, length);
memcpy(data, &rx_buf[READ_SRAM_HDR_LEN], length);
}
static void spi_write_shm(unsigned int address, uint8_t *buf, unsigned int length)
{
logger_trace("SPI write mem address = %d length = %d\n", address, length);
unsigned int header;
if (spi_proto_ver == 1)
header = (WRITE_SRAM_CMD << 21) | (address & 0x1fffff);
else
header = (WRITE_SRAM_CMD << 20) | (address & 0xfffff);
tx_buf[0] = (uint8_t)((header >> 16) & 0xff);
tx_buf[1] = (uint8_t)((header >> 8) & 0xff);
tx_buf[2] = (uint8_t)(header & 0xff);
memcpy(&tx_buf[3], buf, length);
spi_transfer(length + 3);
}
static uint8_t spi_read_cmem(unsigned int address)
{
if (spi_proto_ver == 1)
tx_buf[0] = (uint8_t)((READ_CMEM_CMD << 5) | (address & 0xf));
else
tx_buf[0] = (uint8_t)((READ_CMEM_CMD << 4) | (address & 0xf));
tx_buf[1] = 0;
spi_transfer(2);
logger_trace("SPI read cmem, address = %d, returned = %d\n", address, rx_buf[1]);
return rx_buf[1];
}
static void spi_write_cmem(unsigned int address, unsigned int data)
{
logger_trace("SPI write cmem, address = %d, data = %d\n", address, data);
if (spi_proto_ver == 1)
tx_buf[0] = (uint8_t)((WRITE_CMEM_CMD << 5) | (address & 0xf));
else
tx_buf[0] = (uint8_t)((WRITE_CMEM_CMD << 4) | (address & 0xf));
tx_buf[1] = (uint8_t)(data & 0xf);
spi_transfer(2);
}
static uint8_t spi_ack_irq()
{
logger_trace("SPI ack_irq\n");
return spi_read_cmem(R_EVENTS_ADDRESS);
}
static void spi_read_base_address()
{
have_base_address = false;
unsigned int ba1 = 0;
for (int i = 0; i < BASE_ADDRESS_LEN; i++)
ba1 |= spi_read_cmem(i) << (i * 4);
if ((ba1 & 1) == 1)
{
unsigned int ba2 = 0;
for (int i = 0; i < BASE_ADDRESS_LEN; i++)
ba2 |= spi_read_cmem(i) << (i * 4);
if (ba1 == ba2)
{
have_base_address = true;
base_address = ba1 & ~1;
}
}
}
#define read_shm spi_read_shm
#define write_shm spi_write_shm
#endif
#if defined(MODEL_FE) || defined(MODEL_CP)
static int create_dev_gpiomem_mapping()
{
int fd = open("/dev/gpiomem", O_RDWR | O_SYNC);
if (fd < 0)
{
logger_error("Unable to open /dev/gpiomem\n");
return -1;
}
void *gpio_map = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
close(fd);
if (gpio_map == MAP_FAILED)
{
logger_error("mmap failed, errno = %d\n", errno);
return -1;
}
gpio = (volatile unsigned int *)gpio_map;
return 0;
}
static void set_gpio_pull_mode(int mask, int mode)
{
*(gpio + 37) = mode;
usleep(50);
*(gpio + 38) = mask;
usleep(50);
*(gpio + 38) = 0;
*(gpio + 37) = 0;
usleep(50);
}
#endif
#if defined(MODEL_FE)
static inline void set_dir_read()
{
if (current_dir == 1)
{
*(gpio + 0) = (*(gpio + 0) & ~GPIO_DIR_0_MASK) | GPIO_DIR_0_DIN;
*(gpio + 1) = GPIO_DIR_1_DIN;
current_dir = 0;
}
}
static inline void set_dir_write()
{
if (current_dir == 0)
{
*(gpio + 0) = (*(gpio + 0) & ~GPIO_DIR_0_MASK) | GPIO_DIR_0_DOUT;
*(gpio + 1) = GPIO_DIR_1_DOUT;
current_dir = 1;
}
}
static unsigned int read_sram_reg(unsigned int reg)
{
set_dir_read();
*(gpio + 7) = (reg << PIN_A(0)) | (1 << PIN_REQ);
// Delay so that the ACK pin is sure to be negated after previous access.
*(gpio + 7) = 0;
*(gpio + 7) = 0;
*(gpio + 7) = 0;
*(gpio + 7) = 0;
// Additional delay to hopefully do only one read when there is no contention.
*(gpio + 7) = 0;
*(gpio + 7) = 0;
*(gpio + 7) = 0;
unsigned int value;
while (!((value = *(gpio + 13)) & (1 << PIN_ACK)))
;
value = (value >> PIN_D(0)) & 0xffff;
*(gpio + 10) = (1 << PIN_REQ);
*(gpio + 10) = (15 << PIN_A(0)) | (1 << PIN_WR) | (0xffff << PIN_D(0));
return value;
}
static void write_sram_reg(unsigned int reg, unsigned int value)
{
set_dir_write();
*(gpio + 7) = (reg << PIN_A(0)) | (1 << PIN_REQ) | (1 << PIN_WR) | ((value & 0xffff) << PIN_D(0));
// Delay so that the ACK pin is sure to be negated after previous access.
*(gpio + 7) = 0;
*(gpio + 7) = 0;
*(gpio + 7) = 0;
*(gpio + 7) = 0;
// Additional delay to hopefully do only one read when there is no contention.
*(gpio + 7) = 0;
*(gpio + 7) = 0;
*(gpio + 7) = 0;
while (!(*(gpio + 13) & (1 << PIN_ACK)))
;
*(gpio + 10) = (1 << PIN_REQ);
*(gpio + 10) = (15 << PIN_A(0)) | (1 << PIN_WR) | (0xffff << PIN_D(0));
}
static unsigned int read_reg(unsigned int reg)
{
set_dir_read();
*(gpio + 7) = (reg << PIN_A(0)) | (1 << PIN_REQ);
*(gpio + 7) = 0;
*(gpio + 7) = 0;
*(gpio + 7) = 0;
unsigned int value = *(gpio + 13);
value = (value >> PIN_D(0)) & 0xffff;
*(gpio + 10) = (1 << PIN_REQ);
*(gpio + 7) = 0;
*(gpio + 10) = (15 << PIN_A(0)) | (1 << PIN_WR) | (0xffff << PIN_D(0));
return value;
}
static void write_reg(unsigned int reg, unsigned int value)
{
set_dir_write();
*(gpio + 7) = (reg << PIN_A(0)) | (1 << PIN_REQ) | (1 << PIN_WR) | ((value & 0xffff) << PIN_D(0));
*(gpio + 7) = 0;
*(gpio + 10) = (1 << PIN_REQ);
*(gpio + 7) = 0;
*(gpio + 10) = (15 << PIN_A(0)) | (1 << PIN_WR) | (0xffff << PIN_D(0));
}
static void set_address(unsigned int address)
{
if ((address & 0xffff) != (current_address & 0xffff))
write_reg(REG_ADDR_LO, address & 0xffff);
if (((address >> 16) & 0x3) != ((current_address >> 16) & 0x3))
write_reg(REG_ADDR_HI, (address >> 16) & 0x3);
current_address = address;
}
static void gpio_read_shm(unsigned char *data, unsigned int address, unsigned int length)
{
set_address(address);
current_address = (address + length) & 0x3ffff;
unsigned int v;
if (address & 1)
{
v = read_sram_reg(REG_SRAM_BYTE);
*data++ = v & 0xff;
length--;
}
while (length >= 2)
{
v = read_sram_reg(REG_SRAM_WORD);
*data++ = (v >> 8) & 0xff;
*data++ = v & 0xff;
length -= 2;
}
if (length)
{
v = read_sram_reg(REG_SRAM_BYTE);
*data++ = (v >> 8) & 0xff;
}
}
static void gpio_write_shm(unsigned int address, unsigned char *data, unsigned int length)
{
set_address(address);
current_address = (address + length) & 0x3ffff;
unsigned int v;
if (address & 1)
{
v = *data++;
write_sram_reg(REG_SRAM_BYTE, v);
length--;
}
while (length >= 2)
{
v = ((*data++) << 8) | (*data++);
write_sram_reg(REG_SRAM_WORD, v);
length -= 2;
}
if (length)
{
v = (*data++) << 8;
write_sram_reg(REG_SRAM_BYTE, v);
}
}
#define write_shm gpio_write_shm
#define read_shm gpio_read_shm
static int init_gpio()
{
if (create_dev_gpiomem_mapping())
return -1;
// Set pin directions.
*(gpio + 0) = (*(gpio + 0) & ~GPIO_DIR_0_MASK) | GPIO_DIR_0_DIN;
*(gpio + 1) = (*(gpio + 1) & ~GPIO_DIR_1_MASK) | GPIO_DIR_1_DIN;
*(gpio + 2) = (*(gpio + 2) & ~GPIO_DIR_2_MASK) | GPIO_DIR_2;
*(gpio + 10) = 0x0ffffff0;
set_gpio_pull_mode((1 << PIN_ACK) | (1 << PIN_IRQ), GPIO_PULL_DOWN);
set_gpio_pull_mode((15 << PIN_A(0)) | (1 << PIN_REQ) | (1 << PIN_WR) | (0xffff << PIN_D(0)), GPIO_PULL_NONE);
current_dir = 0;
// Set address pointer.
write_reg(REG_ADDR_LO, 0);
write_reg(REG_ADDR_HI, 0);
current_address = 0;
return 0;
}
static void shutdown_gpio()
{
// Let Linux take care of this.
}
#elif defined(MODEL_CP)
static void gpio_write_reg(unsigned int reg, unsigned int value)
{
if (current_dir == 0)
{
*(gpio + 7) = (1 << PIN_WR);
*(gpio + 1) = GPIO_DIR_1_DOUT;
*(gpio + 2) = GPIO_DIR_2_DOUT;
current_dir = 1;
}
while ((*(gpio + 13) & (1 << PIN_ACK)))
;
*(gpio + 7) = ((value & 0xff) << PIN_D(0)) | (reg << PIN_A(0)) | (1 << PIN_REQ);
while (!(*(gpio + 13) & (1 << PIN_ACK)))
;
*(gpio + 10) = PINS_OUT_NOT_WR;
}
static unsigned int gpio_read_reg(unsigned int reg)
{
if (current_dir == 1)
{
*(gpio + 1) = GPIO_DIR_1_DIN;
*(gpio + 2) = GPIO_DIR_2_DIN;
*(gpio + 10) = (1 << PIN_WR);
current_dir = 0;
}
while ((*(gpio + 13) & (1 << PIN_ACK)))
;
*(gpio + 7) = (reg << PIN_A(0)) | (1 << PIN_REQ);
unsigned int value;
while (!((value = *(gpio + 13)) & (1 << PIN_ACK)))
;
value = (value >> PIN_D(0)) & 0xff;
*(gpio + 10) = PINS_OUT_NOT_WR;
return value;
}
static void clear_pi_irq()
{
gpio_write_reg(REG_IRQ, REG_IRQ_CLR | REG_IRQ_PI);
}
static void set_cp_irq()
{
gpio_write_reg(REG_IRQ, REG_IRQ_SET | REG_IRQ_CP);
}
static void clear_cp_irq()
{
gpio_write_reg(REG_IRQ, REG_IRQ_CLR | REG_IRQ_CP);
}
static void gpio_set_address(unsigned short address)
{
if ((address & 0xff) != (current_address & 0xff))
gpio_write_reg(REG_ADDR_LO, address & 0xff);
if (((address >> 8) & 0xff) != ((current_address >> 8) & 0xff))
gpio_write_reg(REG_ADDR_HI, (address >> 8) & 0xff);
current_address = address;
}
static void gpio_write_shm(unsigned short address, unsigned char *data, unsigned short length)
{
gpio_set_address(address);
for (int i = 0; i < length; i++)
gpio_write_reg(REG_SRAM, *data++);
current_address += length;
}
static void gpio_read_shm(unsigned char *data, unsigned short address, unsigned short length)
{
gpio_set_address(address);
for (int i = 0; i < length; i++)
*data++ = gpio_read_reg(REG_SRAM);
current_address += length;
}
#define write_shm gpio_write_shm
#define read_shm gpio_read_shm
static int init_gpio()
{
if (create_dev_gpiomem_mapping())
return -1;
// Set pin directions.
// Inputs: PIN_IRQ, PIN_ACK, PIN_D(x), unused pins.
// Outputs: PIN_REQ, PIN_A(x), PIN_WR, pin 29 (connects to LED on Pi3).
// Alt0: PIN_CLK.
// Directions of pins 0, 1, 3, 5, 6, 7 are left unchanged.
*(gpio + 0) = (*(gpio + 0) & ~GPIO_DIR_0_MASK) | GPIO_DIR_0;
*(gpio + 1) = GPIO_DIR_1_DIN;
*(gpio + 2) = GPIO_DIR_2_DIN;
set_gpio_pull_mode((1 << PIN_ACK) | (1 << PIN_IRQ), GPIO_PULL_DOWN);
set_gpio_pull_mode(PINS_OUT | (1 << PIN_CLK), GPIO_PULL_NONE);
current_dir = 0;
// Set address pointer.
gpio_write_reg(REG_ADDR_LO, 0);
gpio_write_reg(REG_ADDR_HI, 0);
current_address = 0;
return 0;
}
static void shutdown_gpio()
{
// Let Linux take care of this.
}
#endif
static int init_gpio_irq()
{
int chip_fd = open("/dev/gpiochip0", O_RDWR);
if (chip_fd < 0)
return -1;
struct gpio_v2_line_request line_req = {
.offsets = {IRQ_GPIO},
.consumer = {'a', '3', '1', '4', 'd', 0},
.config = {
.flags = GPIO_V2_LINE_FLAG_INPUT | IRQ_GPIO_EDGE,
},
.num_lines = 1,
};
int err = ioctl(chip_fd, GPIO_V2_GET_LINE_IOCTL, &line_req);
if (err == -1)
return -2;
gpio_irq_fd = line_req.fd;
if (gpio_irq_fd < 0)
return -3;
return 0;
}
static void shutdown_gpio_irq()
{
// No-op, Linux releases resources.
}
static int init_server_socket()
{
server_socket = socket(AF_INET, SOCK_STREAM | SOCK_CLOEXEC, 0);
if (server_socket == -1)
{
logger_error("Failed to create server socket\n");
return -1;
}