From 29285666c65693bba35fded959f0149ca1fdd878 Mon Sep 17 00:00:00 2001 From: Mojtaba Bisheh Niasar Date: Tue, 25 Jul 2023 23:58:40 +0000 Subject: [PATCH] Merged PR 117208: added doe cbc nist test vectors added doe cbc nist test vectors Related work items: #518832 --- .../github-nightly-directed-pipeline.yml | 15 + src/doe/config/compile.yml | 12 + src/doe/config/doe_core_cbc_tb.vf | 38 + src/doe/coverage/config/doe_cm_hier.cfg | 3 + .../tests/directed/doe_cbc_nist_test.yml | 17 + .../doe_nightly_directed_regression.yml | 8 + src/doe/tb/doe_core_cbc_tb.sv | 671 ++++++++++++++++++ 7 files changed, 764 insertions(+) create mode 100644 src/doe/config/doe_core_cbc_tb.vf create mode 100644 src/doe/coverage/config/doe_cm_hier.cfg create mode 100644 src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml create mode 100644 src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml create mode 100644 src/doe/tb/doe_core_cbc_tb.sv diff --git a/etc/pipelines/github-nightly-directed-pipeline.yml b/etc/pipelines/github-nightly-directed-pipeline.yml index f4c7164c6..807893113 100644 --- a/etc/pipelines/github-nightly-directed-pipeline.yml +++ b/etc/pipelines/github-nightly-directed-pipeline.yml @@ -138,6 +138,21 @@ stages: - path: '${WORKSPACE}/Caliptra/src/sha256/stimulus/testsuites/sha256_nightly_directed_regression.yml' - timeout: 60 + - doe_core_cbc_tb: + - display_name: 'DOE_CORE_CBC_TB' + - enabled: true + - configspec_name: 'integration_lib' + - dut: 'doe_core_cbc_tb' + - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/doe/coverage/config/doe_cm_hier.cfg --submit-resource-args RAM/28000' + - testsuites: + - nightly_directed: + - enabled: true + - configspec_name: 'integration_lib' + - dut: 'doe_core_cbc_tb' + - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}' + - path: '${WORKSPACE}/Caliptra/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml' + - timeout: 60 + - soc_ifc_tb: - display_name: 'SOC_IFC_TB' - enabled: true diff --git a/src/doe/config/compile.yml b/src/doe/config/compile.yml index 7b1815664..39c70d8c4 100755 --- a/src/doe/config/compile.yml +++ b/src/doe/config/compile.yml @@ -53,6 +53,18 @@ targets: files: - $COMPILE_ROOT/tb/doe_cbc_tb.sv tops: [doe_cbc_tb] +--- +provides: [doe_core_cbc_tb] +schema_version: 2.4.0 +requires: + - doe_ctrl +targets: + tb: + directories: + - $COMPILE_ROOT/tb + files: + - $COMPILE_ROOT/tb/doe_core_cbc_tb.sv + tops: [doe_core_cbc_tb] global: tool: vcs: diff --git a/src/doe/config/doe_core_cbc_tb.vf b/src/doe/config/doe_core_cbc_tb.vf new file mode 100644 index 000000000..2838f10b9 --- /dev/null +++ b/src/doe/config/doe_core_cbc_tb.vf @@ -0,0 +1,38 @@ ++incdir+${CALIPTRA_ROOT}/src/integration/rtl ++incdir+${CALIPTRA_ROOT}/src/libs/rtl ++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ++incdir+${CALIPTRA_ROOT}/src/doe/rtl ++incdir+${CALIPTRA_ROOT}/src/doe/tb +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh +${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv +${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv +${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv +${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh +${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv +${CALIPTRA_ROOT}/src/doe/tb/doe_core_cbc_tb.sv +${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv +${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg_pkg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_ctrl.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_decipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_encipher_block.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_inv_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_key_mem.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_sbox.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_core_cbc.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_reg.sv +${CALIPTRA_ROOT}/src/doe/rtl/doe_fsm.sv \ No newline at end of file diff --git a/src/doe/coverage/config/doe_cm_hier.cfg b/src/doe/coverage/config/doe_cm_hier.cfg new file mode 100644 index 000000000..bcd0cda31 --- /dev/null +++ b/src/doe/coverage/config/doe_cm_hier.cfg @@ -0,0 +1,3 @@ +begin line+tgl+fsm+cond+branch + +tree doe_core_cbc_tb.dut 0 +end \ No newline at end of file diff --git a/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml b/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml new file mode 100644 index 000000000..8005b2f5c --- /dev/null +++ b/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: doe_cbc_nist_test +seed: 1 \ No newline at end of file diff --git a/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml b/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml new file mode 100644 index 000000000..1af388109 --- /dev/null +++ b/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml @@ -0,0 +1,8 @@ +document: + schema: 1.0 + +contents: + - tests: + tags: ["L0", "directed", "nightly", "DOE"] + paths: + - ${CALIPTRA_ROOT}/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml diff --git a/src/doe/tb/doe_core_cbc_tb.sv b/src/doe/tb/doe_core_cbc_tb.sv new file mode 100644 index 000000000..bd5bcfa55 --- /dev/null +++ b/src/doe/tb/doe_core_cbc_tb.sv @@ -0,0 +1,671 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// doe_core_cbc_tb.sv +// -------- +// DOE testbench for the DOE core CBC. +// +// +//====================================================================== + +module doe_core_cbc_tb(); + +//---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 1; + parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + + + parameter DOE_128_BIT_KEY = 0; + parameter DOE_256_BIT_KEY = 1; + + parameter DOE_DECIPHER = 1'b0; + parameter DOE_ENCIPHER = 1'b1; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [63 : 0] cycle_ctr; + reg [63 : 0] error_ctr; + reg [63 : 0] tc_ctr; + reg [63 : 0] temp_ctr; + + reg clk_tb; + reg reset_n_tb; + reg zeroize_tb; + + logic core_encdec_tb; + logic core_init_tb; + logic core_next_tb; + logic core_ready_tb; + logic [255:0] core_key_tb; + logic core_keylen_tb; + logic [127:0] core_IV_tb; + logic IV_updated_tb; + logic [127:0] core_block_tb; + logic [127:0] core_result_tb; + logic core_valid_tb; + + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + doe_core_cbc dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + + .encdec(core_encdec_tb), + .init_cmd(core_init_tb), + .next_cmd(core_next_tb), + .ready(core_ready_tb), + + .key(core_key_tb), + .keylen(core_keylen_tb), + + .IV(core_IV_tb), + .IV_updated(IV_updated_tb), + + .block_msg(core_block_tb), + .result(core_result_tb), + .result_valid(core_valid_tb) + ); + + + //---------------------------------------------------------------- + // clk_gen + // + // Always running clock generator process. + //---------------------------------------------------------------- + always + begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; + end // clk_gen + + + //---------------------------------------------------------------- + // sys_monitor() + // + // An always running process that creates a cycle counter and + // conditionally displays information about the DUT. + //---------------------------------------------------------------- + always + begin : sys_monitor + #(CLK_PERIOD); + cycle_ctr = cycle_ctr + 1; + end + + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggle reset to put the DUT into a well known state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + $display(""); + end + endtask // reset_dut + + + //---------------------------------------------------------------- + // display_test_results() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_results; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d tests completed - %02d test cases did not complete successfully.", + tc_ctr, error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_results + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + cycle_ctr = 0; + error_ctr = 0; + tc_ctr = 0; + temp_ctr = 0; + + clk_tb = 0; + reset_n_tb = 0; + zeroize_tb = 0; + + core_encdec_tb = 0; + core_init_tb = 0; + core_next_tb = 0; + core_key_tb = 0; + core_keylen_tb = 0; + core_IV_tb = 0; + IV_updated_tb = 0; + core_block_tb = 0; + end + endtask // init_sim + + + //---------------------------------------------------------------- + // wait_ready() + // + // Wait for the ready flag in the dut to be set. + // (Actually we wait for either ready or valid to be set.) + // + // Note: It is the callers responsibility to call the function + // when the dut is actively processing and will in fact at some + // point set the flag. + //---------------------------------------------------------------- + task wait_ready; + begin + #(CLK_PERIOD); + while (core_ready_tb == 0) + begin + #(CLK_PERIOD); + end + end + endtask // wait_ready + + + + //---------------------------------------------------------------- + // init_key() + // + // init the key in the dut by writing the given key and + // key length and then trigger init processing. + //---------------------------------------------------------------- + task init_key(input [255 : 0] key, input key_length); + begin + core_key_tb = key; + core_keylen_tb = key_length; + core_init_tb = 1'b1; + + #CLK_PERIOD; + core_init_tb = 0; + + wait_ready(); + + end + endtask // init_key + + + //---------------------------------------------------------------- + // cbc_mode_single_block_test() + // + // Perform CBC mode encryption or decryption single block test. + //---------------------------------------------------------------- + task cbc_mode_single_block_test(input [7 : 0] tc_number, + input encdec, + input [255 : 0] key, + input key_length, + input [127 : 0] IV, + input [127 : 0] block, + input [127 : 0] expected); + reg [31 : 0] start_time; + reg [31 : 0] end_time; + + begin + $display("*** TC %0d CBC mode test started.", tc_number); + if (encdec==0) + $display("*** DECRYPTION *** "); + else + $display("*** ENCRYPTION *** "); + tc_ctr = tc_ctr + 1; + + start_time = cycle_ctr; + init_key(key, key_length); + + core_IV_tb = IV; + IV_updated_tb = 1'b1; + + #(CLK_PERIOD); + IV_updated_tb = 0; + core_block_tb = block; + core_encdec_tb = encdec; + core_next_tb = 1'b1; + + #(CLK_PERIOD); + core_next_tb = 0; + wait_ready(); + end_time = cycle_ctr - start_time; + $display("*** Single block test processing time = %01d cycles", end_time); + + if (core_result_tb == expected) + begin + $display("*** TC %0d successful.", tc_number); + $display(""); + end + else + begin + $display("*** ERROR: TC %0d NOT successful.", tc_number); + $display("Expected: 0x%032x", expected); + $display("Got: 0x%032x", core_result_tb); + $display(""); + + error_ctr = error_ctr + 1; + end + end + endtask // cbc_mode_single_block_test + + + //---------------------------------------------------------------- + // cbc_mode_double_block_test() + // + // Perform CBC mode encryption or decryption double block test. + //---------------------------------------------------------------- + task cbc_mode_double_block_test(input [7 : 0] tc_number, + input encdec, + input [255 : 0] key, + input key_length, + input [127 : 0] IV, + input [127 : 0] block1, + input [127 : 0] block2, + input [127 : 0] expected1, + input [127 : 0] expected2 + ); + reg [31 : 0] start_time; + reg [31 : 0] end_time; + + begin + $display("*** TC %0d CBC mode DOUBLE BLOCK test started.", tc_number); + tc_ctr = tc_ctr + 1; + + if (encdec==0) + $display("*** DECRYPTION *** "); + else + $display("*** ENCRYPTION *** "); + + start_time = cycle_ctr; + init_key(key, key_length); + + core_IV_tb = IV; + IV_updated_tb = 1'b1; + + #CLK_PERIOD; + IV_updated_tb = 0; + // first block + core_block_tb = block1; + core_encdec_tb = encdec; + core_next_tb = 1'b1; + + #(CLK_PERIOD); + core_next_tb = 0; + wait_ready(); + + if (core_result_tb == expected1) + begin + $display("*** TC %0d first block successful.", tc_number); + $display(""); + end + else + begin + $display("*** ERROR: TC %0d first block NOT successful.", tc_number); + $display("Expected: 0x%032x", expected1); + $display("Got: 0x%032x", core_result_tb); + $display(""); + + error_ctr = error_ctr + 1; + end + + // second block + core_block_tb = block2; + core_next_tb = 1'b1; + + #(CLK_PERIOD); + core_next_tb = 0; + wait_ready(); + + if (core_result_tb == expected2) + begin + $display("*** TC %0d second block successful.", tc_number); + $display(""); + end + else + begin + $display("*** ERROR: TC %0d second block NOT successful.", tc_number); + $display("Expected: 0x%032x", expected2); + $display("Got: 0x%032x", core_result_tb); + $display(""); + + error_ctr = error_ctr + 1; + end + end + endtask // cbc_mode_dual_block_test + + + + + //---------------------------------------------------------------- + // cbc_mode_quadratic_block_test() + // + // Perform CBC mode encryption or decryption quadratic block test. + //---------------------------------------------------------------- + task cbc_mode_quadratic_block_test(input [7 : 0] tc_number, + input encdec, + input [255 : 0] key, + input key_length, + input [127 : 0] IV, + input [127 : 0] block1, + input [127 : 0] block2, + input [127 : 0] block3, + input [127 : 0] block4, + input [127 : 0] expected1, + input [127 : 0] expected2, + input [127 : 0] expected3, + input [127 : 0] expected4 + ); + reg [31 : 0] start_time; + reg [31 : 0] end_time; + + begin + $display("*** TC %0d CBC mode FOUR BLOCK test started.", tc_number); + tc_ctr = tc_ctr + 1; + + + if (encdec==0) + $display("*** DECRYPTION *** "); + else + $display("*** ENCRYPTION *** "); + + start_time = cycle_ctr; + init_key(key, key_length); + + core_IV_tb = IV; + IV_updated_tb = 1'b1; + + #CLK_PERIOD; + IV_updated_tb = 0; + // first block + core_block_tb = block1; + core_encdec_tb = encdec; + core_next_tb = 1'b1; + + #(CLK_PERIOD); + core_next_tb = 0; + wait_ready(); + + if (core_result_tb == expected1) + begin + $display("*** TC %0d first block successful.", tc_number); + $display(""); + end + else + begin + $display("*** ERROR: TC %0d first block NOT successful.", tc_number); + $display("Expected: 0x%032x", expected1); + $display("Got: 0x%032x", core_result_tb); + $display(""); + + error_ctr = error_ctr + 1; + end + + // second block + core_block_tb = block2; + core_next_tb = 1'b1; + + #(CLK_PERIOD); + core_next_tb = 0; + wait_ready(); + + if (core_result_tb == expected2) + begin + $display("*** TC %0d second block successful.", tc_number); + $display(""); + end + else + begin + $display("*** ERROR: TC %0d second block NOT successful.", tc_number); + $display("Expected: 0x%032x", expected2); + $display("Got: 0x%032x", core_result_tb); + $display(""); + + error_ctr = error_ctr + 1; + end + + // third block + core_block_tb = block3; + core_next_tb = 1'b1; + + #(CLK_PERIOD); + core_next_tb = 0; + wait_ready(); + + if (core_result_tb == expected3) + begin + $display("*** TC %0d third block successful.", tc_number); + $display(""); + end + else + begin + $display("*** ERROR: TC %0d third block NOT successful.", tc_number); + $display("Expected: 0x%032x", expected3); + $display("Got: 0x%032x", core_result_tb); + $display(""); + + error_ctr = error_ctr + 1; + end + + // final block + core_block_tb = block4; + core_next_tb = 1'b1; + + #(CLK_PERIOD); + core_next_tb = 0; + wait_ready(); + + if (core_result_tb == expected4) + begin + $display("*** TC %0d fourth block successful.", tc_number); + $display(""); + end + else + begin + $display("*** ERROR: TC %0d fourth block NOT successful.", tc_number); + $display("Expected: 0x%032x", expected4); + $display("Got: 0x%032x", core_result_tb); + $display(""); + + error_ctr = error_ctr + 1; + end + + end_time = cycle_ctr - start_time; + + end + endtask // cbc_mode_quat_block_test + + + //---------------------------------------------------------------- + // doe_cbc_test() + // + // + // Main test task will perform complete test of DOE. + // Test vectors copied from the follwing documents. + // + // https://datatracker.ietf.org/doc/html/rfc3602 + // + // + //---------------------------------------------------------------- + task doe_cbc_test; + reg [255 : 0] nist_doe_key ; + + + reg [127 : 0] nist_IV0; + + reg [127 : 0] nist_plaintext0; + + reg [127 : 0] nist_plaintext1; + + reg [127 : 0] nist_plaintext2; + + reg [127 : 0] nist_plaintext3; + + reg [127 : 0] nist_cbc_128_enc_expected0; + + reg [127 : 0] nist_cbc_128_enc_expected1; + + reg [127 : 0] nist_cbc_128_enc_expected2; + + reg [127 : 0] nist_cbc_128_enc_expected3; + + reg [127 : 0] nist_cbc_256_enc_expected0; + + reg [127 : 0] nist_cbc_256_enc_expected1; + + reg [127 : 0] nist_cbc_256_enc_expected2; + + reg [127 : 0] nist_cbc_256_enc_expected3; + + begin + nist_doe_key = 256'hc286696d887c9aa0611bbb3e2025a45a00000000000000000000000000000000; + nist_IV0 = 128'h562e17996d093d28ddb3ba695a2e6f58; + nist_plaintext0 = 128'h000102030405060708090a0b0c0d0e0f; + nist_cbc_128_enc_expected0 = 128'hd296cd94c2cccf8a3a863028b5e1dc0a; + + $display("CBC 128 bit key single block tests"); + $display("---------------------"); + cbc_mode_single_block_test(8'h01, DOE_ENCIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_plaintext0, nist_cbc_128_enc_expected0); + $display("---------------------"); + cbc_mode_single_block_test(8'h01, DOE_DECIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_cbc_128_enc_expected0, nist_plaintext0); + + $display("---------------------"); + + nist_doe_key = 256'h56e47a38c5598974bc46903dba29034900000000000000000000000000000000; + nist_IV0 = 128'h8ce82eefbea0da3c44699ed7db51b7d9; + nist_plaintext0 = 128'ha0a1a2a3a4a5a6a7a8a9aaabacadaeaf; + nist_cbc_128_enc_expected0 = 128'hc30e32ffedc0774e6aff6af0869f71aa; + + cbc_mode_single_block_test(8'h02, DOE_ENCIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_plaintext0, nist_cbc_128_enc_expected0); + $display("---------------------"); + cbc_mode_single_block_test(8'h03, DOE_DECIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_cbc_128_enc_expected0, nist_plaintext0); + $display("---------------------"); + + nist_doe_key = 256'hc286696d887c9aa0611bbb3e2025a45a00000000000000000000000000000000; + nist_IV0 = 128'h562e17996d093d28ddb3ba695a2e6f58; + nist_plaintext0 = 128'h000102030405060708090a0b0c0d0e0f; + nist_plaintext1 = 128'h101112131415161718191a1b1c1d1e1f; + nist_cbc_128_enc_expected0 = 128'hd296cd94c2cccf8a3a863028b5e1dc0a; + nist_cbc_128_enc_expected1 = 128'h7586602d253cfff91b8266bea6d61ab1; + $display("---------------------"); + cbc_mode_double_block_test(8'h04, DOE_ENCIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_plaintext0, + nist_plaintext1, + nist_cbc_128_enc_expected0, + nist_cbc_128_enc_expected1); + + $display("---------------------"); + cbc_mode_double_block_test(8'h05, DOE_DECIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_cbc_128_enc_expected0, + nist_cbc_128_enc_expected1, + nist_plaintext0, + nist_plaintext1); + $display("---------------------"); + nist_doe_key = 256'h56e47a38c5598974bc46903dba29034900000000000000000000000000000000; + nist_IV0 = 128'h8ce82eefbea0da3c44699ed7db51b7d9; + nist_plaintext0 = 128'ha0a1a2a3a4a5a6a7a8a9aaabacadaeaf; + nist_plaintext1 = 128'hb0b1b2b3b4b5b6b7b8b9babbbcbdbebf; + nist_plaintext2 = 128'hc0c1c2c3c4c5c6c7c8c9cacbcccdcecf; + nist_plaintext3 = 128'hd0d1d2d3d4d5d6d7d8d9dadbdcdddedf; + nist_cbc_128_enc_expected0 = 128'hc30e32ffedc0774e6aff6af0869f71aa; + nist_cbc_128_enc_expected1 = 128'h0f3af07a9a31a9c684db207eb0ef8e4e; + nist_cbc_128_enc_expected2 = 128'h35907aa632c3ffdf868bb7b29d3d46ad; + nist_cbc_128_enc_expected3 = 128'h83ce9f9a102ee99d49a53e87f4c3da55; + + cbc_mode_quadratic_block_test(8'h06, DOE_ENCIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_plaintext0, + nist_plaintext1, + nist_plaintext2, + nist_plaintext3, + nist_cbc_128_enc_expected0, + nist_cbc_128_enc_expected1, + nist_cbc_128_enc_expected2, + nist_cbc_128_enc_expected3); + $display("---------------------"); + cbc_mode_quadratic_block_test(8'h07, DOE_DECIPHER, nist_doe_key , DOE_128_BIT_KEY, nist_IV0, + nist_cbc_128_enc_expected0, + nist_cbc_128_enc_expected1, + nist_cbc_128_enc_expected2, + nist_cbc_128_enc_expected3, + nist_plaintext0, + nist_plaintext1, + nist_plaintext2, + nist_plaintext3); + + $display("---------------------"); + + nist_doe_key = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4; + nist_IV0 = 128'h000102030405060708090A0B0C0D0E0F; + nist_plaintext0 = 128'h6bc1bee22e409f96e93d7e117393172a; + nist_cbc_128_enc_expected0 = 128'hf58c4c04d6e5f1ba779eabfb5f7bfbd6; + + $display("CBC 256 bit key single block tests"); + + cbc_mode_single_block_test(8'h08, DOE_ENCIPHER, nist_doe_key, DOE_256_BIT_KEY, nist_IV0, + nist_plaintext0, nist_cbc_128_enc_expected0); + + $display("---------------------"); + + end + endtask // doe_cbc_test + + //---------------------------------------------------------------- + // main + // + // The main test functionality. + //---------------------------------------------------------------- + initial + begin : main + $display(" -= Testbench for DOE CBC started =-"); + $display(" =============================="); + $display(""); + + init_sim(); + reset_dut(); + + doe_cbc_test(); + + display_test_results(); + + $display(""); + $display("*** DOE simulation done. ***"); + $finish; + end // main + +endmodule // doe_tb