diff --git a/src/OneWare.Ghdl/GhdlModule.cs b/src/OneWare.Ghdl/GhdlModule.cs index db88da3..b618bc0 100644 --- a/src/OneWare.Ghdl/GhdlModule.cs +++ b/src/OneWare.Ghdl/GhdlModule.cs @@ -79,17 +79,19 @@ public void OnInitialized(IContainerProvider containerProvider) new MenuItemViewModel("SynthGhdlToVerilog") { Header = "Convert to Verilog Netlist", - Command = new AsyncRelayCommand(() => ghdlService.SynthAsync(file, "verilog")), + Command = new AsyncRelayCommand(() => ghdlService.SynthAsync(file, "verilog", file.TopFolder!.FullPath)), }, new MenuItemViewModel("SynthGhdlToVerilog") { Header = "Convert to Dot Netlist", - Command = new AsyncRelayCommand(() => ghdlService.SynthAsync(file, "dot")), + Command = new AsyncRelayCommand(() => ghdlService.SynthAsync(file, "dot", file.TopFolder!.FullPath)), } ] }); } }); + + containerProvider.Resolve().RegisterPreCompileStep(); } } \ No newline at end of file diff --git a/src/OneWare.Ghdl/GhdlVhdlToVerilogPreCompileStep.cs b/src/OneWare.Ghdl/GhdlVhdlToVerilogPreCompileStep.cs new file mode 100644 index 0000000..5d506cc --- /dev/null +++ b/src/OneWare.Ghdl/GhdlVhdlToVerilogPreCompileStep.cs @@ -0,0 +1,36 @@ +using OneWare.Essentials.Helpers; +using OneWare.Essentials.Services; +using OneWare.Ghdl.Services; +using OneWare.UniversalFpgaProjectSystem.Models; +using OneWare.UniversalFpgaProjectSystem.Services; + +namespace OneWare.Ghdl; + +public class GhdlVhdlToVerilogPreCompileStep(GhdlService ghdlService, ILogger logger) : IFpgaPreCompileStep +{ + public string Name => "GHDL Vhdl to Verilog"; + + public async Task PerformPreCompileStepAsync(UniversalFpgaProjectRoot project, FpgaModel fpga) + { + try + { + var buildPath = Path.Combine(project.FullPath, "ghdl-output"); + if(Directory.Exists(buildPath)) Directory.Delete(buildPath, true); + Directory.CreateDirectory(buildPath); + var buildDir = project.AddFolder("ghdl-output"); + + foreach (var vhdlFile in project.Files + .Where(x => x.Extension is ".vhd" or ".vhdl") + .Where(x => !project.CompileExcluded.Contains(x)) + .Where(x => !project.TestBenches.Contains(x))) + { + await ghdlService.SynthAsync(vhdlFile, "verilog", buildPath); + } + ProjectHelper.ImportEntries(buildPath, buildDir); + } + catch (Exception e) + { + logger.Error(e.Message, e); + } + } +} \ No newline at end of file diff --git a/src/OneWare.Ghdl/Services/GhdlService.cs b/src/OneWare.Ghdl/Services/GhdlService.cs index 9a7cb4c..cb0c157 100644 --- a/src/OneWare.Ghdl/Services/GhdlService.cs +++ b/src/OneWare.Ghdl/Services/GhdlService.cs @@ -111,7 +111,7 @@ private void SetEnvironment() private Task SynthCurrentFileAsync(string output) { if (_dockService.CurrentDocument?.CurrentFile is IProjectFile selectedFile) - return SynthAsync(selectedFile, output); + return SynthAsync(selectedFile, output, selectedFile.TopFolder!.FullPath); return Task.CompletedTask; } @@ -153,7 +153,7 @@ private async Task ElaborateAsync(IProjectFile file, TestBenchContext cont return true; } - public async Task SynthAsync(IProjectFile file, string outputType) + public async Task SynthAsync(IProjectFile file, string outputType, string outputDirectory) { _dockService.Show(); @@ -182,9 +182,7 @@ public async Task SynthAsync(IProjectFile file, string outputType) _ => ".file" }; - await File.WriteAllTextAsync( - Path.Combine(Path.GetDirectoryName(file.FullPath) ?? "", - Path.GetFileNameWithoutExtension(file.FullPath) + extension), synth.output); + await File.WriteAllTextAsync(Path.Combine(outputDirectory, Path.GetFileNameWithoutExtension(file.FullPath) + extension), synth.output); } private Task SimulateCurrentFileAsync()