Synthesis to verilog does not work for VHDL code with asserts

[Flojo101]

Due to the ChildProcessService combining stdout and stderr, synthesis of VHDL designs that print asserts during elaboration or synthesis fails. The root cause are the asserts, which GHDL prints to stderr. These are then combined with stdout by the ChildProcessService, thus creating a Verilog file with syntax issues.

Potential solutions:

• Have ExecuteShellAsync return stdout and stderr separately instead of combined
• Use a custom output action to copy stdout to a separate string

[Flojo101]

The current way of just writing the ExecuteShellAsync output should also be obsolete in the next GHDL release, as it includes the -o option. It tells GHDL to write the synthesized Verilog code directly to disk