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Reliable Node Extractor for VHDL/Verilog #24

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HendrikMennen opened this issue Nov 9, 2024 · 0 comments
Open

Reliable Node Extractor for VHDL/Verilog #24

HendrikMennen opened this issue Nov 9, 2024 · 0 comments
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enhancement New feature or request help wanted Extra attention is needed

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@HendrikMennen
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Currently the extracting of nodes is done with a Regex. This is not reliable and doesn't support the use of Constants.
@HendrikMennen HendrikMennen added enhancement New feature or request help wanted Extra attention is needed labels Nov 9, 2024
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