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When the "Generate Json Netlist" is used on a Verilog file, the netlist gets generated but is not visible in the project explorer. Instead of needing to manually add the json file type to the include section of the fpgaproj-file, it should be added automatically
The text was updated successfully, but these errors were encountered:
When the "Generate Json Netlist" is used on a Verilog file, the netlist gets generated but is not visible in the project explorer. Instead of needing to manually add the json file type to the include section of the fpgaproj-file, it should be added automatically
The text was updated successfully, but these errors were encountered: