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13 Open 220 Closed
13 Open 220 Closed
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Issues list

Review need for wally-riscv-arch-test priv tests with cvw-arch-verif
#1121 opened Nov 21, 2024 by jordancarlin
2
Code coverage reporting higher coverage than expected
#1120 opened Nov 21, 2024 by jordancarlin
Difficulties getting RV64I working in lockstep
#1114 opened Nov 17, 2024 by davidharrishmc
Wally on Genesys 2 FPGA board? enhancement New feature or request
#1086 opened Nov 12, 2024 by matsbror
2
ImperasDV PBMT misaligned Mismatch
#976 opened Sep 30, 2024 by rosethompson
3
Unexplained extra bit in FMA data path enhancement New feature or request
#970 opened Sep 29, 2024 by davidharrishmc
Concurrent HPTW access fault with IFU bus fetch enhancement New feature or request
#845 opened Jun 19, 2024 by rosethompson
@rosethompson
2
Possible optimization: tlbcamline.sv enhancement New feature or request
#844 opened Jun 19, 2024 by rosethompson
@rosethompson
Setup continuous FPGA regression test and performance validation enhancement New feature or request
#780 opened May 6, 2024 by rosethompson
More tests in nightly regression enhancement New feature or request
#779 opened May 6, 2024 by davidharrishmc
3
Remove flush from EBU critical path enhancement New feature or request
#771 opened May 2, 2024 by davidharrishmc
3
Testfloat on Verilator not progressing enhancement New feature or request
#707 opened Apr 4, 2024 by davidharrishmc
@stineje
4
RAS return after return bug enhancement New feature or request
#610 opened Feb 1, 2024 by rosethompson
@rosethompson
1
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