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Issues: openpower-cores/a2i
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About some unknow instructions in A2 Core
core RTL/Architecture
documentation
Improvements or additions to documentation
#51
opened Jun 8, 2022 by
Grubby-CPU
Error happens when two threads co-execute together
core RTL/Architecture
#47
opened Feb 28, 2022 by
Grubby-CPU
Why choosing ex4 to deal with interrupt and exception
core RTL/Architecture
#44
opened Oct 12, 2021 by
Grubby-CPU
How to deal with wrong target address prediction of link stack
core RTL/Architecture
#41
opened May 13, 2021 by
Grubby-CPU
A design drawback of thread issue selection?
core RTL/Architecture
#37
opened Nov 12, 2020 by
zhaoxiahust
Any hints about the ignore_flush_is0 signal
core RTL/Architecture
#33
opened Oct 29, 2020 by
zhaoxiahust
Problem in simulation of the a2l2_axi.vhdl file
core RTL/Architecture
#32
opened Oct 28, 2020 by
xinyu8888
The RAW/WAW dependency check in iuq_fxu_dep.vhdl
core RTL/Architecture
#29
opened Sep 10, 2020 by
Grubby-CPU
Questions about the medium priority when selecting threads to issue
core RTL/Architecture
#22
opened Sep 2, 2020 by
Jackhuang-code
How to map the branch prediction algorithm to the RTL code
core RTL/Architecture
#14
opened Aug 31, 2020 by
Grubby-CPU
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