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How to deal with wrong target address prediction of link stack #41
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In what cases do you think it gives the wrong prediction? Stack overflow? Other cases where stack is messed up relative to stream? There would have to be a 'final arbiter' later in the pipe to validate the target address. Looking around iuq_bp.vhdl....seems like this is the address creation and the valid... iu5_redirect_ifar_d(EFF_IFAR'left to 61) <= iu4_lnk(EFF_IFAR'left to 61) when iu4_bclr = '1' else
iu4_bta(EFF_IFAR'left to 61);
iu5_redirect_tid_d(0 to 3) <= iu4_redirect_tid(0 to 3) and not iu4_flush_tid(0 to 3);
-- came from this...
iu3_br_pred(0 to 3) <= iu3_br_val(0 to 3) and
(iu3_br_hard(0 to 3) or
(iu3_hint_val(0 to 3) and iu3_hint(0 to 3)) or
(iu3_br_dynamic(0 to 3) and iu3_br_hist0(0 to 3)) or
(iu3_br_static(0 to 3)));
-- which depends on 'predecode bits' From Manual [2.9 Branch Processing] - good info; appears that XU does the final check on target address...
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Hi Guys,
Based on my understanding, the link stack can give a wrong prediction of the branch target address. How does A2 detect this case and flush the pipeline. I did not find any related logic in the iuq_bp.vhdl.
Many thanks
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