About the memory consistency model in A2

[Grubby-CPU]

Hi guys,

Power ISA book III-S mentions "Stores are not performed out-of-order (even if the Store instructions that caused them were executed out-of-order).",

However, there are many papers mentioning "the memory consistency model in Power is very relex where the stores can be out-of-order".

My question is can stores be out-of-order in Power ISA and in A2? I might mis-understand the Power ISA book...

Many thanks