Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

UCT/GDRCOPY: rcache lookup overhead config variable #10311

Draft
wants to merge 1 commit into
base: master
Choose a base branch
from
Draft
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
11 changes: 3 additions & 8 deletions config/ucx.conf
Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,9 @@ CPU model=Grace
UCX_REG_NONBLOCK_MEM_TYPES=host,cuda-managed
UCX_IB_ODP_MEM_TYPES=host,cuda-managed
UCX_IB_MLX5_DEVX_OBJECTS=
UCX_GDR_COPY_BW=0MBs,get_dedicated:30GBs,put_dedicated:30GBs
# Real latency is around 30ns, rest is gdrcopy rcache overhead
# TODO: Add gdrcopy rcache overhead as separate performance graph node
UCX_GDR_COPY_LAT=200ns
UCX_GDR_COPY_BW=0MBs,get_dedicated:30GBs,put_dedicated:30GBsn
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Typo

Suggested change
UCX_GDR_COPY_BW=0MBs,get_dedicated:30GBs,put_dedicated:30GBsn
UCX_GDR_COPY_BW=0MBs,get_dedicated:30GBs,put_dedicated:30GBs

UCX_GDR_COPY_LAT=30ns
UCX_GDR_COPY_RCACHE_OVERHEAD=170ns
UCX_DISTANCE_BW=auto,sys:16500MBs
UCX_CUDA_COPY_ASYNC_MEM_TYPE=cuda

Expand All @@ -27,10 +26,6 @@ UCX_DISTANCE_BW=auto,sys:5100MBs
[AMD Milan]
CPU model=Milan
UCX_DISTANCE_BW=auto,sys:5100MBs
# Real latencies are around 1.4 and 0.4, rest is gdrcopy rcache overhead
# TODO: Add gdrcopy rcache overhead as separate performance graph node
# TODO: Add rcache overhead not only for Milan and GH systems
UCX_GDR_COPY_LAT=get:1.65e-6,put:0.65e-6

[AMD Genoa]
CPU model=Genoa
Expand Down
10 changes: 8 additions & 2 deletions src/uct/cuda/gdr_copy/gdr_copy_iface.c
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,10 @@ static ucs_config_field_t uct_gdr_copy_iface_config_table[] = {
ucs_offsetof(uct_gdr_copy_iface_config_t, put_latency)},
{NULL})},

{"RCACHE_OVERHEAD", "250ns",
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think it should be in uct_gdr_copy_md_config_table right after UCX_GDR_COPY_RCACHE.
And, perhaps md->reg_cost should be initialized using the overhead, if rcache is enabled.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Agree with you. We discussed that with @brminich and came to a conclusion that it should be different md_attr field similar to reg_cost but lookup_cost. Also it seems like ucp_proto_init_add_memreg_time doesn't differentiate cacheable and non-cacheable MDs and adds UCP rcache overhead even for GDRcopy which is wrong. Also we need to somehow consider that overhead separately for memtype_ep operation if they used to do D2H and H2D copies which extends the work that need to be done significantly.

"gdr_copy regions rcache lookup estimated overhead",
ucs_offsetof(uct_gdr_copy_iface_config_t, rcache_overhead), UCS_CONFIG_TYPE_TIME},

{NULL}
};

Expand Down Expand Up @@ -137,7 +141,7 @@ uct_gdr_copy_iface_query(uct_iface_h tl_iface, uct_iface_attr_t *iface_attr)
iface->config.put_bw.dedicated);
iface_attr->bandwidth.shared = ucs_max(iface->config.get_bw.shared,
iface->config.put_bw.shared);
iface_attr->overhead = UCT_GDR_COPY_IFACE_OVERHEAD;
iface_attr->overhead = 0;
iface_attr->priority = 0;

return UCS_OK;
Expand All @@ -158,7 +162,8 @@ uct_gdr_copy_estimate_perf(uct_iface_h tl_iface, uct_perf_attr_t *perf_attr)
}

if (perf_attr->field_mask & UCT_PERF_ATTR_FIELD_SEND_PRE_OVERHEAD) {
perf_attr->send_pre_overhead = UCT_GDR_COPY_IFACE_OVERHEAD;
perf_attr->send_pre_overhead = UCT_GDR_COPY_IFACE_OVERHEAD +
iface->config.rcache_ovh;
}

if (perf_attr->field_mask & UCT_PERF_ATTR_FIELD_SEND_POST_OVERHEAD) {
Expand Down Expand Up @@ -240,6 +245,7 @@ static UCS_CLASS_INIT_FUNC(uct_gdr_copy_iface_t, uct_md_h md, uct_worker_h worke
self->config.put_bw = gdr_config->put_bw;
self->config.get_latency = ucs_linear_func_make(gdr_config->get_latency, 0);
self->config.put_latency = ucs_linear_func_make(gdr_config->put_latency, 0);
self->config.rcache_ovh = gdr_config->rcache_overhead;

return UCS_OK;
}
Expand Down
2 changes: 2 additions & 0 deletions src/uct/cuda/gdr_copy/gdr_copy_iface.h
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ typedef struct uct_gdr_copy_iface {
uct_ppn_bandwidth_t put_bw;
ucs_linear_func_t get_latency;
ucs_linear_func_t put_latency;
double rcache_ovh;
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think there is no need to shorten the word.

} config;
} uct_gdr_copy_iface_t;

Expand All @@ -30,6 +31,7 @@ typedef struct uct_gdr_copy_iface_config {
uct_ppn_bandwidth_t put_bw;
double get_latency;
double put_latency;
double rcache_overhead;
} uct_gdr_copy_iface_config_t;

#endif
Loading