From c49367584c1d569a940cab9a2668c8f24c707e29 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 2 Oct 2023 10:30:58 +0200 Subject: [PATCH 1/3] Narrower correction of issues #731/#742 Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_core.sv | 2 ++ rtl/cv32e40p_ex_stage.sv | 8 +++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40p_core.sv index 899492da4..e6f9f7098 100644 --- a/rtl/cv32e40p_core.sv +++ b/rtl/cv32e40p_core.sv @@ -780,6 +780,8 @@ module cv32e40p_core .mult_multicycle_o(mult_multicycle), // to ID/EX pipe registers + .data_req_i (data_req_o), // from ID/EX pipeline + .data_rvalid_i (data_rvalid_i), // from ID/EX pipeline .data_misaligned_ex_i(data_misaligned_ex), // from ID/EX pipeline .data_misaligned_i (data_misaligned), diff --git a/rtl/cv32e40p_ex_stage.sv b/rtl/cv32e40p_ex_stage.sv index 08392f29f..5d49b5ae8 100644 --- a/rtl/cv32e40p_ex_stage.sv +++ b/rtl/cv32e40p_ex_stage.sv @@ -76,6 +76,8 @@ module cv32e40p_ex_stage output logic mult_multicycle_o, + input logic data_req_i, + input logic data_rvalid_i, input logic data_misaligned_ex_i, input logic data_misaligned_i, @@ -369,11 +371,11 @@ module cv32e40p_ex_stage apu_result_q <= 'b0; apu_flags_q <= 'b0; end else begin - if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) begin + if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || (data_req_i && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin apu_rvalid_q <= 1'b1; apu_result_q <= apu_result_i; apu_flags_q <= apu_flags_i; - end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) begin + end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin apu_rvalid_q <= 1'b0; end end @@ -381,7 +383,7 @@ module cv32e40p_ex_stage assign apu_req_o = apu_req; assign apu_gnt = apu_gnt_i; - assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || regfile_alu_we_i || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q); + assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q); assign apu_operands_o = apu_operands_i; assign apu_op_o = apu_op_i; assign apu_result = apu_rvalid_q ? apu_result_q : apu_result_i; From eb0668c4d60f9bc2d5d379cf7e5c479bfe42d1f3 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 2 Oct 2023 11:54:30 +0200 Subject: [PATCH 2/3] Issues #869/#870/#876/#877 correction. Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_id_stage.sv | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/rtl/cv32e40p_id_stage.sv b/rtl/cv32e40p_id_stage.sv index 7b7f85cbd..7811eabfd 100644 --- a/rtl/cv32e40p_id_stage.sv +++ b/rtl/cv32e40p_id_stage.sv @@ -832,7 +832,7 @@ module cv32e40p_id_stage apu_read_regs[1] = regfile_addr_ra_id; apu_read_regs_valid[1] = 1'b1; end - OP_B_REGB_OR_FWD: begin + OP_B_REGB_OR_FWD, OP_B_BMASK: begin apu_read_regs[1] = regfile_addr_rb_id; apu_read_regs_valid[1] = 1'b1; end @@ -840,6 +840,15 @@ module cv32e40p_id_stage apu_read_regs[1] = regfile_addr_rc_id; apu_read_regs_valid[1] = 1'b1; end + OP_B_IMM: begin + if (alu_bmask_b_mux_sel == BMASK_B_REG) begin + apu_read_regs[1] = regfile_addr_rb_id; + apu_read_regs_valid[1] = 1'b1; + end else begin + apu_read_regs[1] = regfile_addr_rb_id; + apu_read_regs_valid[1] = 1'b0; + end + end default: begin apu_read_regs[1] = regfile_addr_rb_id; apu_read_regs_valid[1] = 1'b0; @@ -854,7 +863,9 @@ module cv32e40p_id_stage apu_read_regs_valid[2] = 1'b1; end OP_C_REGC_OR_FWD: begin - if ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR)) begin + if ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR) && + !((alu_op_b_mux_sel == OP_B_IMM) && (alu_bmask_b_mux_sel == BMASK_B_REG)) && + !(alu_op_b_mux_sel == OP_B_BMASK)) begin apu_read_regs[2] = regfile_addr_rc_id; apu_read_regs_valid[2] = 1'b1; end else begin From 767fb0fd85d981d548ae942eb748b847a29b71f4 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 2 Oct 2023 11:56:01 +0200 Subject: [PATCH 3/3] Issue #880 correction. Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_controller.sv | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/rtl/cv32e40p_controller.sv b/rtl/cv32e40p_controller.sv index d3941dd28..549802690 100644 --- a/rtl/cv32e40p_controller.sv +++ b/rtl/cv32e40p_controller.sv @@ -226,6 +226,8 @@ module cv32e40p_controller import cv32e40p_pkg::*; logic hwlp_counter1_gt_1; logic hwlp_counter0_eq_1; logic hwlp_counter1_eq_1; + logic hwlp_counter0_eq_0; + logic hwlp_counter1_eq_0; logic hwlp_end0_eq_pc_plus4; logic hwlp_end1_eq_pc_plus4; logic hwlp_start0_leq_pc; @@ -816,8 +818,8 @@ module cv32e40p_controller import cv32e40p_pkg::*; ctrl_fsm_ns = is_hwlp_body ? DECODE_HWLOOP : DECODE; end - hwlp_dec_cnt_o[0] = hwlp_end0_eq_pc; - hwlp_dec_cnt_o[1] = hwlp_end1_eq_pc; + hwlp_dec_cnt_o[0] = hwlp_end0_eq_pc && !hwlp_counter0_eq_0; + hwlp_dec_cnt_o[1] = hwlp_end1_eq_pc && !hwlp_counter1_eq_0; end endcase // unique case (1'b1) @@ -1275,6 +1277,8 @@ generate assign hwlp_counter1_gt_1 = hwlp_counter_i[1] > 1; assign hwlp_counter0_eq_1 = hwlp_counter_i[0] == 1; assign hwlp_counter1_eq_1 = hwlp_counter_i[1] == 1; + assign hwlp_counter0_eq_0 = hwlp_counter_i[0] == 0; + assign hwlp_counter1_eq_0 = hwlp_counter_i[1] == 0; assign hwlp_end0_eq_pc_plus4 = hwlp_end_addr_i[0] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[0] - 4 == pc_id_i + 4 assign hwlp_end1_eq_pc_plus4 = hwlp_end_addr_i[1] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[1] - 4 == pc_id_i + 4 assign hwlp_start0_leq_pc = hwlp_start_addr_i[0] <= pc_id_i; @@ -1293,6 +1297,8 @@ generate assign hwlp_counter1_gt_1 = 1'b0; assign hwlp_counter0_eq_1 = 1'b0; assign hwlp_counter1_eq_1 = 1'b0; + assign hwlp_counter0_eq_0 = 1'b0; + assign hwlp_counter1_eq_0 = 1'b0; assign hwlp_end0_eq_pc_plus4 = 1'b0; assign hwlp_end1_eq_pc_plus4 = 1'b0; assign hwlp_start0_leq_pc = 1'b0;