.gitlab-ci.yml

# Copyright 2019 ETH Zurich and University of Bologna
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

variables:
  GIT_SUBMODULE_STRATEGY: recursive
  QUESTA: "questa-2023.4-zr"
  VSIM: "$QUESTA vsim"
  VSIM_BIN: "$QUESTA vsim"
  RISCV: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0"
  PULP_RISCV_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0"

before_script:
  - pwd

# after_script:
#   - echo "stage finished"

stages:
  - fetch
  - build
  - test
  - sim_questa_multivers

fetch_ips_bender:
  stage: fetch
  script:
    - echo "Fetching IPs using bender"
    - make checkout
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - .bender/*
      - utils/bin/bender

build_rtl:
  stage: build
  before_script:
  script:
    - echo "Compiling RTL model and DPI libraries"
    - make build
    - echo "Fetching VIPs"
    - ./target/sim/vip/get-vips.sh --yes # --gitlab
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - target/sim/tb/tb_lib/remote_bitbang/* # we want to reuse bitbang lib
      - target/sim/vip/*
      - build/questasim/*


lint:
  stage: test
  script:
    - echo "Running Spyglass Lint in rtl_handoff methodology with goal lint_rtl"
    - make lint_rtl
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - build/spyglass/working_dir/*
    reports:
      junit: build/spyglass/working_dir/reports/lint_rtl.report.xml
  dependencies:
    - fetch_ips_bender
  needs:
    - fetch_ips_bender
  

# Use sdk-releases to run all tests
test_sequential_bare:
  stage: test
  needs: [ build_rtl ]
  parallel:
    matrix:
      - { TEST: dct             }
      - { TEST: fft2            }
      - { TEST: rijndael        }
      - { TEST: jacobi-2d-imper }
      - { TEST: bitDescriptor   }
      - { TEST: stencil_vect    }
      - { TEST: keccak          }
      - { TEST: fir             }
      - { TEST: stencil         }
      - { TEST: ipm             }
      - { TEST: towerofhanoi    }
      - { TEST: crc32           }
      - { TEST: conv2d          }
      - { TEST: seidel          }
      - { TEST: fibonacci       }
      - { TEST: gauss-2d        }
      - { TEST: aes_cbc         }
      - { TEST: bubblesort      }
      - { TEST: fdtd-1d         }
      - { TEST: jacobi-1d-imper }
      - { TEST: fft             }
  script:
    - echo "Running sequential bare tests"
    - make relink
    - source sw/pulp-runtime/configs/pulpissimo_cv32.sh
    - export VSIM_PATH=$PWD/build/questasim
    - cd sw/regression_tests/sequential_bare_tests/${TEST}
    - make clean all run

test_riscv:
  stage: test
  needs: [ build_rtl ]
  parallel:
    matrix:
    - { TEST: testBitManipulation }
    - { TEST: testVecCmp          }
    - { TEST: testAddSubNorm      }
    - { TEST: testMisaligned      }
    - { TEST: testALU             }
    - { TEST: testMAC3            }
    - { TEST: testVecArith        }
    - { TEST: testDotMul          }
    - { TEST: testVecLogic        }
    # - { TEST: testComplex         }
    - { TEST: testCnt             }
    - { TEST: testVecRelat        }
    - { TEST: testShufflePack     }
    - { TEST: testMUL             }
    - { TEST: testHWLP            }
    - { TEST: testMacNorm         }
    # - { TEST: testDivRem          }
    - { TEST: testVariadic        }
    - { TEST: testMAC             }
    - { TEST: testLoadStore       }
    - { TEST: testALUExt          }
    - { TEST: testBuiltins        }
  script:
    - echo "Running riscv tests"
    - source sw/pulp-runtime/configs/pulpissimo_cv32.sh
    - export VSIM_PATH=$PWD/build/questasim
    - cd sw/regression_tests/riscv_tests/${TEST}
    - make clean all run

freertos_helloworld:
  stage: test
  before_script:
    - git clone https://github.com/pulp-platform/pulp-freertos.git sw/pulp-freertos
    - cd sw/pulp-freertos
    - git checkout d6966cae9471b7a592bd09b7acfd5b832666e3b5
    - git submodule update --init --recursive
    - cd ../..
  script:
    - make scripts
    - make clean build
    - export VSIM_PATH=$PWD/build/questasim
    - cd sw/pulp-freertos
    - source env/pulpissimo-cv32e40p.sh
    - cd tests/hello_world_pmsis
    - $QUESTA make all run

test_dm:
  stage: test
  before_script:
    - source sw/pulp-runtime/configs/pulpissimo_cv32.sh
    - make -C sw/regression_tests/hello clean all
  script:
    - echo "(Re)generating scripts with DPI disabled"
    - make scripts
    - echo "Setting up vsim path"
    - export VSIM_PATH=$PWD/build/questasim
    - echo "Running debug module testbench"
    # Note that the program is irrelevant we just put something for it to not complain
    - riscv make build run_sim VSIM_USER_PLUSARGS="+jtag_dm_tests +srec_ignore_checksum" EXECUTABLE_PATH=sw/regression_tests/hello/build/test/test

fpga_synth_genesys2:
  stage: test
  before_script:
  script:
    - echo "Starting synthesis with vivado"
    - make genesys2 VIVADO='vitis-2022.1 vivado'
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - target/fpga/pulpissimo_genesys2.bit
      - target/fpga/pulpissimo_genesys2.bin
      - target/fpga/*.jou
      - target/fpga/*.log
      - target/fpga/*.str
      - target/fpga/pulpissimo-genesys2/reports
      - target/fpga/pulpissimo-genesys2/rtl
      - target/fpga/pulpissimo-genesys2/tcl
      - target/fpga/pulpissimo-genesys2/pulpissimo-genesys2.xpr
      - target/fpga/pulpissimo-genesys2/fpga-settings.mk
      - target/fpga/pulpissimo-genesys2/*.log
      - target/fpga/pulpissimo-genesys2/*.cfg
      - target/fpga/pulpissimo-genesys2/*.gdb
      - target/fpga/pulpissimo-genesys2/*.jou
      - target/fpga/pulpissimo-genesys2/*.log

fpga_synth_nexys_video:
  stage: test
  before_script:
  script:
    - echo "Starting synthesis with vivado"
    - make nexys_video VIVADO='vitis-2022.1 vivado'
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - target/fpga/pulpissimo_nexys_video.bit
      - target/fpga/pulpissimo_nexys_video.bin
      - target/fpga/*.jou
      - target/fpga/*.log
      - target/fpga/*.str
      - target/fpga/pulpissimo-nexys_video/reports
      - target/fpga/pulpissimo-nexys_video/rtl
      - target/fpga/pulpissimo-nexys_video/tcl
      - target/fpga/pulpissimo-nexys_video/pulpissimo-nexys_video.xpr
      - target/fpga/pulpissimo-nexys_video/fpga-settings.mk
      - target/fpga/pulpissimo-nexys_video/*.log
      - target/fpga/pulpissimo-nexys_video/*.cfg
      - target/fpga/pulpissimo-nexys_video/*.gdb
      - target/fpga/pulpissimo-nexys_video/*.jou
      - target/fpga/pulpissimo-nexys_video/*.log

fpga_synth_nexys:
  stage: test
  before_script:
  script:
    - echo "Starting synthesis with vivado"
    - make nexys rev=nexys4 VIVADO='vitis-2022.1 vivado'
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - target/fpga/pulpissimo_nexys.bit
      - target/fpga/pulpissimo_nexys.bin
      - target/fpga/*.jou
      - target/fpga/*.log
      - target/fpga/*.str
      - target/fpga/pulpissimo-nexys/reports
      - target/fpga/pulpissimo-nexys/rtl
      - target/fpga/pulpissimo-nexys/tcl
      - target/fpga/pulpissimo-nexys/pulpissimo-nexys.xpr
      - target/fpga/pulpissimo-nexys/fpga-settings.mk
      - target/fpga/pulpissimo-nexys/*.log
      - target/fpga/pulpissimo-nexys/*.cfg
      - target/fpga/pulpissimo-nexys/*.gdb
      - target/fpga/pulpissimo-nexys/*.jou
      - target/fpga/pulpissimo-nexys/*.log

fpga_synth_zcu104:
  stage: test
  before_script:
  script:
    - echo "Starting synthesis with vivado"
    - make zcu104 VIVADO='vitis-2023.2 vivado'
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - target/fpga/pulpissimo_zcu104.bit
      - target/fpga/pulpissimo_zcu104.bin
      - target/fpga/*.jou
      - target/fpga/*.log
      - target/fpga/*.str
      - target/fpga/pulpissimo-zcu104/reports
      - target/fpga/pulpissimo-zcu104/rtl
      - target/fpga/pulpissimo-zcu104/tcl
      - target/fpga/pulpissimo-zcu104/pulpissimo-zcu104.xpr
      - target/fpga/pulpissimo-zcu104/fpga-settings.mk
      - target/fpga/pulpissimo-zcu104/*.log
      - target/fpga/pulpissimo-zcu104/*.cfg
      - target/fpga/pulpissimo-zcu104/*.gdb
      - target/fpga/pulpissimo-zcu104/*.jou
      - target/fpga/pulpissimo-zcu104/*.log

fpga_synth_zcu102:
  stage: test
  before_script:
  timeout: 5 hours
  script:
    - echo "Starting synthesis with vivado"
    - make zcu102 VIVADO='vitis-2020.2 vivado'
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - target/fpga/pulpissimo_zcu102.bit
      - target/fpga/pulpissimo_zcu102.bin
      - target/fpga/*.jou
      - target/fpga/*.log
      - target/fpga/*.str
      - target/fpga/pulpissimo-zcu102/reports
      - target/fpga/pulpissimo-zcu102/rtl
      - target/fpga/pulpissimo-zcu102/tcl
      - target/fpga/pulpissimo-zcu102/pulpissimo-zcu102.xpr
      - target/fpga/pulpissimo-zcu102/fpga-settings.mk
      - target/fpga/pulpissimo-zcu102/*.log
      - target/fpga/pulpissimo-zcu102/*.cfg
      - target/fpga/pulpissimo-zcu102/*.gdb
      - target/fpga/pulpissimo-zcu102/*.jou
      - target/fpga/pulpissimo-zcu102/*.log

sim_questa_multivers:
  stage: sim_questa_multivers
  allow_failure: true
  when: always
  parallel:
    matrix:
      - QUESTA_PREFIX:
        - 'vsim'                   # Default
        - 'questa-2019.3-kgf vsim'
        # - 'questa-2020.1-kgf vsim'
        # - 'questa-2021.1-bt vsim'  # Has errors
        # - 'questa-2021.2-bt vsim'  # Has errors
        - 'questa-2021.3-kgf vsim'
        - 'questa-2022.3-bt vsim'
        - 'questa-2023.4-zr vsim'
        # - 'vsim-10.0d-kgf'         # Incompatible
        # - 'vsim-10.1c-kgf'         # Incompatible
        # - 'vsim-10.2c-kgf'         # Incompatible
        # - 'vsim-10.3a-kgf'         # Incompatible
        # - 'vsim-10.3e-kgf'         # Incompatible
        # - 'vsim-10.4c-kgf'         # Incompatible
        # - 'vsim-10.5a-kgf'         # Incompatible
        # - 'vsim-10.5c-kgf'
        # - 'vsim-10.6b-kgf'
        - 'vsim-10.7b-kgf'
        - 'vsim-10.7e-kgf'
  before_script:
    - export VSIM="$QUESTA_PREFIX"
    - export VSIM_BIN="$QUESTA_PREFIX"
    - mkdir hello
    - printf "#include <stdio.h>\nint main(){\n  printf(\"Hello World\\\n\");\n  return 0;\n}\n" > hello/hello.c
    - printf "PULP_APP = hello\nPULP_APP_FC_SRCS = hello.c\nPULP_APP_HOST_SRCS = hello.c\nPULP_CFLAGS = -O3 -g\n\ninclude \$(PULP_SDK_HOME)/install/rules/pulp_rt.mk\n" > hello/Makefile
  script:
    - make scripts
    - make clean build
    - export VSIM_PATH=$PWD/build/questasim
    - source sw/pulp-runtime/configs/pulpissimo_cv32.sh
    - make -C hello clean all run
  dependencies:
    - fetch_ips_bender
  needs:
    - fetch_ips_bender

spi_boot:
  stage: test
  before_script:
    - git clone https://github.com/pulp-platform/pulp-runtime.git -b v0.0.15
    - mkdir hello
    - printf "#include <stdio.h>\nint main(){\n  printf(\"Hello World\\\n\");\n  return 0;\n}\n" > hello/hello.c
    - printf "PULP_APP = hello\nPULP_APP_FC_SRCS = hello.c\nPULP_APP_HOST_SRCS = hello.c\nPULP_CFLAGS = -O3 -g\n\ninclude \$(PULP_SDK_HOME)/install/rules/pulp_rt.mk\n" > hello/Makefile
  script:
    - make clean build USE_VIPS=1
    - export VSIM_PATH=$PWD/build/questasim
    - source pulp-runtime/configs/pulpissimo_cv32.sh
    - make -C hello clean all run bootmode=spi
  dependencies:
    - build_rtl
  needs:
    - build_rtl