WIP: realign to EFCL Summer School

.gitlab-ci.yml

@@ -17,8 +17,8 @@ variables:
   QUESTA: "questa-2023.4-zr"
   VSIM: "$QUESTA vsim"
   VSIM_BIN: "$QUESTA vsim"
-  RISCV: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0"
-  PULP_RISCV_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0"
+  RISCV: "/usr/pack/riscv-1.0-kgf/efclschool-llvm-18.1.6"
+  PULP_RISCV_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/efclschool-llvm-18.1.6"
 
 before_script:
   - pwd

Bender.lock

@@ -41,8 +41,8 @@ packages:
     - apb
     - common_cells
   axi:
-    revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6
-    version: 0.39.3
+    revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
+    version: 0.39.4
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -57,8 +57,8 @@ packages:
     dependencies:
     - common_cells
   common_cells:
-    revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4
-    version: 1.35.0
+    revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
+    version: 1.37.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -79,6 +79,29 @@ packages:
     - common_cells
     - fpnew
     - tech_cells_generic
+  cv32e40x:
+    revision: fe5e7f41ad284b5aee583a727503bb6f1097daab
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/cv32e40x.git
+    dependencies: []
+  fir-hwpe:
+    revision: 0397301c727e2f232e0f508fbdc13401c023fa26
+    version: 2.0.2
+    source:
+      Git: https://github.com/pulp-platform/fir-hwpe.git
+    dependencies:
+    - hci
+    - hwpe-ctrl
+    - hwpe-stream
+    - zeroriscy
+  fir-xifu:
+    revision: 2b1a71fa7310c20ae0824b93669766713ebcec88
+    version: 0.1.3
+    source:
+      Git: https://github.com/pulp-platform/fir-xifu.git
+    dependencies:
+    - cv32e40x
   fpnew:
     revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
     version: null
@@ -112,21 +135,22 @@ packages:
     - common_verification
     - register_interface
     - tech_cells_generic
+  hci:
+    revision: d31af36ebcaf2196fb51676b40782aa8cbd9cc69
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/hci.git
+    dependencies:
+    - cluster_interconnect
+    - hwpe-stream
+    - l2_tcdm_hybrid_interco
   hwpe-ctrl:
-    revision: 1916c72f024175f1fe351acc3db3c6e9925a117d
-    version: 1.7.3
+    revision: 877d676329785f7bba042402e0a6f329a387573d
+    version: null
     source:
       Git: https://github.com/pulp-platform/hwpe-ctrl.git
     dependencies:
     - tech_cells_generic
-  hwpe-mac-engine:
-    revision: cd48c574f1972ecbe02d3f463a0e12a92acde484
-    version: 1.3.3
-    source:
-      Git: https://github.com/pulp-platform/hwpe-mac-engine.git
-    dependencies:
-    - hwpe-ctrl
-    - hwpe-stream
   hwpe-stream:
     revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1
     version: 1.8.0
@@ -147,6 +171,12 @@ packages:
     source:
       Git: https://github.com/pulp-platform/jtag_pulp.git
     dependencies: []
+  l2_tcdm_hybrid_interco:
+    revision: fa55e72859dcfb117a2788a77352193bef94ff2b
+    version: 1.0.0
+    source:
+      Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
+    dependencies: []
   pulp_io:
     revision: da6f8817b667f17973ecb19cb1e7aa4347108716
     version: 0.1.0
@@ -166,8 +196,8 @@ packages:
     - udma_sdio
     - udma_uart
   pulp_soc:
-    revision: bf65372aab4edd404160170e2a4d2c63b27ab5f2
-    version: 5.0.1
+    revision: 8c6b9dea6ba8dbdbc995efb6e0e24194d470f373
+    version: null
     source:
       Git: https://github.com/pulp-platform/pulp_soc.git
     dependencies:
@@ -180,8 +210,10 @@ packages:
     - cluster_interconnect
     - common_cells
     - cv32e40p
+    - cv32e40x
+    - fir-hwpe
+    - fir-xifu
     - fpnew
-    - hwpe-mac-engine
     - ibex
     - jtag_pulp
     - pulp_io
@@ -190,6 +222,12 @@ packages:
     - scm
     - tech_cells_generic
     - timer_unit
+  pulpissimo_essentials:
+    revision: null
+    version: null
+    source:
+      Path: target/synthesis/bender/pulpissimo_essentials
+    dependencies: []
   pulpissimo_optional_vips:
     revision: null
     version: null
@@ -249,6 +287,12 @@ packages:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
     - common_verification
+  tech_cells_gf22fdx:
+    revision: null
+    version: null
+    source:
+      Path: target/synthesis/bender/tech_cells
+    dependencies: []
   timer_unit:
     revision: 4c69615c89db9397a9747d6f6d6a36727854f0bc
     version: 1.0.3
@@ -328,3 +372,9 @@ packages:
     dependencies:
     - common_cells
     - udma_core
+  zeroriscy:
+    revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36
+    version: null
+    source:
+      Git: https://github.com/yvantor/ibex.git
+    dependencies: []

Bender.yml

@@ -16,14 +16,17 @@ dependencies:
   common_cells:                { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.21.0 }
   apb:                         { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4 }
   jtag_pulp:                   { git: "https://github.com/pulp-platform/jtag_pulp.git",          version: 0.2.0 }
-  pulp_soc:                    { git: "https://github.com/pulp-platform/pulp_soc.git",           version: 5.0.1 }
+  pulp_soc:                    { git: "https://github.com/pulp-platform/pulp_soc.git",           rev: efcl_ss-v0.2.4 } # branch fc/cv32e40x
   tbtools:                     { git: "https://github.com/pulp-platform/tbtools.git",            version: 0.2.1 }
   tech_cells_generic:          { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
   pulpissimo_padframe_rtl_sim: { path: "hw/padframe/pulpissimo_padframe_rtl_sim_autogen" }
   pulpissimo_padframe_fpga:    { path: "hw/padframe/pulpissimo_padframe_fpga_autogen" }
   register_interface:          { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 }
   generic_FLL:                 { git: "https://github.com/pulp-platform/generic_FLL.git",        version: 0.2.0 }
   apb_fll_if:                  { git: "https://github.com/pulp-platform/apb_fll_if.git",         version: 0.2.1 }
+  # the following dependencies are non-free, and will be ignored in a free setup
+  tech_cells_gf22fdx:          { path: "target/synthesis/bender/tech_cells" }
+  pulpissimo_essentials:       { path: "target/synthesis/bender/pulpissimo_essentials" }
 
 
   # Target Specific Dependencies
@@ -49,8 +52,8 @@ sources:
   - target: not(any(fpga, xilinx))
     files:
       - hw/asic_autogen_rom.sv
-  - hw/soc_domain.sv
-  - hw/pulpissimo.sv
+      - hw/soc_domain.sv
+      - hw/pulpissimo.sv
 
 
   # rtl_sim - Generic version of pulpissimo used for non-verilator RTL simulation 
@@ -78,7 +81,6 @@ sources:
       - target/sim/tb/tb_pulp.sv
       - target/sim/tb/tb_pulp_simple.sv
 
-
 vendor_package:
   # Import the GPIO repository directly. Since we have to regenerate the RTL
   # when we change the number GPIOs we cannot just depend on it as a regular

Makefile

@@ -27,11 +27,19 @@ include target/lint/spyglass/Makefile
 include target/fpga/Makefile
 include $(PULPISSIMO_ROOT)/utils/utils.mk
 
+# ignore synthesis targets if only free setup available
+-include target/synthesis/Makefile
+
 .PHONY: checkout
 ## Checkout all Bender IPs
 checkout: $(PULPISSIMO_UTILS)/bender
 	$(PULPISSIMO_UTILS)/bender checkout
 
+.PHONY: checkout-synthesis
+checkout-synthesis: $(PULPISSIMO_UTILS)/bender
+	git clone --recursive [email protected]:pulp-restricted/pulpissimo-synthesis target/synthesis
+	$(PULPISSIMO_UTILS)/bender update
+
 .PHONY: hw bootrom padframe
 ## Re-generate generated hardware IPs
 hw: bootrom padframe

README.md

@@ -246,6 +246,13 @@ If you encounter this bug use the following temporary workaround instead to buil
 VP_WORKAROUND_NONNULL_BUG=yes make build-pulp-sdk
 ```
 
+### Non-free synthesis setup
+If you have access to the non-free synthesis setup, you can download requirements
+with the command
+```bash
+make checkout-synthesis
+```
+
 ### Building the RTL simulation platform
 Note you need Questasim or Xcelium to do an RTL simulation of PULPissimo
 (verilator support planned, but not finished). Intel Modelsim for Intel FPGAs

hw/pulpissimo.sv

@@ -29,7 +29,7 @@
 
 module pulpissimo #(
   /// 0 for CV32E40P with XPULP Extensions, 1 for IBEX RV32IMC (formerly ZERORISCY),
-  /// 2 for IBEX RV32EC (formerly MICRORISCY)
+  /// 2 for IBEX RV32EC (formerly MICRORISCY), 3 for CV32E40X
   parameter  int unsigned CORE_TYPE = 0,
   /// Enable XPULP extensions on CV32E40P. Has no effect if an IBEX core variant is use.
   parameter  bit          USE_XPULP = 1,
@@ -39,7 +39,7 @@ module pulpissimo #(
   /// Standard RISC-V extension: Reuses the integer regfile for FPU usage instead of requiring a
   /// dedicated FPU regfile. Requires correct compiler settings for software to work!
   parameter  bit          USE_ZFINX = 1,
-  parameter  bit          USE_HWPE = 0,
+  parameter  bit          USE_HWPE = 1,
   /// Enable the virtual stdout interface for communication with simulated testbenches. This
   /// parameter must be disabled during any form of physical implementation.
   parameter  bit          SIM_STDOUT = 0,

target/fpga/Makefile

@@ -119,3 +119,16 @@ clean_zcu102:
 	$(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zcu102 clean
 	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bit
 	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zcu102.bin
+
+## Generates the bistream for the zyboz7 board
+zyboz7: $(PULPISSIMO_FPGA_ROOT)/pulpissimo/tcl/generated/compile.tcl
+	$(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7 all
+	cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7/pulpissimo-zyboz7.runs/impl_1/xilinx_pulpissimo.bit $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bit
+	cp $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7/pulpissimo-zyboz7.runs/impl_1/xilinx_pulpissimo.bin $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bin
+	@echo "Bitstream generation for zyboz7 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zyboz7.bit and ./pulpissimo_zyboz7.bin"
+
+## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zyboz7 board.
+clean_zyboz7:
+	$(MAKE) -C $(PULPISSIMO_FPGA_ROOT)/pulpissimo-zyboz7 clean
+	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bit
+	rm -f $(PULPISSIMO_FPGA_ROOT)/pulpissimo_zyboz7.bin

target/fpga/pulpissimo-zyboz7/.gitignore

@@ -0,0 +1,22 @@
+#Ignore vivado project files generated by the tcl script
+**/.Xil/*
+**/reports/*
+**/*.cache/*
+**/*.hw/*
+**/*.ip_user_files/*
+**/*.runs/*
+**/*.sim/*
+**/*.srcs/*
+*.edf
+*.xpr
+*.jou
+*.log
+
+.cxl.*
+
+*_stub.v
+gmon.out
+
+/pulpissimo-nexys_video/**/pulpissimo.bit
+
+**/xdc/constraints.xdc

target/fpga/pulpissimo-zyboz7/Makefile

@@ -0,0 +1,41 @@
+include fpga-settings.mk
+
+PROJECT:=pulpissimo-$(BOARD)
+VIVADO ?= vivado
+
+.DEFAULT_GOAL:=help
+
+.PHONY: help all gui ips clean-ips clk clean-clk clean
+
+#Make sure BENDER environment variable is available for subprocesses in Make
+export BENDER
+
+all: ips ## Generate the bitstream for pulpissimo with vivado in batch mode. The vivado invocation command may be overriden with the env variable VIVADO.
+	$(VIVADO) -mode batch -source tcl/run.tcl
+
+gui: ips ## Generates the bitstream for pulpissimo with vivado in GUI mode. The vivado invocation command may be overriden with the env variable VIVADO.
+	$(VIVADO) -mode gui -source tcl/run.tcl &
+
+ips: clk ## Synthesizes necessary xilinx IP
+
+clean-ips: clean-clk ## Clean all IPs
+
+clk: ## Synthesizes the Xilinx Clocking Manager IPs
+	$(MAKE) -C ips/xilinx_clk_mngr all
+	$(MAKE) -C ips/xilinx_slow_clk_mngr all
+
+clean-clk: ## Removes all Clocking Wizard IP outputs
+	$(MAKE) -C ips/xilinx_clk_mngr clean
+	$(MAKE) -C ips/xilinx_slow_clk_mngr clean
+
+clean: clean-ips ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*)
+	rm -rf ${PROJECT}.*[^'bit']
+	rm -rf ${PROJECT}.*[^'bin']
+	rm -rf *.log
+	rm -rf vivado*
+
+download: ## Download the bitstream into the FPGA
+	$(VIVADO) -mode batch -source tcl/download_bitstream.tcl -tclargs $(PROJECT).runs/impl_1/xilinx_pulpissimo.bit pulpissimo_$(BOARD).bit
+
+help:
+	@grep -E -h '^[a-zA-Z_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'