From 14bae099355bda4df6817dbf21031879af57676e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Sun, 28 Mar 2021 20:32:50 +0200 Subject: [PATCH 01/12] load process into itcm needs newer fixed cortex-m-rt 0.6.13+unreleased relevant? https://reviews.llvm.org/D81986 --- .cargo/config | 1 + Cargo.lock | 20 ++++++++------------ Cargo.toml | 25 +++++++++++++++++-------- build.rs | 9 +++++++++ memory.x | 23 ++++++++++++++++++----- src/bin/dual-iir.rs | 2 ++ src/hardware/mod.rs | 4 ++-- src/startup.S | 28 ++++++++++++++++++++++++++++ 8 files changed, 85 insertions(+), 27 deletions(-) create mode 100644 build.rs create mode 100644 src/startup.S diff --git a/.cargo/config b/.cargo/config index deffdfc51..ad2c02499 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,6 +1,7 @@ [target.'cfg(all(target_arch = "arm", target_os = "none"))'] runner = "gdb-multiarch -q -x openocd.gdb" rustflags = [ + "-C", "link-arg=--nmagic", "-C", "link-arg=-Tlink.x", # The target (below) defaults to cortex-m4 # There currently are two different options to go beyond that: diff --git a/Cargo.lock b/Cargo.lock index 946a63467..03a85586b 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -100,6 +100,12 @@ dependencies = [ "rustc_version", ] +[[package]] +name = "cc" +version = "1.0.67" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e3c69b077ad434294d3ce9f1f6143a2a4b89a8a2d54ef813d85003a4fd1137fd" + [[package]] name = "cfg-if" version = "1.0.0" @@ -145,18 +151,13 @@ dependencies = [ [[package]] name = "cortex-m-rt" version = "0.6.13" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "980c9d0233a909f355ed297ef122f257942de5e0a2cb1c39f60684b65bcb90fb" dependencies = [ "cortex-m-rt-macros", - "r0", ] [[package]] name = "cortex-m-rt-macros" -version = "0.1.8" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4717562afbba06e760d34451919f5c3bf3ac15c7bb897e8b04862a7428378647" +version = "0.6.11" dependencies = [ "proc-macro2", "quote", @@ -572,12 +573,6 @@ dependencies = [ "proc-macro2", ] -[[package]] -name = "r0" -version = "0.2.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f" - [[package]] name = "rand" version = "0.8.3" @@ -720,6 +715,7 @@ version = "0.4.1" dependencies = [ "ad9959", "asm-delay", + "cc", "cortex-m 0.6.7", "cortex-m-log", "cortex-m-rt", diff --git a/Cargo.toml b/Cargo.toml index 8d32d80d5..a18e5951f 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -47,6 +47,23 @@ smoltcp-nal = "0.1.0" miniconf = "0.1" generic-array = "0.14" +[dependencies.mcp23017] +git = "https://github.com/mrd0ll4r/mcp23017.git" + +[dependencies.stm32h7xx-hal] +features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] +git = "https://github.com/stm32-rs/stm32h7xx-hal" +branch = "master" + +[build-dependencies] +cc = "1.0" + +[patch.crates-io.cortex-m-rt] +path = "../cortex-m-rt" +# 0.6.13 +# git = "https://github.com/rust-embedded/cortex-m-rt.git" +# rev = "8c90451" + [patch.crates-io.miniconf] git = "https://github.com/quartiq/miniconf.git" branch = "develop" @@ -67,14 +84,6 @@ branch = "master" # a new release of smoltcp is made, we can remove this patch. git = "https://github.com/smoltcp-rs/smoltcp.git" -[dependencies.mcp23017] -git = "https://github.com/mrd0ll4r/mcp23017.git" - -[dependencies.stm32h7xx-hal] -features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] -git = "https://github.com/stm32-rs/stm32h7xx-hal" -branch = "master" - [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] bkpt = [ ] diff --git a/build.rs b/build.rs new file mode 100644 index 000000000..3f9eaf986 --- /dev/null +++ b/build.rs @@ -0,0 +1,9 @@ +fn main() { + println!("cargo:rerun-if-changed=memory.x"); + + cc::Build::new() + .file("src/startup.S") + .compile("startup"); + println!("cargo:rerun-if-changed=src/startup.S"); +} + diff --git a/memory.x b/memory.x index c1569cedd..a13251761 100644 --- a/memory.x +++ b/memory.x @@ -13,10 +13,6 @@ MEMORY } SECTIONS { - .itcm : ALIGN(8) { - *(.itcm .itcm.*); - . = ALIGN(8); - } > ITCM .axisram (NOLOAD) : ALIGN(8) { *(.axisram .axisram.*); . = ALIGN(8); @@ -33,4 +29,21 @@ SECTIONS { *(.sram3 .sram3.*); . = ALIGN(4); } > SRAM3 -} INSERT AFTER .bss; + .itcm : ALIGN(8) { + . = ALIGN(8); + __sitcm = .; + *(.itcm .itcm.*); + . = ALIGN(8); + __eitcm = .; + } > ITCM AT>FLASH + __siitcm = LOADADDR(.itcm); + +/* This may be the only insert location that doesn't affect those __[es]... + * that are (unfortunately) placed outside their sections */ +} INSERT BEFORE .uninit; + +ASSERT(__sitcm % 8 == 0 && __eitcm % 8 == 0, " +BUG(cortex-m-rt): .itcm is not 8-byte aligned"); + +ASSERT(__siitcm % 4 == 0, " +BUG(cortex-m-rt): the LMA of .itcm is not 4-byte aligned"); diff --git a/src/bin/dual-iir.rs b/src/bin/dual-iir.rs index 4a27d487c..5a878dcdf 100644 --- a/src/bin/dual-iir.rs +++ b/src/bin/dual-iir.rs @@ -110,6 +110,8 @@ const APP: () = { /// Because the ADC and DAC operate at the same rate, these two constraints actually implement /// the same time bounds, meeting one also means the other is also met. #[task(binds=DMA1_STR4, resources=[adcs, dacs, iir_state, iir_ch], priority=2)] + #[inline(never)] + #[link_section = ".itcm.process"] fn process(c: process::Context) { let adc_samples = [ c.resources.adcs.0.acquire_buffer(), diff --git a/src/hardware/mod.rs b/src/hardware/mod.rs index cc7a34ab6..a83c9d641 100644 --- a/src/hardware/mod.rs +++ b/src/hardware/mod.rs @@ -58,11 +58,11 @@ fn panic(_info: &core::panic::PanicInfo) -> ! { } #[cortex_m_rt::exception] -fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! { +unsafe fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! { panic!("HardFault at {:#?}", ef); } #[cortex_m_rt::exception] -fn DefaultHandler(irqn: i16) { +unsafe fn DefaultHandler(irqn: i16) { panic!("Unhandled exception (IRQn = {})", irqn); } diff --git a/src/startup.S b/src/startup.S new file mode 100644 index 000000000..b85bf11bc --- /dev/null +++ b/src/startup.S @@ -0,0 +1,28 @@ +.cfi_sections .debug_frame + +# .thumb +.section .text.pre_init, "ax" +.globl __pre_init +.type __pre_init,%function +.thumb_func +.cfi_startproc +__pre_init: + # Analogous to cortex-m-rt Reset code for .data copying. + # Initialise .itcm code. `__sitcm`, `__siitcm`, and `__eitcm` come from the + # linker script. Copy from r2 into r0 until r0 reaches r1. + ldr r0,=__sitcm + ldr r1,=__eitcm + ldr r2,=__siitcm +1: + cmp r1, r0 + beq 2f + # load 1 word from r2 to r3, inc r2 + ldm r2!, {r3} + # store 1 word from r3 to r0, inc r0 + stm r0!, {r3} + b 1b +2: + dsb + isb + bx lr +.cfi_endproc From fc7374424a75876c67cafac877fbbc03aba39bc9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 29 Mar 2021 18:51:50 +0200 Subject: [PATCH 02/12] enable itcm/dtcm explicitly --- src/startup.S | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/startup.S b/src/startup.S index b85bf11bc..3a5b6ea2d 100644 --- a/src/startup.S +++ b/src/startup.S @@ -7,6 +7,22 @@ .thumb_func .cfi_startproc __pre_init: + + # Enable ITCM and DTCM + ldr r0, =1 + ldr r1, =0xE000EF90 + ldr r2, [r1] + # Set ITCMCR.EN + orr r2, r2, r0 + str r2, [r1] + ldr r1, =0xE000EF94 + ldr r2, [r1] + # Set DTCMCR.EN + orr r2, r2, r0 + str r2, [r1] + dsb + isb + # Analogous to cortex-m-rt Reset code for .data copying. # Initialise .itcm code. `__sitcm`, `__siitcm`, and `__eitcm` come from the # linker script. Copy from r2 into r0 until r0 reaches r1. From cd3cfa63e6248c66e34ea1fe0af1fcb72a74c58f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Tue, 20 Apr 2021 13:26:07 +0200 Subject: [PATCH 03/12] memory.x: remove comment about old cortex-m-rt --- memory.x | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/memory.x b/memory.x index a13251761..d87640af9 100644 --- a/memory.x +++ b/memory.x @@ -37,10 +37,7 @@ SECTIONS { __eitcm = .; } > ITCM AT>FLASH __siitcm = LOADADDR(.itcm); - -/* This may be the only insert location that doesn't affect those __[es]... - * that are (unfortunately) placed outside their sections */ -} INSERT BEFORE .uninit; +} INSERT AFTER .uninit; ASSERT(__sitcm % 8 == 0 && __eitcm % 8 == 0, " BUG(cortex-m-rt): .itcm is not 8-byte aligned"); From 9e66054d211870441f9a8429d443c5796bfe1674 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 29 Apr 2021 16:39:01 +0200 Subject: [PATCH 04/12] bump cortex-m-rt to 0.6.13+git --- Cargo.lock | 2 ++ Cargo.toml | 6 ++---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 03a85586b..d8e77823e 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -151,6 +151,7 @@ dependencies = [ [[package]] name = "cortex-m-rt" version = "0.6.13" +source = "git+https://github.com/rust-embedded/cortex-m-rt.git?rev=a2e3ad5#a2e3ad54478c6b98e519a1b0946395d790c0b6c7" dependencies = [ "cortex-m-rt-macros", ] @@ -158,6 +159,7 @@ dependencies = [ [[package]] name = "cortex-m-rt-macros" version = "0.6.11" +source = "git+https://github.com/rust-embedded/cortex-m-rt.git?rev=a2e3ad5#a2e3ad54478c6b98e519a1b0946395d790c0b6c7" dependencies = [ "proc-macro2", "quote", diff --git a/Cargo.toml b/Cargo.toml index a18e5951f..e6559a02e 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -59,10 +59,8 @@ branch = "master" cc = "1.0" [patch.crates-io.cortex-m-rt] -path = "../cortex-m-rt" -# 0.6.13 -# git = "https://github.com/rust-embedded/cortex-m-rt.git" -# rev = "8c90451" +git = "https://github.com/rust-embedded/cortex-m-rt.git" +rev = "a2e3ad5" [patch.crates-io.miniconf] git = "https://github.com/quartiq/miniconf.git" From 23bdd816a7c70cda274f83d47f4ff3dacae63611 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 29 Apr 2021 16:44:12 +0200 Subject: [PATCH 05/12] dependencies: align with master --- Cargo.toml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index e6559a02e..3499ac3a6 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -47,14 +47,6 @@ smoltcp-nal = "0.1.0" miniconf = "0.1" generic-array = "0.14" -[dependencies.mcp23017] -git = "https://github.com/mrd0ll4r/mcp23017.git" - -[dependencies.stm32h7xx-hal] -features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] -git = "https://github.com/stm32-rs/stm32h7xx-hal" -branch = "master" - [build-dependencies] cc = "1.0" @@ -82,6 +74,14 @@ branch = "master" # a new release of smoltcp is made, we can remove this patch. git = "https://github.com/smoltcp-rs/smoltcp.git" +[dependencies.mcp23017] +git = "https://github.com/mrd0ll4r/mcp23017.git" + +[dependencies.stm32h7xx-hal] +features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] +git = "https://github.com/stm32-rs/stm32h7xx-hal" +branch = "master" + [features] semihosting = ["panic-semihosting", "cortex-m-log/semihosting"] bkpt = [ ] From 780b3441a21dbdbc3782a52d400cb7d1d84344f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 29 Apr 2021 17:33:20 +0200 Subject: [PATCH 06/12] fmt --- build.rs | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/build.rs b/build.rs index 3f9eaf986..d0c281d80 100644 --- a/build.rs +++ b/build.rs @@ -1,9 +1,6 @@ fn main() { println!("cargo:rerun-if-changed=memory.x"); - cc::Build::new() - .file("src/startup.S") - .compile("startup"); + cc::Build::new().file("src/startup.S").compile("startup"); println!("cargo:rerun-if-changed=src/startup.S"); } - From b8b3bc0873267a055a2a3709043d8b28baf44ca9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 29 Apr 2021 17:44:54 +0200 Subject: [PATCH 07/12] gha: install gcc --- .github/workflows/ci.yml | 2 ++ .github/workflows/release.yml | 1 + 2 files changed, 3 insertions(+) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index cf68b3f23..be5ebcc78 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -16,6 +16,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 + - run: sudo apt install gcc-arm-none-eabi - uses: actions-rs/toolchain@v1 with: toolchain: stable @@ -51,6 +52,7 @@ jobs: features: nightly steps: - uses: actions/checkout@v2 + - run: sudo apt install gcc-arm-none-eabi - uses: actions-rs/toolchain@v1 with: toolchain: ${{ matrix.toolchain }} diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 5be1311d5..50e0dd890 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -12,6 +12,7 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 + - run: sudo apt install gcc-arm-none-eabi - uses: actions-rs/toolchain@v1 with: toolchain: stable From ff5f3af8a49b0472be0c3e60a2d5925f237d2f83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 13 May 2021 15:22:44 +0200 Subject: [PATCH 08/12] remove duplicate linker option --- .cargo/config | 1 - 1 file changed, 1 deletion(-) diff --git a/.cargo/config b/.cargo/config index 0682cd08b..82780fa5d 100644 --- a/.cargo/config +++ b/.cargo/config @@ -2,7 +2,6 @@ runner = "probe-run --chip STM32H743ZITx --speed 30000" # runner = "gdb-multiarch -q -x openocd.gdb" rustflags = [ - "-C", "link-arg=--nmagic", "-C", "link-arg=-Tlink.x", "-C", "link-arg=--nmagic", "-C", "target-cpu=cortex-m7", From 4d5f1ab5e916494adeaff8f917548d8335b4191b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 14 May 2021 17:20:08 +0200 Subject: [PATCH 09/12] itcm: implement in rust and execute during setup() --- .github/workflows/ci.yml | 2 -- .github/workflows/release.yml | 1 - Cargo.lock | 7 ------ Cargo.toml | 3 --- build.rs | 3 --- src/hardware/configuration.rs | 30 ++++++++++++++++++++++++ src/startup.S | 44 ----------------------------------- 7 files changed, 30 insertions(+), 60 deletions(-) delete mode 100644 src/startup.S diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index be5ebcc78..cf68b3f23 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -16,7 +16,6 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - - run: sudo apt install gcc-arm-none-eabi - uses: actions-rs/toolchain@v1 with: toolchain: stable @@ -52,7 +51,6 @@ jobs: features: nightly steps: - uses: actions/checkout@v2 - - run: sudo apt install gcc-arm-none-eabi - uses: actions-rs/toolchain@v1 with: toolchain: ${{ matrix.toolchain }} diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 0463aa6a6..475c05ee0 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -12,7 +12,6 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - - run: sudo apt install gcc-arm-none-eabi - uses: actions-rs/toolchain@v1 with: toolchain: stable diff --git a/Cargo.lock b/Cargo.lock index a10d3c116..a85ba1825 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -102,12 +102,6 @@ dependencies = [ "rustc_version", ] -[[package]] -name = "cc" -version = "1.0.67" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e3c69b077ad434294d3ce9f1f6143a2a4b89a8a2d54ef813d85003a4fd1137fd" - [[package]] name = "cfg-if" version = "1.0.0" @@ -756,7 +750,6 @@ version = "0.5.0" dependencies = [ "ad9959", "asm-delay", - "cc", "cortex-m 0.7.2", "cortex-m-rt", "cortex-m-rtic", diff --git a/Cargo.toml b/Cargo.toml index 9fcec8196..63c1846a9 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -58,9 +58,6 @@ rev = "61933f857a" features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] version = "0.9.0" -[build-dependencies] -cc = "1.0" - [patch.crates-io.cortex-m-rt] git = "https://github.com/rust-embedded/cortex-m-rt.git" rev = "a2e3ad5" diff --git a/build.rs b/build.rs index d0c281d80..e71f6a660 100644 --- a/build.rs +++ b/build.rs @@ -1,6 +1,3 @@ fn main() { println!("cargo:rerun-if-changed=memory.x"); - - cc::Build::new().file("src/startup.S").compile("startup"); - println!("cargo:rerun-if-changed=src/startup.S"); } diff --git a/src/hardware/configuration.rs b/src/hardware/configuration.rs index f48b3d29f..f762d488e 100644 --- a/src/hardware/configuration.rs +++ b/src/hardware/configuration.rs @@ -105,6 +105,32 @@ pub struct PounderDevices { /// Static storage for the ethernet DMA descriptor ring. static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); +/// Setup ITCM and load its code from flash +unsafe fn setup_itcm() { + extern "C" { + static mut __sitcm: u32; + static mut __eitcm: u32; + static mut __siitcm: u32; + } + use core::{ptr, slice, sync::atomic}; + + // ITCM is enabled on reset on our CPU but might not be on others. + // Keep for completeness. + const ITCMCR: *mut u32 = 0xE000_EF90usize as _; + ptr::write_volatile(ITCMCR, ptr::read_volatile(ITCMCR) | 1); + atomic::fence(atomic::Ordering::SeqCst); + + let len = + (&__eitcm as *const u32).offset_from(&__sitcm as *const _) as usize; + let dst = slice::from_raw_parts_mut(&mut __sitcm as *mut _, len); + let src = slice::from_raw_parts(&__siitcm as *const _, len); + dst.copy_from_slice(src); + + atomic::fence(atomic::Ordering::SeqCst); + cortex_m::asm::dsb(); + cortex_m::asm::isb(); +} + /// Configure the stabilizer hardware for operation. /// /// # Args @@ -160,6 +186,10 @@ pub fn setup( log::info!("starting..."); } + unsafe { + setup_itcm(); + } + // Set up the system timer for RTIC scheduling. { let tim15 = diff --git a/src/startup.S b/src/startup.S deleted file mode 100644 index 3a5b6ea2d..000000000 --- a/src/startup.S +++ /dev/null @@ -1,44 +0,0 @@ -.cfi_sections .debug_frame - -# .thumb -.section .text.pre_init, "ax" -.globl __pre_init -.type __pre_init,%function -.thumb_func -.cfi_startproc -__pre_init: - - # Enable ITCM and DTCM - ldr r0, =1 - ldr r1, =0xE000EF90 - ldr r2, [r1] - # Set ITCMCR.EN - orr r2, r2, r0 - str r2, [r1] - ldr r1, =0xE000EF94 - ldr r2, [r1] - # Set DTCMCR.EN - orr r2, r2, r0 - str r2, [r1] - dsb - isb - - # Analogous to cortex-m-rt Reset code for .data copying. - # Initialise .itcm code. `__sitcm`, `__siitcm`, and `__eitcm` come from the - # linker script. Copy from r2 into r0 until r0 reaches r1. - ldr r0,=__sitcm - ldr r1,=__eitcm - ldr r2,=__siitcm -1: - cmp r1, r0 - beq 2f - # load 1 word from r2 to r3, inc r2 - ldm r2!, {r3} - # store 1 word from r3 to r0, inc r0 - stm r0!, {r3} - b 1b -2: - dsb - isb - bx lr -.cfi_endproc From 75a38dfba963a4d447b2a3af8cb7e86c3d7d7796 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 14 May 2021 17:36:47 +0200 Subject: [PATCH 10/12] deps: add rationales for git dependencies --- Cargo.toml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Cargo.toml b/Cargo.toml index 63c1846a9..00acb2249 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -46,10 +46,12 @@ miniconf = "0.1.0" shared-bus = {version = "0.2.2", features = ["cortex-m"] } serde-json-core = "0.3" +# rtt-target bump [dependencies.rtt-logger] git = "https://github.com/quartiq/rtt-logger.git" rev = "70b0eb5" +# rewrite [dependencies.mcp23017] git = "https://github.com/mrd0ll4r/mcp23017.git" rev = "61933f857a" @@ -58,6 +60,7 @@ rev = "61933f857a" features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"] version = "0.9.0" +# link.x section start/end [patch.crates-io.cortex-m-rt] git = "https://github.com/rust-embedded/cortex-m-rt.git" rev = "a2e3ad5" From c5d3837745e94f71dd01aed644f30edb27bd0aa7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 28 May 2021 16:03:40 +0200 Subject: [PATCH 11/12] itcm: add some comments, make it safe --- src/hardware/configuration.rs | 53 ++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 16 deletions(-) diff --git a/src/hardware/configuration.rs b/src/hardware/configuration.rs index f762d488e..23121dff7 100644 --- a/src/hardware/configuration.rs +++ b/src/hardware/configuration.rs @@ -105,8 +105,17 @@ pub struct PounderDevices { /// Static storage for the ethernet DMA descriptor ring. static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new(); -/// Setup ITCM and load its code from flash -unsafe fn setup_itcm() { +/// Setup ITCM and load its code from flash. +/// +/// For portability and maintainability this is implemented in Rust. +/// Since this is implemented in Rust the compiler may assume that bss and data are set +/// up already. There is no easy way to ensure this implementation will never need bss +/// or data. Hence we can't safely run this as the cortex-m-rt `pre_init` hook before +/// bss/data is setup. +/// +/// Calling (through IRQ or directly) any code in ITCM before having called +/// this method is undefined. +fn load_itcm() { extern "C" { static mut __sitcm: u32; static mut __eitcm: u32; @@ -114,18 +123,29 @@ unsafe fn setup_itcm() { } use core::{ptr, slice, sync::atomic}; - // ITCM is enabled on reset on our CPU but might not be on others. - // Keep for completeness. - const ITCMCR: *mut u32 = 0xE000_EF90usize as _; - ptr::write_volatile(ITCMCR, ptr::read_volatile(ITCMCR) | 1); - atomic::fence(atomic::Ordering::SeqCst); + // NOTE(unsafe): Assuming the address symbols from the linker as well as + // the source instruction data are all valid, this is safe as it only + // copies linker-prepared data to where the code expects it to be. + // Calling it multiple times is safe as well. - let len = - (&__eitcm as *const u32).offset_from(&__sitcm as *const _) as usize; - let dst = slice::from_raw_parts_mut(&mut __sitcm as *mut _, len); - let src = slice::from_raw_parts(&__siitcm as *const _, len); - dst.copy_from_slice(src); + unsafe { + // ITCM is enabled on reset on our CPU but might not be on others. + // Keep for completeness. + const ITCMCR: *mut u32 = 0xE000_EF90usize as _; + ptr::write_volatile(ITCMCR, ptr::read_volatile(ITCMCR) | 1); + + // Ensure ITCM is enabled before loading. + atomic::fence(atomic::Ordering::SeqCst); + + let len = + (&__eitcm as *const u32).offset_from(&__sitcm as *const _) as usize; + let dst = slice::from_raw_parts_mut(&mut __sitcm as *mut _, len); + let src = slice::from_raw_parts(&__siitcm as *const _, len); + // Load code into ITCM. + dst.copy_from_slice(src); + } + // Ensure ITCM is loaded before potentially executing any instructions from it. atomic::fence(atomic::Ordering::SeqCst); cortex_m::asm::dsb(); cortex_m::asm::isb(); @@ -183,12 +203,12 @@ pub fn setup( log::set_logger(&LOGGER) .map(|()| log::set_max_level(log::LevelFilter::Trace)) .unwrap(); - log::info!("starting..."); + log::info!("Starting"); } - unsafe { - setup_itcm(); - } + // Before being able to call any code in ITCM, load that code from flash. + log::info!("Loading ITCM"); + load_itcm(); // Set up the system timer for RTIC scheduling. { @@ -902,6 +922,7 @@ pub fn setup( #[cfg(feature = "pounder_v1_1")] let pounder_stamper = { + logger::info!("Pounder v1.1 or later"); let etr_pin = gpioa.pa0.into_alternate_af3(); // The frequency in the constructor is dont-care, as we will modify the period + clock From 79d30b4c6b454b0b5676331207b72a8a3e0e4072 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 28 May 2021 16:32:26 +0200 Subject: [PATCH 12/12] setup: cleanup --- src/hardware/configuration.rs | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/hardware/configuration.rs b/src/hardware/configuration.rs index 23121dff7..e2eb65351 100644 --- a/src/hardware/configuration.rs +++ b/src/hardware/configuration.rs @@ -207,7 +207,6 @@ pub fn setup( } // Before being able to call any code in ITCM, load that code from flash. - log::info!("Loading ITCM"); load_itcm(); // Set up the system timer for RTIC scheduling. @@ -922,7 +921,7 @@ pub fn setup( #[cfg(feature = "pounder_v1_1")] let pounder_stamper = { - logger::info!("Pounder v1.1 or later"); + log::info!("Assuming Pounder v1.1 or later"); let etr_pin = gpioa.pa0.into_alternate_af3(); // The frequency in the constructor is dont-care, as we will modify the period + clock @@ -985,13 +984,13 @@ pub fn setup( digital_inputs, }; + // Enable the instruction cache. + core.SCB.enable_icache(); + // info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap()); // info!("Built on {}", build_info::BUILT_TIME_UTC); // info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET); log::info!("setup() complete"); - // Enable the instruction cache. - core.SCB.enable_icache(); - (stabilizer, pounder) }