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Help..I can't reproduce conditonal branch attack on boom-core in chipyard #4
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Same. The interesting thing is that the attack works for the first character, this makes me think the problem is the the cache flush. |
Same for me. The branch prediction implementation has also changed a lot since the last commit on this project, so the branch predictor training done on the old implementation of BOOM may not work on the new implementation of how branch prediction is done. |
I have intestigated this behaviour during an internship. It's quite dumb : the new TAGE-L branch predictor has a loop predictor, which make a constant length loop work only as long as the loop predictor doesn't kick in. A small +1/-1 variation is enough to make the attack work as it did before. |
You mean like this? I am building this solution now to see if it solves the problem! class WithTAGELBPD extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
bpdMaxMetaLength = 120,
globalHistoryLength = 64,
localHistoryLength = 1,
localHistoryNSets = 0,
branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => {
//val loop = Module(new LoopBranchPredictorBank()(p)) <------
val tage = Module(new TageBranchPredictorBank()(p))
val btb = Module(new BTBBranchPredictorBank()(p))
val bim = Module(new BIMBranchPredictorBank()(p))
val ubtb = Module(new FAMicroBTBBranchPredictorBank()(p))
val preds = Seq(/*loop, */tage, btb, ubtb, bim) <------
preds.map(_.io := DontCare)
ubtb.io.resp_in(0) := resp_in
bim.io.resp_in(0) := ubtb.io.resp
btb.io.resp_in(0) := bim.io.resp
tage.io.resp_in(0) := btb.io.resp
//loop.io.resp_in(0) := tage.io.resp <---------
(preds, tage.io.resp) // loop.io.resp) <---------
})
)))
case other => other
}
}) |
I must admit I didn't test it like this, only by making the loops vary in length here (I think I just added for(uint64_t atkRound = 0; atkRound < ATTACK_SAME_ROUNDS; ++atkRound){
// make sure array you read from is not in the cache
flushCache((uint64_t)array2, sizeof(array2));
for(int64_t j = ((TRAIN_TIMES+1)*ROUNDS)-1; j >= 0; --j){
// bit twiddling to set passInIdx=randIdx or to attackIdx after TRAIN_TIMES iterations
// avoid jumps in case those tip off the branch predictor
// note: randIdx changes everytime the atkRound changes so that the tally does not get affected
// training creates a false hit in array2 for that array1 value (you want this to be ignored by having it changed)
randIdx = atkRound % array1_sz;
passInIdx = ((j % (TRAIN_TIMES+1)) - 1) & ~0xFFFF; // after every TRAIN_TIMES set passInIdx=...FFFF0000 else 0
passInIdx = (passInIdx | (passInIdx >> 16)); // set the passInIdx=-1 or 0
passInIdx = randIdx ^ (passInIdx & (attackIdx ^ randIdx)); // select randIdx or attackIdx |
Looks like it worked when I commented ut the loop predictor! Thank you @DorianXGH !
|
my chipyard version is f387c4b99424e869235f927aebcb7dabc643a6f5
and I use
CONFIG=LargeBoomConfig
orCONFIG=MediumBoomConfig
to make verilator and vcs simulator , but using the both two to simulate is not work:The text was updated successfully, but these errors were encountered: