From 42ba992f0196a6538dc4bbab432d620b0cd9b9b2 Mon Sep 17 00:00:00 2001
From: Chien Wong <m@xv97.com>
Date: Sat, 25 Nov 2023 22:26:53 +0800
Subject: [PATCH] Fix build error that assigning to `&T` is undefined behavior

Signed-off-by: Chien Wong <m@xv97.com>
---
 src/serial.rs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/serial.rs b/src/serial.rs
index da4c404..8492fde 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -31,6 +31,7 @@
 //! let received = block!(rx.read()).unwrap();
 //!  ```
 
+use core::cell::UnsafeCell;
 use core::marker::PhantomData;
 use core::ptr;
 
@@ -419,7 +420,7 @@ impl<USART: UsartX> crate::hal::serial::Write<u8> for Tx<USART> {
             // NOTE(unsafe) atomic write to stateless register
             // NOTE(write_volatile) 8-bit write that's not possible through the svd2rust API
             unsafe {
-                ptr::write_volatile(&(*USART::ptr()).data as *const _ as *mut _, byte)
+                ptr::write_volatile(UnsafeCell::raw_get(&(*USART::ptr()).data as *const _ as _), byte);
             }
             Ok(())
         } else {