From c82e57d359030454be9158cfd4989c651c613b1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 7 Dec 2022 17:33:54 +0100 Subject: [PATCH 01/21] Add vscode debug config --- .vscode/launch.json | 24 ++++++++++++++++++++++++ .vscode/settings.json | 3 +++ .vscode/tasks.json | 19 +++++++++++++++++++ Cargo.toml | 3 ++- 4 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 .vscode/launch.json create mode 100644 .vscode/settings.json create mode 100644 .vscode/tasks.json diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..edd9225 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,24 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Hifive1 (Debug)", + // (rev-b) Substitute with the board number + "device": "FE310", + "type": "cortex-debug", + "preLaunchTask": "build-hifive", + // Defined in tasks.json + "request": "launch", + "servertype": "jlink", + // "showDevDebugOutput": "raw", + "cwd": "${workspaceRoot}", + // Executable to launch + "executable": "${workspaceRoot}/target/riscv32imac-unknown-none-elf/debug/hifive1-example", + "interface": "jtag", + "svdFile": "${workspaceRoot}/hifive.svd", + // Set this to point to risc-v gdb path + "gdbPath": "${workspaceRoot}/../../Toolchains/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-amd64/riscv32-esp-elf/bin/riscv32-esp-elf-gdb", + "toolchainPrefix": "riscv32-esp-elf", + }, + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..4302e07 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cortex-debug.variableUseNaturalFormat": true +} \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..92911de --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,19 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "build-hifive", + "command": "cargo", + "args": [ + "build", + ], + "problemMatcher": [ + "$rustc" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + ] +} diff --git a/Cargo.toml b/Cargo.toml index 601da86..8a40c84 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -10,7 +10,7 @@ license = "ISC" edition = "2018" [dependencies] -e310x-hal = "0.9.1" +e310x-hal = {path = "../e310x-hal"} embedded-hal = "0.2.5" riscv = "0.6.0" nb = "1.0.0" @@ -21,6 +21,7 @@ board-hifive1-revb = ["e310x-hal/g002"] board-redv = ["e310x-hal/g002"] board-lofive = [] board-lofive-r1 = ["e310x-hal/g002"] +virq = ["e310x-hal/virq"] [package.metadata.docs.rs] features = ['board-hifive1-revb'] From a5245e88f0912f4d7b2ba80c21cb225bd6725d04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Mon, 12 Dec 2022 17:09:50 +0100 Subject: [PATCH 02/21] Add debug config and virq example --- .cargo/config | 2 + .vscode/launch.json | 2 +- Cargo.toml | 4 +- examples/virq.rs | 96 +++++++++++++++++++++++++++++++++++++++++++++ hifive1-link.x | 1 + 5 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 .cargo/config create mode 100644 examples/virq.rs diff --git a/.cargo/config b/.cargo/config new file mode 100644 index 0000000..323d097 --- /dev/null +++ b/.cargo/config @@ -0,0 +1,2 @@ +[build] +target = "riscv32imac-unknown-none-elf" \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json index edd9225..ad9c4b8 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -17,7 +17,7 @@ "interface": "jtag", "svdFile": "${workspaceRoot}/hifive.svd", // Set this to point to risc-v gdb path - "gdbPath": "${workspaceRoot}/../../Toolchains/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-amd64/riscv32-esp-elf/bin/riscv32-esp-elf-gdb", + "gdbPath": "${workspaceRoot}/riscv32-esp-elf-gdb", "toolchainPrefix": "riscv32-esp-elf", }, ] diff --git a/Cargo.toml b/Cargo.toml index 8a40c84..8261881 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -10,10 +10,12 @@ license = "ISC" edition = "2018" [dependencies] -e310x-hal = {path = "../e310x-hal"} +e310x-hal = {git = "https://github.com/greenlsi/e310x-hal"} embedded-hal = "0.2.5" riscv = "0.6.0" +riscv-rt = "0.10.0" nb = "1.0.0" +panic-halt = "0.2.0" [features] board-hifive1 = [] diff --git a/examples/virq.rs b/examples/virq.rs new file mode 100644 index 0000000..75e026c --- /dev/null +++ b/examples/virq.rs @@ -0,0 +1,96 @@ +#![no_main] +#![no_std] + +/* + Demonstration on how to use the feature "virq" from e310x-hal. +This feature enables a kind of vectorized interrupt matching for +all 52 the external interrupts that e310x has. It simply offers a convenient +way to handle each interrupt separately with a function called as the interrupt source. +For example, if an interrupt for GPIO0 is received, and a no mangled function called GPIO0() +exists, that function will automatically handle the exception, and it will be automatically +marked as complete by the PLIC. +This can be applied for all the 52 interrupts declared in e310x/interrupts.rs. +*/ + +extern crate panic_halt; + +use hifive1::{ + hal::core::plic::Priority, + hal::core::CorePeripherals, + hal::DeviceResources, + hal::{ + core::plic::{self, INTERRUPT}, + e310x::{ + interrupt::Interrupt, + plic::{priority, PRIORITY}, + GPIO0, PLIC, + }, + gpio::gpio0, + prelude::*, + }, + pin, sprintln, +}; +use riscv::register::mstatus; +use riscv_rt::entry; + +/* Handler for the GPIO0 interrupt */ +#[no_mangle] +fn GPIO0() { + sprintln!("We reached the GPIO0 interrupt!"); +} + +/* Code adapted from https://github.com/riscv-rust/riscv-rust-quickstart/blob/interrupt-test/examples/interrupt.rs*/ +#[entry] +fn main() -> ! { + /* Get the ownership of the device resources singleton */ + let resources = DeviceResources::take().unwrap(); + let peripherals = resources.peripherals; + + /* Configure system clock */ + let sysclock = hifive1::configure_clocks(peripherals.PRCI, peripherals.AONCLK, 64.mhz().into()); + /* Get the board pins */ + let gpio = resources.pins; + + /* Configure stdout for debugging */ + hifive1::stdout::configure( + peripherals.UART0, + pin!(gpio, uart0_tx), + pin!(gpio, uart0_rx), + 115_200.bps(), + sysclock, + ); + + /* Set GPIO0 (pin 16) as input */ + let gpio0 = pin!(gpio, dig16); + _ = gpio0.into_pull_up_input(); + + /* Wrapper for easy access */ + let mut plic = resources.core_peripherals.plic; + + /* Unsafe block */ + unsafe { + /* Get raw PLIC pointer */ + let rplic = &*hifive1::hal::e310x::PLIC::ptr(); + let gpio0_index = 7; + /* Index 7 is the GPIO0 interrupt source, so we modify it's priority */ + for (i, p) in rplic.priority.iter().enumerate() { + if i == gpio0_index { + p.write(|w| w.bits(0xffffffff)); + } else { + /* Clear all other priorities */ + p.write(|w| w.bits(0)); + } + } + let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); + /* Enable GPIO fall interrupts */ + gpio_block.fall_ie.write(|w| w.bits(0xffffffff)); + /* Clear pending interrupts */ + gpio_block.fall_ip.write(|w| w.bits(0xffffffff)); + + /* Activate global interrupts (mie bit) */ + mstatus::set_mie(); + plic.threshold.set(Priority::P1); + plic.mext.enable(); + } + loop {} +} diff --git a/hifive1-link.x b/hifive1-link.x index c472d9b..daeba82 100644 --- a/hifive1-link.x +++ b/hifive1-link.x @@ -1,2 +1,3 @@ INCLUDE hifive1-memory.x INCLUDE link.x +INCLUDE interrupts.x \ No newline at end of file From 74a2048e10512520d5bdb654736736473bb8de5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Mon, 12 Dec 2022 17:44:24 +0100 Subject: [PATCH 03/21] add features to tasks.json --- .cargo/config | 6 ++++++ .vscode/launch.json | 3 ++- .vscode/tasks.json | 3 +++ examples/virq.rs | 2 +- gdb_init | 9 +++++++++ 5 files changed, 21 insertions(+), 2 deletions(-) create mode 100644 gdb_init diff --git a/.cargo/config b/.cargo/config index 323d097..a6dfeb9 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,2 +1,8 @@ +[target.riscv32imac-unknown-none-elf] +runner = "../../Toolchains/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gdb -q -x gdb_init" +rustflags = [ + "-C", "link-arg=-Thifive1-link.x", +] + [build] target = "riscv32imac-unknown-none-elf" \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json index ad9c4b8..48c5a6f 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -17,7 +17,8 @@ "interface": "jtag", "svdFile": "${workspaceRoot}/hifive.svd", // Set this to point to risc-v gdb path - "gdbPath": "${workspaceRoot}/riscv32-esp-elf-gdb", + "gdbPath": "${workspaceRoot}/../../Toolchains/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-amd64/riscv32-esp-elf/bin/riscv32-esp-elf-gdb", // Set this to point to Espressif's GDB version + // "gdbPath": "${workspaceRoot}/riscv32-esp-elf-gdb", "toolchainPrefix": "riscv32-esp-elf", }, ] diff --git a/.vscode/tasks.json b/.vscode/tasks.json index 92911de..6fdaeac 100644 --- a/.vscode/tasks.json +++ b/.vscode/tasks.json @@ -6,6 +6,9 @@ "command": "cargo", "args": [ "build", + "--features=\"virq board-redv\"", + "--example", + "virq" ], "problemMatcher": [ "$rustc" diff --git a/examples/virq.rs b/examples/virq.rs index 75e026c..0a5921e 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -74,7 +74,7 @@ fn main() -> ! { let gpio0_index = 7; /* Index 7 is the GPIO0 interrupt source, so we modify it's priority */ for (i, p) in rplic.priority.iter().enumerate() { - if i == gpio0_index { + if i > 0 && i < 52 { p.write(|w| w.bits(0xffffffff)); } else { /* Clear all other priorities */ diff --git a/gdb_init b/gdb_init new file mode 100644 index 0000000..d6e49b6 --- /dev/null +++ b/gdb_init @@ -0,0 +1,9 @@ +set history save on +set confirm off +set remotetimeout 240 +target extended-remote :3333 +set print asm-demangle on +monitor reset halt +load +continue +# quit From ec1a528aa12e0583fc4a99dfcaad3120a0ba460a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 14 Dec 2022 14:23:50 +0100 Subject: [PATCH 04/21] Fixed example and .json files --- .vscode/launch.json | 4 +- .vscode/tasks.json | 5 +- examples/virq.rs | 27 +- hifive.svd | 3169 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 3191 insertions(+), 14 deletions(-) create mode 100644 hifive.svd diff --git a/.vscode/launch.json b/.vscode/launch.json index 48c5a6f..a62dca9 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -3,7 +3,7 @@ "configurations": [ { "name": "Hifive1 (Debug)", - // (rev-b) Substitute with the board number + // Substitute with the board number "device": "FE310", "type": "cortex-debug", "preLaunchTask": "build-hifive", @@ -13,7 +13,7 @@ // "showDevDebugOutput": "raw", "cwd": "${workspaceRoot}", // Executable to launch - "executable": "${workspaceRoot}/target/riscv32imac-unknown-none-elf/debug/hifive1-example", + "executable": "${workspaceRoot}/target/riscv32imac-unknown-none-elf/debug/examples/virq", "interface": "jtag", "svdFile": "${workspaceRoot}/hifive.svd", // Set this to point to risc-v gdb path diff --git a/.vscode/tasks.json b/.vscode/tasks.json index 6fdaeac..6d2affc 100644 --- a/.vscode/tasks.json +++ b/.vscode/tasks.json @@ -6,9 +6,8 @@ "command": "cargo", "args": [ "build", - "--features=\"virq board-redv\"", - "--example", - "virq" + "--features=board-redv,virq", + "--example=virq" ], "problemMatcher": [ "$rustc" diff --git a/examples/virq.rs b/examples/virq.rs index 0a5921e..ca6738a 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -35,8 +35,14 @@ use riscv_rt::entry; /* Handler for the GPIO0 interrupt */ #[no_mangle] -fn GPIO0() { - sprintln!("We reached the GPIO0 interrupt!"); +#[allow(non_snake_case)] +fn GPIO4() { + sprintln!("We reached the GPIO4 interrupt!"); + /* Clear the GPIO pending interrupt */ + unsafe { + let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); + gpio_block.fall_ip.write(|w| w.bits(0xffffffff)); + } } /* Code adapted from https://github.com/riscv-rust/riscv-rust-quickstart/blob/interrupt-test/examples/interrupt.rs*/ @@ -60,9 +66,9 @@ fn main() -> ! { sysclock, ); - /* Set GPIO0 (pin 16) as input */ - let gpio0 = pin!(gpio, dig16); - _ = gpio0.into_pull_up_input(); + /* Set GPIO4 (pin 12) as input */ + let gpio4 = pin!(gpio, dig12); + _ = gpio4.into_pull_up_input(); /* Wrapper for easy access */ let mut plic = resources.core_peripherals.plic; @@ -71,10 +77,11 @@ fn main() -> ! { unsafe { /* Get raw PLIC pointer */ let rplic = &*hifive1::hal::e310x::PLIC::ptr(); - let gpio0_index = 7; - /* Index 7 is the GPIO0 interrupt source, so we modify it's priority */ + let gpio0_block_start = 7; + /* Index 7 is the GPIO0 interrupt source start */ for (i, p) in rplic.priority.iter().enumerate() { - if i > 0 && i < 52 { + /* set priority of our interrupt */ + if i == gpio0_block_start + 5 { p.write(|w| w.bits(0xffffffff)); } else { /* Clear all other priorities */ @@ -84,8 +91,10 @@ fn main() -> ! { let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); /* Enable GPIO fall interrupts */ gpio_block.fall_ie.write(|w| w.bits(0xffffffff)); - /* Clear pending interrupts */ + gpio_block.rise_ie.write(|w| w.bits(0x0)); + /* Clear pending interrupts from previous states */ gpio_block.fall_ip.write(|w| w.bits(0xffffffff)); + gpio_block.rise_ip.write(|w| w.bits(0x0)); /* Activate global interrupts (mie bit) */ mstatus::set_mie(); diff --git a/hifive.svd b/hifive.svd new file mode 100644 index 0000000..3ad2768 --- /dev/null +++ b/hifive.svd @@ -0,0 +1,3169 @@ + + + sifive_hifive1_revb + 0.1 + From sifive,hifive1-revb,model device generator + 8 + 32 + 32 + read-write + + + riscv_clint0_0 + From riscv,clint0,control peripheral generator + 0x2000000 + + 0 + 0x10000 + registers + + + + msip_0 + MSIP Register for hart 0 + 0x0 + + + mtimecmp_0 + MTIMECMP Register for hart 0 + 0x4000 + 64 + + + mtime + MTIME Register + 0xBFF8 + 64 + + + + + riscv_plic0_0 + From riscv,plic0,control peripheral generator + 0xC000000 + + 0 + 0x4000000 + registers + + + + priority_1 + PRIORITY Register for interrupt id 1 + 0x4 + + + priority_2 + PRIORITY Register for interrupt id 2 + 0x8 + + + priority_3 + PRIORITY Register for interrupt id 3 + 0xC + + + priority_4 + PRIORITY Register for interrupt id 4 + 0x10 + + + priority_5 + PRIORITY Register for interrupt id 5 + 0x14 + + + priority_6 + PRIORITY Register for interrupt id 6 + 0x18 + + + priority_7 + PRIORITY Register for interrupt id 7 + 0x1C + + + priority_8 + PRIORITY Register for interrupt id 8 + 0x20 + + + priority_9 + PRIORITY Register for interrupt id 9 + 0x24 + + + priority_10 + PRIORITY Register for interrupt id 10 + 0x28 + + + priority_11 + PRIORITY Register for interrupt id 11 + 0x2C + + + priority_12 + PRIORITY Register for interrupt id 12 + 0x30 + + + priority_13 + PRIORITY Register for interrupt id 13 + 0x34 + + + priority_14 + PRIORITY Register for interrupt id 14 + 0x38 + + + priority_15 + PRIORITY Register for interrupt id 15 + 0x3C + + + priority_16 + PRIORITY Register for interrupt id 16 + 0x40 + + + priority_17 + PRIORITY Register for interrupt id 17 + 0x44 + + + priority_18 + PRIORITY Register for interrupt id 18 + 0x48 + + + priority_19 + PRIORITY Register for interrupt id 19 + 0x4C + + + priority_20 + PRIORITY Register for interrupt id 20 + 0x50 + + + priority_21 + PRIORITY Register for interrupt id 21 + 0x54 + + + priority_22 + PRIORITY Register for interrupt id 22 + 0x58 + + + priority_23 + PRIORITY Register for interrupt id 23 + 0x5C + + + priority_24 + PRIORITY Register for interrupt id 24 + 0x60 + + + priority_25 + PRIORITY Register for interrupt id 25 + 0x64 + + + priority_26 + PRIORITY Register for interrupt id 26 + 0x68 + + + priority_27 + PRIORITY Register for interrupt id 27 + 0x6C + + + priority_28 + PRIORITY Register for interrupt id 28 + 0x70 + + + priority_29 + PRIORITY Register for interrupt id 29 + 0x74 + + + priority_30 + PRIORITY Register for interrupt id 30 + 0x78 + + + priority_31 + PRIORITY Register for interrupt id 31 + 0x7C + + + priority_32 + PRIORITY Register for interrupt id 32 + 0x80 + + + priority_33 + PRIORITY Register for interrupt id 33 + 0x84 + + + priority_34 + PRIORITY Register for interrupt id 34 + 0x88 + + + priority_35 + PRIORITY Register for interrupt id 35 + 0x8C + + + priority_36 + PRIORITY Register for interrupt id 36 + 0x90 + + + priority_37 + PRIORITY Register for interrupt id 37 + 0x94 + + + priority_38 + PRIORITY Register for interrupt id 38 + 0x98 + + + priority_39 + PRIORITY Register for interrupt id 39 + 0x9C + + + priority_40 + PRIORITY Register for interrupt id 40 + 0xA0 + + + priority_41 + PRIORITY Register for interrupt id 41 + 0xA4 + + + priority_42 + PRIORITY Register for interrupt id 42 + 0xA8 + + + priority_43 + PRIORITY Register for interrupt id 43 + 0xAC + + + priority_44 + PRIORITY Register for interrupt id 44 + 0xB0 + + + priority_45 + PRIORITY Register for interrupt id 45 + 0xB4 + + + priority_46 + PRIORITY Register for interrupt id 46 + 0xB8 + + + priority_47 + PRIORITY Register for interrupt id 47 + 0xBC + + + priority_48 + PRIORITY Register for interrupt id 48 + 0xC0 + + + priority_49 + PRIORITY Register for interrupt id 49 + 0xC4 + + + priority_50 + PRIORITY Register for interrupt id 50 + 0xC8 + + + priority_51 + PRIORITY Register for interrupt id 51 + 0xCC + + + priority_52 + PRIORITY Register for interrupt id 52 + 0xD0 + + + pending_0 + PENDING Register for interrupt ids 31 to 0 + 0x1000 + + + pending_1 + PENDING Register for interrupt ids 52 to 32 + 0x1004 + + + enable_0_0 + ENABLE Register for interrupt ids 31 to 0 for hart 0 + 0x2000 + + + enable_1_0 + ENABLE Register for interrupt ids 52 to 32 for hart 0 + 0x2004 + + + threshold_0 + PRIORITY THRESHOLD Register for hart 0 + 0x200000 + + + claimplete_0 + CLAIM and COMPLETE Register for hart 0 + 0x200004 + + + + + sifive_aon0_0 + From sifive,aon0,mem peripheral generator + 0x10000000 + + 0 + 0x8000 + registers + + + + backup_0 + Backup Register 0 + 0x80 + + + backup_1 + Backup Register 1 + 0x84 + + + backup_2 + Backup Register 2 + 0x88 + + + backup_3 + Backup Register 3 + 0x8C + + + backup_4 + Backup Register 4 + 0x90 + + + backup_5 + Backup Register 5 + 0x94 + + + backup_6 + Backup Register 6 + 0x98 + + + backup_7 + Backup Register 7 + 0x9C + + + backup_8 + Backup Register 8 + 0xA0 + + + backup_9 + Backup Register 9 + 0xA4 + + + backup_10 + Backup Register 10 + 0xA8 + + + backup_11 + Backup Register 11 + 0xAC + + + backup_12 + Backup Register 12 + 0xB0 + + + backup_13 + Backup Register 13 + 0xB4 + + + backup_14 + Backup Register 14 + 0xB8 + + + backup_15 + Backup Register 15 + 0xBC + + + wdogcfg + wdog Configuration + 0x0 + + + wdogscale + Counter scale value. + [3:0] + read-write + + + wdogrsten + Controls whether the comparator output can set the wdogrst bit and hence cause a full reset. + [8:8] + read-write + + + wdogzerocmp + Reset counter to zero after match. + [9:9] + read-write + + + wdogenalways + Enable Always - run continuously + [12:12] + read-write + + + wdogcoreawake + Increment the watchdog counter if the processor is not asleep + [13:13] + read-write + + + wdogip0 + Interrupt 0 Pending + [28:28] + read-write + + + + + wdogcount + Counter Register + 0x8 + + + wdogs + Scaled value of Counter + 0x10 + + + wdogfeed + Feed register + 0x18 + + + wdogkey + Key Register + 0x1C + + + wdogcmp0 + Comparator 0 + 0x20 + + + rtccfg + rtc Configuration + 0x40 + + + rtcscale + Counter scale value. + [3:0] + read-write + + + rtcenalways + Enable Always - run continuously + [12:12] + read-write + + + rtcip0 + Interrupt 0 Pending + [28:28] + read-write + + + + + rtccountlo + Low bits of Counter + 0x48 + + + rtccounthi + High bits of Counter + 0x4C + + + rtcs + Scaled value of Counter + 0x50 + + + rtccmp0 + Comparator 0 + 0x60 + + + pmuwakeupi0 + Wakeup program instruction 0 + 0x100 + + + pmuwakeupi1 + Wakeup program instruction 1 + 0x104 + + + pmuwakeupi2 + Wakeup program instruction 2 + 0x108 + + + pmuwakeupi3 + Wakeup program instruction 3 + 0x10C + + + pmuwakeupi4 + Wakeup program instruction 4 + 0x110 + + + pmuwakeupi5 + Wakeup program instruction 5 + 0x114 + + + pmuwakeupi6 + Wakeup program instruction 6 + 0x118 + + + pmuwakeupi7 + Wakeup program instruction 7 + 0x11C + + + pmusleepi0 + Sleep program instruction 0 + 0x120 + + + pmusleepi1 + Sleep program instruction 1 + 0x124 + + + pmusleepi2 + Sleep program instruction 2 + 0x128 + + + pmusleepi3 + Sleep program instruction 3 + 0x12C + + + pmusleepi4 + Sleep program instruction 4 + 0x130 + + + pmusleepi5 + Sleep program instruction 5 + 0x134 + + + pmusleepi6 + Sleep program instruction 6 + 0x138 + + + pmusleepi7 + Sleep program instruction 7 + 0x13C + + + pmuie + PMU Interrupt Enables + 0x140 + + + pmucause + PMU Wakeup Cause + 0x144 + + + pmusleep + Initiate PMU Sleep Sequence + 0x148 + + + pmukey + PMU Key. Reads as 1 when PMU is unlocked + 0x14C + + + aoncfg + AON Block Configuration Information + 0x300 + + + has_bandgap + Bandgap feature is present + [0:0] + read-only + + + has_bod + Brownout detector feature is present + [1:1] + read-only + + + has_lfrosc + Low Frequency Ring Oscillator feature is present + [2:2] + read-only + + + has_lfrcosc + Low Frequency RC Oscillator feature is present + [3:3] + read-only + + + has_lfxosc + Low Frequency Crystal Oscillator feature is present + [4:4] + read-only + + + has_por + Power-On-Reset feature is present + [5:5] + read-only + + + has_ldo + Low Dropout Regulator feature is present + [6:6] + read-only + + + + + lfrosccfg + Ring Oscillator Configuration and Status + 0x70 + + + lfroscdiv + Ring Oscillator Divider Register + [5:0] + read-write + + + lfrosctrim + Ring Oscillator Trim Register + [20:16] + read-write + + + lfroscen + Ring Oscillator Enable + [30:30] + read-write + + + lfroscrdy + Ring Oscillator Ready + [31:31] + read-only + + + + + lfclkmux + Low-Frequency Clock Mux Control and Status + 0x7C + + + lfextclk_sel + Low Frequency Clock Source Selector + [0:0] + read-write + + + internal + Use internal LF clock source + 0 + + + external + Use external LF clock source + 1 + + + + + lfextclk_mux_status + Setting of the aon_lfclksel pin + [31:31] + read-only + + + external + Use external LF clock source + 0 + + + sw + Use clock source selected by lfextclk_sel + 1 + + + + + + + + + sifive_fe310_g000_prci_0 + From sifive,fe310-g000,prci,mem peripheral generator + 0x10008000 + + 0 + 0x8000 + registers + + + + hfrosccfg + Ring Oscillator Configuration and Status + 0x0 + + + hfroscdiv + Ring Oscillator Divider Register + [5:0] + read-write + + + hfrosctrim + Ring Oscillator Trim Register + [20:16] + read-write + + + hfroscen + Ring Oscillator Enable + [30:30] + read-write + + + hfroscrdy + Ring Oscillator Ready + [31:31] + read-only + + + + + hfxosccfg + Crystal Oscillator Configuration and Status + 0x4 + + + hfxoscen + Crystal Oscillator Enable + [30:30] + read-write + + + hfxoscrdy + Crystal Oscillator Ready + [31:31] + read-only + + + + + pllcfg + PLL Configuration and Status + 0x8 + + + pllr + PLL R Value + [2:0] + read-write + + + pllf + PLL F Value + [9:4] + read-write + + + pllq + PLL Q Value + [11:10] + read-write + + + pllsel + PLL Select + [16:16] + read-write + + + pllrefsel + PLL Reference Select + [17:17] + read-write + + + pllbypass + PLL Bypass + [18:18] + read-write + + + plllock + PLL Lock + [31:31] + read-only + + + + + plloutdiv + PLL Final Divide Configuration + 0xC + + + plloutdiv + PLL Final Divider Value + [5:0] + read-write + + + plloutdivby1 + PLL Final Divide By 1 + [13:8] + read-write + + + + + procmoncfg + Process Monitor Configuration and Status + 0xF0 + + + procmon_div_sel + Proccess Monitor Divider + [4:0] + read-write + + + procmon_delay_sel + Process Monitor Delay Selector + [12:8] + read-write + + + procmon_en + Process Monitor Enable + [16:16] + read-write + + + procomon_sel + Process Monitor Select + [25:24] + read-write + + + + + + + sifive_gpio0_0 + From sifive,gpio0,control peripheral generator + 0x10012000 + + 0 + 0x1000 + registers + + + + input_val + Pin value + 0x0 + + + input_en + Pin input enable + 0x4 + + + output_en + Pin output enable + 0x8 + + + output_val + Output value + 0xC + + + pue + Internal pull-up enable + 0x10 + + + ds + Pin drive strength + 0x14 + + + rise_ie + Rise interrupt enable + 0x18 + + + rise_ip + Rise interrupt pending + 0x1C + + + fall_ie + Fall interrupt enable + 0x20 + + + fall_ip + Fall interrupt pending + 0x24 + + + high_ie + High interrupt enable + 0x28 + + + high_ip + High interrupt pending + 0x2C + + + low_ie + Low interrupt enable + 0x30 + + + low_ip + Low interrupt pending + 0x34 + + + iof_en + I/O function enable + 0x38 + + + iof_sel + I/O function select + 0x3C + + + out_xor + Output XOR (invert) + 0x40 + + + + + sifive_uart0_0 + From sifive,uart0,control peripheral generator + 0x10013000 + + 0 + 0x1000 + registers + + + + txdata + Transmit data register + 0x0 + + + data + Transmit data + [7:0] + read-write + + + full + Transmit FIFO full + [31:31] + read-only + + + + + rxdata + Receive data register + 0x4 + + + data + Received data + [7:0] + read-only + + + empty + Receive FIFO empty + [31:31] + read-only + + + + + txctrl + Transmit control register + 0x8 + + + txen + Transmit enable + [0:0] + read-write + + + nstop + Number of stop bits + [1:1] + read-write + + + txcnt + Transmit watermark level + [18:16] + read-write + + + + + rxctrl + Receive control register + 0xC + + + rxen + Receive enable + [0:0] + read-write + + + rxcnt + Receive watermark level + [18:16] + read-write + + + + + ie + UART interrupt enable + 0x10 + + + txwm + Transmit watermark interrupt enable + [0:0] + read-write + + + rxwm + Receive watermark interrupt enable + [1:1] + read-write + + + + + ip + UART interrupt pending + 0x14 + + + txwm + Transmit watermark interrupt pending + [0:0] + read-only + + + rxwm + Receive watermark interrupt pending + [1:1] + read-only + + + + + div + Baud rate divisor + 0x18 + + + div + Baud rate divisor. + [15:0] + read-write + + + + + + + sifive_spi0_0 + From sifive,spi0,control peripheral generator + 0x10014000 + + 0 + 0x1000 + registers + + + + sckdiv + Serial clock divisor + 0x0 + + + div + Divisor for serial clock. + [11:0] + read-write + + + + + sckmode + Serial clock mode + 0x4 + + + pha + Serial clock phase + [0:0] + read-write + + + pol + Serial clock polarity + [1:1] + read-write + + + + + csid + Chip select ID + 0x10 + + + csid + Chip select ID. + [31:0] + read-write + + + + + csdef + Chip select default + 0x14 + + + csdef + Chip select default value. Reset to all-1s. + [31:0] + read-write + + + + + csmode + Chip select mode + 0x18 + + + mode + Chip select mode + [1:0] + read-write + + + + + delay0 + Delay control 0 + 0x28 + + + cssck + CS to SCK Delay + [7:0] + read-write + + + sckcs + SCK to CS Delay + [23:16] + read-write + + + + + delay1 + Delay control 1 + 0x2C + + + intercs + Minimum CS inactive time + [7:0] + read-write + + + interxfr + Maximum interframe delay + [23:16] + read-write + + + + + extradel + SPI extra sampling delay to increase the SPI frequency + 0x38 + + + coarse + Coarse grain sample delay (multiples of system clocks) + [11:0] + read-write + + + fine + Fine grain sample delay (multiples of process-specific buffer delay) + [16:12] + read-write + + + + + sampledel + Number of delay stages from slave to the SPI controller + 0x3C + + + sd + Number of delay stages from slave to SPI controller + [4:0] + read-write + + + + + fmt + Frame format + 0x40 + + + proto + SPI protocol + [1:0] + read-write + + + endian + SPI endianness + [2:2] + read-write + + + dir + SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise. + [3:3] + read-write + + + len + Number of bits per frame + [19:16] + read-write + + + + + txdata + Tx FIFO Data + 0x48 + + + data + Transmit data + [7:0] + read-write + + + full + FIFO full flag + [31:31] + read-only + + + + + rxdata + Rx FIFO data + 0x4C + + + data + Received data + [7:0] + read-only + + + empty + FIFO empty flag + [31:31] + read-write + + + + + txmark + Tx FIFO watermark + 0x50 + + + txmark + Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise. + [2:0] + read-write + + + + + rxmark + Rx FIFO watermark + 0x54 + + + rxmark + Receive watermark + [2:0] + read-write + + + + + fctrl + SPI flash interface control + 0x60 + + + en + SPI Flash Mode Select + [0:0] + read-write + + + + + ffmt + SPI flash instruction format + 0x64 + + + cmd_en + Enable sending of command + [0:0] + read-write + + + addr_len + Number of address bytes (0 to 4) + [3:1] + read-write + + + pad_cnt + Number of dummy cycles + [7:4] + read-write + + + cmd_proto + Protocol for transmitting command + [9:8] + read-write + + + addr_proto + Protocol for transmitting address and padding + [11:10] + read-write + + + data_proto + Protocol for receiving data bytes + [13:12] + read-write + + + cmd_code + Value of command byte + [23:16] + read-write + + + pad_code + First 8 bits to transmit during dummy cycles + [31:24] + read-write + + + + + ie + SPI interrupt enable + 0x70 + + + txwm + Transmit watermark enable + [0:0] + read-write + + + rxwm + Receive watermark enable + [1:1] + read-write + + + + + ip + SPI interrupt pending + 0x74 + + + txwm + Transmit watermark pending + [0:0] + read-only + + + rxwm + Receive watermark pending + [1:1] + read-only + + + + + + + sifive_pwm0_0 + From sifive,pwm0,control peripheral generator + 0x10015000 + + 0 + 0x1000 + registers + + + + pwmcfg + PWM configuration register + 0x0 + + + pwmscale + PWM Counter scale + [3:0] + read-write + + + pwmsticky + PWM Sticky - disallow clearing pwmcmpXip bits + [8:8] + read-write + + + pwmzerocmp + PWM Zero - counter resets to zero after match + [9:9] + read-write + + + pwmdeglitch + PWM Deglitch - latch pwmcmpXip within same cycle + [10:10] + read-write + + + pwmenalways + PWM enable always - run continuously + [12:12] + read-write + + + pwmenoneshot + PWM enable one shot - run one cycle + [13:13] + read-write + + + pwmcmp0center + PWM0 Compare Center + [16:16] + read-write + + + pwmcmp1center + PWM1 Compare Center + [17:17] + read-write + + + pwmcmp2center + PWM2 Compare Center + [18:18] + read-write + + + pwmcmp3center + PWM3 Compare Center + [19:19] + read-write + + + pwmcmp0invert + PWM0 Invert + [20:20] + read-write + + + pwmcmp1invert + PWM1 Invert + [21:21] + read-write + + + pwmcmp2invert + PWM2 Invert + [22:22] + read-write + + + pwmcmp3invert + PWM3 Invert + [23:23] + read-write + + + pwmcmp0gang + PWM0/PWM1 Compare Gang + [24:24] + read-write + + + pwmcmp1gang + PWM1/PWM2 Compare Gang + [25:25] + read-write + + + pwmcmp2gang + PWM2/PWM3 Compare Gang + [26:26] + read-write + + + pwmcmp3gang + PWM3/PWM0 Compare Gang + [27:27] + read-write + + + pwmcmp0ip + PWM0 Interrupt Pending + [28:28] + read-write + + + pwmcmp1ip + PWM1 Interrupt Pending + [29:29] + read-write + + + pwmcmp2ip + PWM2 Interrupt Pending + [30:30] + read-write + + + pwmcmp3ip + PWM3 Interrupt Pending + [31:31] + read-write + + + + + pwmcount + PWM count register + 0x8 + + + pwmcount + PWM count register. + [30:0] + read-write + + + + + pwms + Scaled PWM count register + 0x10 + + + pwms + Scaled PWM count register. + [15:0] + read-write + + + + + pwmcmp0 + PWM 0 compare register + 0x20 + + + pwmcmp0 + PWM 0 Compare Value + [15:0] + read-write + + + + + pwmcmp1 + PWM 1 compare register + 0x24 + + + pwmcmp1 + PWM 1 Compare Value + [15:0] + read-write + + + + + pwmcmp2 + PWM 2 compare register + 0x28 + + + pwmcmp2 + PWM 2 Compare Value + [15:0] + read-write + + + + + pwmcmp3 + PWM 3 compare register + 0x2C + + + pwmcmp3 + PWM 3 Compare Value + [15:0] + read-write + + + + + + + sifive_i2c0_0 + From sifive,i2c0,control peripheral generator + 0x10016000 + + 0 + 0x1000 + registers + + + + prescale_low + Clock Prescale register lo-byte + 0x0 + + + prescale_high + Clock Prescale register hi-byte + 0x4 + + + control + Control register + 0x8 + + + en + I2C core enable bit + [6:6] + read-write + + + ien + I2C core interrupt enable bit + [7:7] + read-write + + + + + transmit__receive + Transmit and receive data byte register + 0xC + + + command__status + Command write and status read register + 0x10 + + + wr_iack__rd_if + Clear interrupt and Interrupt pending + [0:0] + read-write + + + wr_res__rd_tip + Reserved and Transfer in progress + [1:1] + read-write + + + wr_res__rd_res + Reserved and Reserved + [2:2] + read-write + + + wr_ack__rd_res + Send ACK/NACK and Reserved + [3:3] + read-write + + + wr_txd__rd_res + Transmit data and Reserved + [4:4] + read-write + + + wr_rxd__rd_al + Receive data and Arbitration lost + [5:5] + read-write + + + wr_sto__rd_busy + Generate stop and I2C bus busy + [6:6] + read-write + + + wr_sta__rd_rxack + Generate start and Got ACK/NACK + [7:7] + read-write + + + + + + + sifive_uart0_1 + From sifive,uart0,control peripheral generator + 0x10023000 + + 0 + 0x1000 + registers + + + + txdata + Transmit data register + 0x0 + + + data + Transmit data + [7:0] + read-write + + + full + Transmit FIFO full + [31:31] + read-only + + + + + rxdata + Receive data register + 0x4 + + + data + Received data + [7:0] + read-only + + + empty + Receive FIFO empty + [31:31] + read-only + + + + + txctrl + Transmit control register + 0x8 + + + txen + Transmit enable + [0:0] + read-write + + + nstop + Number of stop bits + [1:1] + read-write + + + txcnt + Transmit watermark level + [18:16] + read-write + + + + + rxctrl + Receive control register + 0xC + + + rxen + Receive enable + [0:0] + read-write + + + rxcnt + Receive watermark level + [18:16] + read-write + + + + + ie + UART interrupt enable + 0x10 + + + txwm + Transmit watermark interrupt enable + [0:0] + read-write + + + rxwm + Receive watermark interrupt enable + [1:1] + read-write + + + + + ip + UART interrupt pending + 0x14 + + + txwm + Transmit watermark interrupt pending + [0:0] + read-only + + + rxwm + Receive watermark interrupt pending + [1:1] + read-only + + + + + div + Baud rate divisor + 0x18 + + + div + Baud rate divisor. + [15:0] + read-write + + + + + + + sifive_spi0_1 + From sifive,spi0,control peripheral generator + 0x10024000 + + 0 + 0x1000 + registers + + + + sckdiv + Serial clock divisor + 0x0 + + + div + Divisor for serial clock. + [11:0] + read-write + + + + + sckmode + Serial clock mode + 0x4 + + + pha + Serial clock phase + [0:0] + read-write + + + pol + Serial clock polarity + [1:1] + read-write + + + + + csid + Chip select ID + 0x10 + + + csid + Chip select ID. + [31:0] + read-write + + + + + csdef + Chip select default + 0x14 + + + csdef + Chip select default value. Reset to all-1s. + [31:0] + read-write + + + + + csmode + Chip select mode + 0x18 + + + mode + Chip select mode + [1:0] + read-write + + + + + delay0 + Delay control 0 + 0x28 + + + cssck + CS to SCK Delay + [7:0] + read-write + + + sckcs + SCK to CS Delay + [23:16] + read-write + + + + + delay1 + Delay control 1 + 0x2C + + + intercs + Minimum CS inactive time + [7:0] + read-write + + + interxfr + Maximum interframe delay + [23:16] + read-write + + + + + extradel + SPI extra sampling delay to increase the SPI frequency + 0x38 + + + coarse + Coarse grain sample delay (multiples of system clocks) + [11:0] + read-write + + + fine + Fine grain sample delay (multiples of process-specific buffer delay) + [16:12] + read-write + + + + + sampledel + Number of delay stages from slave to the SPI controller + 0x3C + + + sd + Number of delay stages from slave to SPI controller + [4:0] + read-write + + + + + fmt + Frame format + 0x40 + + + proto + SPI protocol + [1:0] + read-write + + + endian + SPI endianness + [2:2] + read-write + + + dir + SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise. + [3:3] + read-write + + + len + Number of bits per frame + [19:16] + read-write + + + + + txdata + Tx FIFO Data + 0x48 + + + data + Transmit data + [7:0] + read-write + + + full + FIFO full flag + [31:31] + read-only + + + + + rxdata + Rx FIFO data + 0x4C + + + data + Received data + [7:0] + read-only + + + empty + FIFO empty flag + [31:31] + read-write + + + + + txmark + Tx FIFO watermark + 0x50 + + + txmark + Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise. + [2:0] + read-write + + + + + rxmark + Rx FIFO watermark + 0x54 + + + rxmark + Receive watermark + [2:0] + read-write + + + + + fctrl + SPI flash interface control + 0x60 + + + en + SPI Flash Mode Select + [0:0] + read-write + + + + + ffmt + SPI flash instruction format + 0x64 + + + cmd_en + Enable sending of command + [0:0] + read-write + + + addr_len + Number of address bytes (0 to 4) + [3:1] + read-write + + + pad_cnt + Number of dummy cycles + [7:4] + read-write + + + cmd_proto + Protocol for transmitting command + [9:8] + read-write + + + addr_proto + Protocol for transmitting address and padding + [11:10] + read-write + + + data_proto + Protocol for receiving data bytes + [13:12] + read-write + + + cmd_code + Value of command byte + [23:16] + read-write + + + pad_code + First 8 bits to transmit during dummy cycles + [31:24] + read-write + + + + + ie + SPI interrupt enable + 0x70 + + + txwm + Transmit watermark enable + [0:0] + read-write + + + rxwm + Receive watermark enable + [1:1] + read-write + + + + + ip + SPI interrupt pending + 0x74 + + + txwm + Transmit watermark pending + [0:0] + read-only + + + rxwm + Receive watermark pending + [1:1] + read-only + + + + + + + sifive_pwm0_1 + From sifive,pwm0,control peripheral generator + 0x10025000 + + 0 + 0x1000 + registers + + + + pwmcfg + PWM configuration register + 0x0 + + + pwmscale + PWM Counter scale + [3:0] + read-write + + + pwmsticky + PWM Sticky - disallow clearing pwmcmpXip bits + [8:8] + read-write + + + pwmzerocmp + PWM Zero - counter resets to zero after match + [9:9] + read-write + + + pwmdeglitch + PWM Deglitch - latch pwmcmpXip within same cycle + [10:10] + read-write + + + pwmenalways + PWM enable always - run continuously + [12:12] + read-write + + + pwmenoneshot + PWM enable one shot - run one cycle + [13:13] + read-write + + + pwmcmp0center + PWM0 Compare Center + [16:16] + read-write + + + pwmcmp1center + PWM1 Compare Center + [17:17] + read-write + + + pwmcmp2center + PWM2 Compare Center + [18:18] + read-write + + + pwmcmp3center + PWM3 Compare Center + [19:19] + read-write + + + pwmcmp0invert + PWM0 Invert + [20:20] + read-write + + + pwmcmp1invert + PWM1 Invert + [21:21] + read-write + + + pwmcmp2invert + PWM2 Invert + [22:22] + read-write + + + pwmcmp3invert + PWM3 Invert + [23:23] + read-write + + + pwmcmp0gang + PWM0/PWM1 Compare Gang + [24:24] + read-write + + + pwmcmp1gang + PWM1/PWM2 Compare Gang + [25:25] + read-write + + + pwmcmp2gang + PWM2/PWM3 Compare Gang + [26:26] + read-write + + + pwmcmp3gang + PWM3/PWM0 Compare Gang + [27:27] + read-write + + + pwmcmp0ip + PWM0 Interrupt Pending + [28:28] + read-write + + + pwmcmp1ip + PWM1 Interrupt Pending + [29:29] + read-write + + + pwmcmp2ip + PWM2 Interrupt Pending + [30:30] + read-write + + + pwmcmp3ip + PWM3 Interrupt Pending + [31:31] + read-write + + + + + pwmcount + PWM count register + 0x8 + + + pwmcount + PWM count register. + [30:0] + read-write + + + + + pwms + Scaled PWM count register + 0x10 + + + pwms + Scaled PWM count register. + [15:0] + read-write + + + + + pwmcmp0 + PWM 0 compare register + 0x20 + + + pwmcmp0 + PWM 0 Compare Value + [15:0] + read-write + + + + + pwmcmp1 + PWM 1 compare register + 0x24 + + + pwmcmp1 + PWM 1 Compare Value + [15:0] + read-write + + + + + pwmcmp2 + PWM 2 compare register + 0x28 + + + pwmcmp2 + PWM 2 Compare Value + [15:0] + read-write + + + + + pwmcmp3 + PWM 3 compare register + 0x2C + + + pwmcmp3 + PWM 3 Compare Value + [15:0] + read-write + + + + + + + sifive_spi0_2 + From sifive,spi0,control peripheral generator + 0x10034000 + + 0 + 0x1000 + registers + + + + sckdiv + Serial clock divisor + 0x0 + + + div + Divisor for serial clock. + [11:0] + read-write + + + + + sckmode + Serial clock mode + 0x4 + + + pha + Serial clock phase + [0:0] + read-write + + + pol + Serial clock polarity + [1:1] + read-write + + + + + csid + Chip select ID + 0x10 + + + csid + Chip select ID. + [31:0] + read-write + + + + + csdef + Chip select default + 0x14 + + + csdef + Chip select default value. Reset to all-1s. + [31:0] + read-write + + + + + csmode + Chip select mode + 0x18 + + + mode + Chip select mode + [1:0] + read-write + + + + + delay0 + Delay control 0 + 0x28 + + + cssck + CS to SCK Delay + [7:0] + read-write + + + sckcs + SCK to CS Delay + [23:16] + read-write + + + + + delay1 + Delay control 1 + 0x2C + + + intercs + Minimum CS inactive time + [7:0] + read-write + + + interxfr + Maximum interframe delay + [23:16] + read-write + + + + + extradel + SPI extra sampling delay to increase the SPI frequency + 0x38 + + + coarse + Coarse grain sample delay (multiples of system clocks) + [11:0] + read-write + + + fine + Fine grain sample delay (multiples of process-specific buffer delay) + [16:12] + read-write + + + + + sampledel + Number of delay stages from slave to the SPI controller + 0x3C + + + sd + Number of delay stages from slave to SPI controller + [4:0] + read-write + + + + + fmt + Frame format + 0x40 + + + proto + SPI protocol + [1:0] + read-write + + + endian + SPI endianness + [2:2] + read-write + + + dir + SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise. + [3:3] + read-write + + + len + Number of bits per frame + [19:16] + read-write + + + + + txdata + Tx FIFO Data + 0x48 + + + data + Transmit data + [7:0] + read-write + + + full + FIFO full flag + [31:31] + read-only + + + + + rxdata + Rx FIFO data + 0x4C + + + data + Received data + [7:0] + read-only + + + empty + FIFO empty flag + [31:31] + read-write + + + + + txmark + Tx FIFO watermark + 0x50 + + + txmark + Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise. + [2:0] + read-write + + + + + rxmark + Rx FIFO watermark + 0x54 + + + rxmark + Receive watermark + [2:0] + read-write + + + + + fctrl + SPI flash interface control + 0x60 + + + en + SPI Flash Mode Select + [0:0] + read-write + + + + + ffmt + SPI flash instruction format + 0x64 + + + cmd_en + Enable sending of command + [0:0] + read-write + + + addr_len + Number of address bytes (0 to 4) + [3:1] + read-write + + + pad_cnt + Number of dummy cycles + [7:4] + read-write + + + cmd_proto + Protocol for transmitting command + [9:8] + read-write + + + addr_proto + Protocol for transmitting address and padding + [11:10] + read-write + + + data_proto + Protocol for receiving data bytes + [13:12] + read-write + + + cmd_code + Value of command byte + [23:16] + read-write + + + pad_code + First 8 bits to transmit during dummy cycles + [31:24] + read-write + + + + + ie + SPI interrupt enable + 0x70 + + + txwm + Transmit watermark enable + [0:0] + read-write + + + rxwm + Receive watermark enable + [1:1] + read-write + + + + + ip + SPI interrupt pending + 0x74 + + + txwm + Transmit watermark pending + [0:0] + read-only + + + rxwm + Receive watermark pending + [1:1] + read-only + + + + + + + sifive_pwm0_2 + From sifive,pwm0,control peripheral generator + 0x10035000 + + 0 + 0x1000 + registers + + + + pwmcfg + PWM configuration register + 0x0 + + + pwmscale + PWM Counter scale + [3:0] + read-write + + + pwmsticky + PWM Sticky - disallow clearing pwmcmpXip bits + [8:8] + read-write + + + pwmzerocmp + PWM Zero - counter resets to zero after match + [9:9] + read-write + + + pwmdeglitch + PWM Deglitch - latch pwmcmpXip within same cycle + [10:10] + read-write + + + pwmenalways + PWM enable always - run continuously + [12:12] + read-write + + + pwmenoneshot + PWM enable one shot - run one cycle + [13:13] + read-write + + + pwmcmp0center + PWM0 Compare Center + [16:16] + read-write + + + pwmcmp1center + PWM1 Compare Center + [17:17] + read-write + + + pwmcmp2center + PWM2 Compare Center + [18:18] + read-write + + + pwmcmp3center + PWM3 Compare Center + [19:19] + read-write + + + pwmcmp0invert + PWM0 Invert + [20:20] + read-write + + + pwmcmp1invert + PWM1 Invert + [21:21] + read-write + + + pwmcmp2invert + PWM2 Invert + [22:22] + read-write + + + pwmcmp3invert + PWM3 Invert + [23:23] + read-write + + + pwmcmp0gang + PWM0/PWM1 Compare Gang + [24:24] + read-write + + + pwmcmp1gang + PWM1/PWM2 Compare Gang + [25:25] + read-write + + + pwmcmp2gang + PWM2/PWM3 Compare Gang + [26:26] + read-write + + + pwmcmp3gang + PWM3/PWM0 Compare Gang + [27:27] + read-write + + + pwmcmp0ip + PWM0 Interrupt Pending + [28:28] + read-write + + + pwmcmp1ip + PWM1 Interrupt Pending + [29:29] + read-write + + + pwmcmp2ip + PWM2 Interrupt Pending + [30:30] + read-write + + + pwmcmp3ip + PWM3 Interrupt Pending + [31:31] + read-write + + + + + pwmcount + PWM count register + 0x8 + + + pwmcount + PWM count register. + [30:0] + read-write + + + + + pwms + Scaled PWM count register + 0x10 + + + pwms + Scaled PWM count register. + [15:0] + read-write + + + + + pwmcmp0 + PWM 0 compare register + 0x20 + + + pwmcmp0 + PWM 0 Compare Value + [15:0] + read-write + + + + + pwmcmp1 + PWM 1 compare register + 0x24 + + + pwmcmp1 + PWM 1 Compare Value + [15:0] + read-write + + + + + pwmcmp2 + PWM 2 compare register + 0x28 + + + pwmcmp2 + PWM 2 Compare Value + [15:0] + read-write + + + + + pwmcmp3 + PWM 3 compare register + 0x2C + + + pwmcmp3 + PWM 3 Compare Value + [15:0] + read-write + + + + + + + \ No newline at end of file From dae40eac6ba9c6c87d34d648e711a5f1b7250120 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 14 Dec 2022 14:36:53 +0100 Subject: [PATCH 05/21] Cargo.toml: Declare example --- .gitignore | 4 +++- .vscode/launch.json | 2 +- .vscode/tasks.json | 6 +++--- Cargo.toml | 4 ++++ 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index becb52e..8b486ab 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,6 @@ Cargo.lock target/ core -.gdb_history \ No newline at end of file +.gdb_history +.vscode/.cortex-debug.peripherals.state.json +.vscode/.cortex-debug.registers.state.json diff --git a/.vscode/launch.json b/.vscode/launch.json index a62dca9..3910efc 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -6,7 +6,7 @@ // Substitute with the board number "device": "FE310", "type": "cortex-debug", - "preLaunchTask": "build-hifive", + "preLaunchTask": "example-virq", // Defined in tasks.json "request": "launch", "servertype": "jlink", diff --git a/.vscode/tasks.json b/.vscode/tasks.json index 6d2affc..aee0a12 100644 --- a/.vscode/tasks.json +++ b/.vscode/tasks.json @@ -2,12 +2,12 @@ "version": "2.0.0", "tasks": [ { - "label": "build-hifive", + "label": "example-virq", "command": "cargo", "args": [ "build", - "--features=board-redv,virq", - "--example=virq" + "--features=board-redv,virq", + "--example=virq" ], "problemMatcher": [ "$rustc" diff --git a/Cargo.toml b/Cargo.toml index 8261881..bed1471 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -25,5 +25,9 @@ board-lofive = [] board-lofive-r1 = ["e310x-hal/g002"] virq = ["e310x-hal/virq"] +[[example]] +name = "virq" +required-features = ["virq"] + [package.metadata.docs.rs] features = ['board-hifive1-revb'] From 0de0d4539253bd0e5d062530f6928e5ed17f242b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 14 Dec 2022 15:04:53 +0100 Subject: [PATCH 06/21] Cleanup unused dependencies --- .vscode/launch.json | 2 +- examples/virq.rs | 13 ++----------- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index 3910efc..1b59742 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -16,7 +16,7 @@ "executable": "${workspaceRoot}/target/riscv32imac-unknown-none-elf/debug/examples/virq", "interface": "jtag", "svdFile": "${workspaceRoot}/hifive.svd", - // Set this to point to risc-v gdb path + // Set this to point to risc-v gdb path (this sample uses expressif's toolchain ) "gdbPath": "${workspaceRoot}/../../Toolchains/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-amd64/riscv32-esp-elf/bin/riscv32-esp-elf-gdb", // Set this to point to Espressif's GDB version // "gdbPath": "${workspaceRoot}/riscv32-esp-elf-gdb", "toolchainPrefix": "riscv32-esp-elf", diff --git a/examples/virq.rs b/examples/virq.rs index ca6738a..2de8b82 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -16,20 +16,11 @@ extern crate panic_halt; use hifive1::{ hal::core::plic::Priority, - hal::core::CorePeripherals, hal::DeviceResources, - hal::{ - core::plic::{self, INTERRUPT}, - e310x::{ - interrupt::Interrupt, - plic::{priority, PRIORITY}, - GPIO0, PLIC, - }, - gpio::gpio0, - prelude::*, - }, + hal::prelude::*, pin, sprintln, }; + use riscv::register::mstatus; use riscv_rt::entry; From b839fd6e4cd22a56563472bc3e773e119f51b16d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 14 Dec 2022 15:08:13 +0100 Subject: [PATCH 07/21] virq.rs: Code formatting --- examples/virq.rs | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/examples/virq.rs b/examples/virq.rs index 2de8b82..b5560dc 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -14,12 +14,7 @@ This can be applied for all the 52 interrupts declared in e310x/interrupts.rs. extern crate panic_halt; -use hifive1::{ - hal::core::plic::Priority, - hal::DeviceResources, - hal::prelude::*, - pin, sprintln, -}; +use hifive1::{hal::core::plic::Priority, hal::prelude::*, hal::DeviceResources, pin, sprintln}; use riscv::register::mstatus; use riscv_rt::entry; From ce176c365ba67b5a0dc30d0d9e4b45c44429b72f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= Date: Wed, 14 Dec 2022 17:03:12 +0100 Subject: [PATCH 08/21] Minor changes in toolchain paths --- .cargo/config | 4 ++-- .vscode/launch.json | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.cargo/config b/.cargo/config index a6dfeb9..f633610 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,8 +1,8 @@ [target.riscv32imac-unknown-none-elf] -runner = "../../Toolchains/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gdb -q -x gdb_init" +runner = "../../../toolchains/sifive/bin/riscv64-unknown-elf-gdb -q -x gdb_init" rustflags = [ "-C", "link-arg=-Thifive1-link.x", ] [build] -target = "riscv32imac-unknown-none-elf" \ No newline at end of file +target = "riscv32imac-unknown-none-elf" diff --git a/.vscode/launch.json b/.vscode/launch.json index 1b59742..711b69a 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -17,9 +17,9 @@ "interface": "jtag", "svdFile": "${workspaceRoot}/hifive.svd", // Set this to point to risc-v gdb path (this sample uses expressif's toolchain ) - "gdbPath": "${workspaceRoot}/../../Toolchains/riscv32-esp-elf-gcc11_2_0-esp-2022r1-linux-amd64/riscv32-esp-elf/bin/riscv32-esp-elf-gdb", // Set this to point to Espressif's GDB version + "gdbPath": "${workspaceRoot}/../../../toolchains/sifive/bin/riscv64-unknown-elf-gdb", // Set this to point to Espressif's GDB version // "gdbPath": "${workspaceRoot}/riscv32-esp-elf-gdb", - "toolchainPrefix": "riscv32-esp-elf", + "toolchainPrefix": "riscv64-unknown-elf", }, ] } \ No newline at end of file From c8cc9466cb9bfbb91d81e80848c6a983676568eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 14 Dec 2022 17:05:19 +0100 Subject: [PATCH 09/21] Minor comment changes --- .vscode/launch.json | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index 711b69a..c4fd976 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -16,9 +16,8 @@ "executable": "${workspaceRoot}/target/riscv32imac-unknown-none-elf/debug/examples/virq", "interface": "jtag", "svdFile": "${workspaceRoot}/hifive.svd", - // Set this to point to risc-v gdb path (this sample uses expressif's toolchain ) - "gdbPath": "${workspaceRoot}/../../../toolchains/sifive/bin/riscv64-unknown-elf-gdb", // Set this to point to Espressif's GDB version - // "gdbPath": "${workspaceRoot}/riscv32-esp-elf-gdb", + // Set this to point to sifive risc-v gdb path + "gdbPath": "${workspaceRoot}/../../../toolchains/sifive/bin/riscv64-unknown-elf-gdb", "toolchainPrefix": "riscv64-unknown-elf", }, ] From 04031d6d0182ab1a2868795cda5f264b87279b93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 14 Dec 2022 17:06:57 +0100 Subject: [PATCH 10/21] launch.json: Add jlink path --- .vscode/launch.json | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.vscode/launch.json b/.vscode/launch.json index c4fd976..3edb867 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -10,6 +10,9 @@ // Defined in tasks.json "request": "launch", "servertype": "jlink", + // JLink server path + // "serverpath": "", + // GDB debug output // "showDevDebugOutput": "raw", "cwd": "${workspaceRoot}", // Executable to launch From c84bed2d37c6202aa1364254ee38f554acd7d927 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=C3=A9rez?= Date: Wed, 14 Dec 2022 17:41:27 +0100 Subject: [PATCH 11/21] Change constant to bitshift --- .cargo/config | 2 +- .vscode/launch.json | 2 +- examples/virq.rs | 13 ++++++++----- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/.cargo/config b/.cargo/config index f633610..019b199 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,5 +1,5 @@ [target.riscv32imac-unknown-none-elf] -runner = "../../../toolchains/sifive/bin/riscv64-unknown-elf-gdb -q -x gdb_init" +runner = "../../Toolchains/sifive/bin/riscv64-unknown-elf-gdb -q -x gdb_init" rustflags = [ "-C", "link-arg=-Thifive1-link.x", ] diff --git a/.vscode/launch.json b/.vscode/launch.json index 3edb867..70caa57 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -20,7 +20,7 @@ "interface": "jtag", "svdFile": "${workspaceRoot}/hifive.svd", // Set this to point to sifive risc-v gdb path - "gdbPath": "${workspaceRoot}/../../../toolchains/sifive/bin/riscv64-unknown-elf-gdb", + "gdbPath": "${workspaceRoot}/../../Toolchains/sifive/bin/riscv64-unknown-elf-gdb", "toolchainPrefix": "riscv64-unknown-elf", }, ] diff --git a/examples/virq.rs b/examples/virq.rs index b5560dc..242c131 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -19,6 +19,9 @@ use hifive1::{hal::core::plic::Priority, hal::prelude::*, hal::DeviceResources, use riscv::register::mstatus; use riscv_rt::entry; +/* we have chosen the GPIO4 (a.k.a dig12) for this example */ +const GPIO_N : usize = 4; + /* Handler for the GPIO0 interrupt */ #[no_mangle] #[allow(non_snake_case)] @@ -27,7 +30,7 @@ fn GPIO4() { /* Clear the GPIO pending interrupt */ unsafe { let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); - gpio_block.fall_ip.write(|w| w.bits(0xffffffff)); + gpio_block.fall_ip.write(|w| w.bits(1< ! { unsafe { /* Get raw PLIC pointer */ let rplic = &*hifive1::hal::e310x::PLIC::ptr(); - let gpio0_block_start = 7; /* Index 7 is the GPIO0 interrupt source start */ + let gpio0_block_start = 7; for (i, p) in rplic.priority.iter().enumerate() { /* set priority of our interrupt */ - if i == gpio0_block_start + 5 { + if i == gpio0_block_start + (GPIO_N + 1) { p.write(|w| w.bits(0xffffffff)); } else { /* Clear all other priorities */ @@ -76,11 +79,11 @@ fn main() -> ! { } let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); /* Enable GPIO fall interrupts */ - gpio_block.fall_ie.write(|w| w.bits(0xffffffff)); + gpio_block.fall_ie.write(|w| w.bits(1< Date: Wed, 14 Dec 2022 17:47:15 +0100 Subject: [PATCH 12/21] Code format --- examples/virq.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/virq.rs b/examples/virq.rs index 242c131..3547ddc 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -20,7 +20,7 @@ use riscv::register::mstatus; use riscv_rt::entry; /* we have chosen the GPIO4 (a.k.a dig12) for this example */ -const GPIO_N : usize = 4; +const GPIO_N: usize = 4; /* Handler for the GPIO0 interrupt */ #[no_mangle] @@ -30,7 +30,7 @@ fn GPIO4() { /* Clear the GPIO pending interrupt */ unsafe { let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); - gpio_block.fall_ip.write(|w| w.bits(1< ! { } let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); /* Enable GPIO fall interrupts */ - gpio_block.fall_ie.write(|w| w.bits(1< Date: Mon, 20 Feb 2023 22:48:08 +0100 Subject: [PATCH 13/21] update include filename in linker script to match e310x-hal --- hifive1-link.x | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hifive1-link.x b/hifive1-link.x index daeba82..e611438 100644 --- a/hifive1-link.x +++ b/hifive1-link.x @@ -1,3 +1,3 @@ INCLUDE hifive1-memory.x INCLUDE link.x -INCLUDE interrupts.x \ No newline at end of file +INCLUDE fe310x-interrupt.x From 1c63f6e67671ff0014b2c9d41d935a2223a34878 Mon Sep 17 00:00:00 2001 From: Daniel Perez Date: Thu, 22 Jun 2023 21:17:04 +0200 Subject: [PATCH 14/21] Fixed example to work with new PLIC structure and linker changes. --- .cargo/config | 2 +- Cargo.toml | 7 ++++--- examples/virq.rs | 23 ++++++++--------------- hifive1-link.x | 1 - memory-hifive1-revb.x | 2 +- memory-hifive1.x | 2 +- memory-lofive-r1.x | 2 +- 7 files changed, 16 insertions(+), 23 deletions(-) diff --git a/.cargo/config b/.cargo/config index 019b199..aa75f41 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,5 +1,5 @@ [target.riscv32imac-unknown-none-elf] -runner = "../../Toolchains/sifive/bin/riscv64-unknown-elf-gdb -q -x gdb_init" +runner = "/home/steew/things/dev/bin/riscv-sifive/bin/riscv64-unknown-elf-gdb -q -x gdb_init" rustflags = [ "-C", "link-arg=-Thifive1-link.x", ] diff --git a/Cargo.toml b/Cargo.toml index bed1471..04ea320 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,9 +11,10 @@ edition = "2018" [dependencies] e310x-hal = {git = "https://github.com/greenlsi/e310x-hal"} +e310x = {git = "https://github.com/greenlsi/e310x", features = ["v-extern"]} embedded-hal = "0.2.5" riscv = "0.6.0" -riscv-rt = "0.10.0" +riscv-rt = "0.11.0" nb = "1.0.0" panic-halt = "0.2.0" @@ -23,11 +24,11 @@ board-hifive1-revb = ["e310x-hal/g002"] board-redv = ["e310x-hal/g002"] board-lofive = [] board-lofive-r1 = ["e310x-hal/g002"] -virq = ["e310x-hal/virq"] +v-extern = ["e310x/v-extern"] [[example]] name = "virq" -required-features = ["virq"] +required-features = ["v-extern"] [package.metadata.docs.rs] features = ['board-hifive1-revb'] diff --git a/examples/virq.rs b/examples/virq.rs index 3547ddc..48dbed1 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -14,7 +14,7 @@ This can be applied for all the 52 interrupts declared in e310x/interrupts.rs. extern crate panic_halt; -use hifive1::{hal::core::plic::Priority, hal::prelude::*, hal::DeviceResources, pin, sprintln}; +use hifive1::{ hal::prelude::*, hal::DeviceResources, pin, sprintln}; use riscv::register::mstatus; use riscv_rt::entry; @@ -65,18 +65,11 @@ fn main() -> ! { /* Unsafe block */ unsafe { /* Get raw PLIC pointer */ - let rplic = &*hifive1::hal::e310x::PLIC::ptr(); - /* Index 7 is the GPIO0 interrupt source start */ - let gpio0_block_start = 7; - for (i, p) in rplic.priority.iter().enumerate() { - /* set priority of our interrupt */ - if i == gpio0_block_start + (GPIO_N + 1) { - p.write(|w| w.bits(0xffffffff)); - } else { - /* Clear all other priorities */ - p.write(|w| w.bits(0)); - } - } + //let rplic = &*hifive1::hal::e310x::PLIC::ptr(); + hifive1::hal::e310x::PLIC::set_priority( + &mut plic, + hifive1::hal::e310x::Interrupt::GPIO4, + e310x_hal::e310x::Priority::P7); let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); /* Enable GPIO fall interrupts */ gpio_block.fall_ie.write(|w| w.bits(1 << GPIO_N)); @@ -87,8 +80,8 @@ fn main() -> ! { /* Activate global interrupts (mie bit) */ mstatus::set_mie(); - plic.threshold.set(Priority::P1); - plic.mext.enable(); + plic.set_threshold(e310x_hal::e310x::Priority::P1); + plic.enable_interrupt(hifive1::hal::e310x::Interrupt::GPIO4); } loop {} } diff --git a/hifive1-link.x b/hifive1-link.x index e611438..c472d9b 100644 --- a/hifive1-link.x +++ b/hifive1-link.x @@ -1,3 +1,2 @@ INCLUDE hifive1-memory.x INCLUDE link.x -INCLUDE fe310x-interrupt.x diff --git a/memory-hifive1-revb.x b/memory-hifive1-revb.x index e9e4bc5..4239af3 100644 --- a/memory-hifive1-revb.x +++ b/memory-hifive1-revb.x @@ -1,4 +1,4 @@ -INCLUDE memory-fe310.x +INCLUDE device.x MEMORY { FLASH : ORIGIN = 0x20000000, LENGTH = 4M diff --git a/memory-hifive1.x b/memory-hifive1.x index cd55c70..e5dc86e 100644 --- a/memory-hifive1.x +++ b/memory-hifive1.x @@ -1,4 +1,4 @@ -INCLUDE memory-fe310.x +INCLUDE device.x MEMORY { FLASH : ORIGIN = 0x20000000, LENGTH = 16M diff --git a/memory-lofive-r1.x b/memory-lofive-r1.x index cd55c70..e5dc86e 100644 --- a/memory-lofive-r1.x +++ b/memory-lofive-r1.x @@ -1,4 +1,4 @@ -INCLUDE memory-fe310.x +INCLUDE device.x MEMORY { FLASH : ORIGIN = 0x20000000, LENGTH = 16M From b884fc6ff50ad77e34019ad3f9f0706037f2d818 Mon Sep 17 00:00:00 2001 From: Daniel Perez Date: Fri, 23 Jun 2023 14:11:01 +0200 Subject: [PATCH 15/21] experimental pin mod --- examples/virq.rs | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/examples/virq.rs b/examples/virq.rs index 48dbed1..c834cf9 100644 --- a/examples/virq.rs +++ b/examples/virq.rs @@ -14,7 +14,7 @@ This can be applied for all the 52 interrupts declared in e310x/interrupts.rs. extern crate panic_halt; -use hifive1::{ hal::prelude::*, hal::DeviceResources, pin, sprintln}; +use hifive1::{hal::prelude::*, hal::DeviceResources, pin, sprintln}; use riscv::register::mstatus; use riscv_rt::entry; @@ -56,8 +56,9 @@ fn main() -> ! { ); /* Set GPIO4 (pin 12) as input */ - let gpio4 = pin!(gpio, dig12); - _ = gpio4.into_pull_up_input(); + // let gpio4 = pin!(gpio, dig12); + let input = gpio.pin4.into_pull_up_input(); + //let input = gpio4.into_pull_up_input(); /* Wrapper for easy access */ let mut plic = resources.core_peripherals.plic; @@ -69,7 +70,8 @@ fn main() -> ! { hifive1::hal::e310x::PLIC::set_priority( &mut plic, hifive1::hal::e310x::Interrupt::GPIO4, - e310x_hal::e310x::Priority::P7); + e310x_hal::e310x::Priority::P7, + ); let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); /* Enable GPIO fall interrupts */ gpio_block.fall_ie.write(|w| w.bits(1 << GPIO_N)); From c8585c511f0a90f6c2b77853d0046d52148b918e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Thu, 7 Dec 2023 16:10:52 +0100 Subject: [PATCH 16/21] Update Cargo.toml --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index 04ea320..a9e2969 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,7 +11,7 @@ edition = "2018" [dependencies] e310x-hal = {git = "https://github.com/greenlsi/e310x-hal"} -e310x = {git = "https://github.com/greenlsi/e310x", features = ["v-extern"]} +e310x = {git = "https://github.com/greenlsi/e310x"} embedded-hal = "0.2.5" riscv = "0.6.0" riscv-rt = "0.11.0" From ea7fb3b3690560aa58a60f1bf43165005db1fe6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Thu, 7 Dec 2023 16:21:53 +0100 Subject: [PATCH 17/21] Update Cargo.toml --- Cargo.toml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index a9e2969..5658361 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,7 +11,6 @@ edition = "2018" [dependencies] e310x-hal = {git = "https://github.com/greenlsi/e310x-hal"} -e310x = {git = "https://github.com/greenlsi/e310x"} embedded-hal = "0.2.5" riscv = "0.6.0" riscv-rt = "0.11.0" @@ -24,7 +23,6 @@ board-hifive1-revb = ["e310x-hal/g002"] board-redv = ["e310x-hal/g002"] board-lofive = [] board-lofive-r1 = ["e310x-hal/g002"] -v-extern = ["e310x/v-extern"] [[example]] name = "virq" From 615c802148eeda73952747f4e288d2b4e36d0da1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Thu, 7 Dec 2023 16:23:58 +0100 Subject: [PATCH 18/21] Update Cargo.toml --- Cargo.toml | 1 + 1 file changed, 1 insertion(+) diff --git a/Cargo.toml b/Cargo.toml index 5658361..8781071 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -23,6 +23,7 @@ board-hifive1-revb = ["e310x-hal/g002"] board-redv = ["e310x-hal/g002"] board-lofive = [] board-lofive-r1 = ["e310x-hal/g002"] +v-extern = ["e310x-hal/v-extern"] [[example]] name = "virq" From 459486ab5cedea0d7bd0e0232214a0773ca35bf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Wed, 4 Sep 2024 15:43:21 +0200 Subject: [PATCH 19/21] update to new HAL --- .cargo/config | 8 ---- .cargo/config.toml | 9 +++++ .vscode/settings.json | 6 ++- Cargo.toml | 12 ++---- assemble.sh | 11 ------ bin/flash.a | Bin 2222 -> 0 bytes build.rs | 6 --- examples/gpio4.rs | 78 ++++++++++++++++++++++++++++++++++++ examples/mtimer.rs | 61 +++++++++++++++++++++++++++++ examples/virq.rs | 89 ------------------------------------------ flash.S | 45 --------------------- src/clock.rs | 6 +-- src/flash.rs | 57 +++++++++++++++++++++++++-- src/stdout.rs | 14 +++---- 14 files changed, 220 insertions(+), 182 deletions(-) delete mode 100644 .cargo/config create mode 100644 .cargo/config.toml delete mode 100755 assemble.sh delete mode 100644 bin/flash.a create mode 100644 examples/gpio4.rs create mode 100644 examples/mtimer.rs delete mode 100644 examples/virq.rs delete mode 100644 flash.S diff --git a/.cargo/config b/.cargo/config deleted file mode 100644 index aa75f41..0000000 --- a/.cargo/config +++ /dev/null @@ -1,8 +0,0 @@ -[target.riscv32imac-unknown-none-elf] -runner = "/home/steew/things/dev/bin/riscv-sifive/bin/riscv64-unknown-elf-gdb -q -x gdb_init" -rustflags = [ - "-C", "link-arg=-Thifive1-link.x", -] - -[build] -target = "riscv32imac-unknown-none-elf" diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 0000000..6f096c8 --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,9 @@ +[target.'cfg(all(target_arch = "riscv32", target_os = "none"))'] +runner = "qemu-system-riscv32 -machine sifive_e,revb=true -nographic -kernel" +# runner = "riscv64-unknown-elf-gdb -q -x gdb_init" +rustflags = [ + "-C", "link-arg=-Thifive1-link.x", +] + +[build] +target = "riscv32imac-unknown-none-elf" diff --git a/.vscode/settings.json b/.vscode/settings.json index 4302e07..49346de 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,3 +1,5 @@ { - "cortex-debug.variableUseNaturalFormat": true -} \ No newline at end of file + "cortex-debug.variableUseNaturalFormat": true, + "rust-analyzer.cargo.features": ["board-redv"], + "rust-analyzer.check.allTargets": false, +} diff --git a/Cargo.toml b/Cargo.toml index 8781071..90e11dd 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -7,13 +7,13 @@ categories = ["embedded", "hardware-support", "no-std"] description = "Board support crate for HiFive1 and LoFive boards" keywords = ["riscv", "register", "peripheral"] license = "ISC" -edition = "2018" +edition = "2021" [dependencies] e310x-hal = {git = "https://github.com/greenlsi/e310x-hal"} embedded-hal = "0.2.5" -riscv = "0.6.0" -riscv-rt = "0.11.0" +riscv = { git = "https://github.com/rust-embedded/riscv", branch = "riscv-pac-only", features = ["critical-section-single-hart"]} # TODO use crates.io +riscv-rt = { git = "https://github.com/rust-embedded/riscv", branch = "riscv-pac-only" } # TODO use crates.io nb = "1.0.0" panic-halt = "0.2.0" @@ -23,11 +23,7 @@ board-hifive1-revb = ["e310x-hal/g002"] board-redv = ["e310x-hal/g002"] board-lofive = [] board-lofive-r1 = ["e310x-hal/g002"] -v-extern = ["e310x-hal/v-extern"] - -[[example]] -name = "virq" -required-features = ["v-extern"] +v-trap = ["e310x-hal/v-trap"] [package.metadata.docs.rs] features = ['board-hifive1-revb'] diff --git a/assemble.sh b/assemble.sh deleted file mode 100755 index 3a04536..0000000 --- a/assemble.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -set -euxo pipefail - -# remove existing blobs because otherwise this will append object files to the old blobs -rm -f bin/*.a - -riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/hifive1 -c -mabi=ilp32 -march=rv32imac flash.S -o bin/flash.o -riscv64-unknown-elf-ar crs bin/flash.a bin/flash.o - -rm bin/flash.o diff --git a/bin/flash.a b/bin/flash.a deleted file mode 100644 index 4c734e21c25daa429a7aced6fcbdaeb1545f37ce..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2222 zcma)6&rcIU6n@ifD@7=U5+x#L6-A6@DGS2I5J;>hhUft`Mh~!s0!_+~Y?lU&iNup8 z9zE#IgE2jL@Fs~~JaF{D-=GJNCSFWT)bGuY?Y2PlCG+O{-n{wV%(!+*wA$x#^?q;AU6`@G2Xze*&>k9?qPvU<7iQ!4-Db2dS3wH^45 z+D`x51bxeYxsmv-d^VYkf8R~yYrBuPUPH;E6YxU(O1Hzy@>qhOjxYMEK(qgGv9Hy(+Z`o5bw(E?zoYsc+2PQ~76zws|&2-k8 z8ieypmH8?OKFfq(9dS$UdTw@woyTq-&dfQew;H}Se;KuElW!psHH&b#(ZD`DI&2X> zSTvyX>u1rdhZ}+XmT->Zoe>^F0E_rh)Xkz~Q@u1IL}Ot}T%P4Xgm(d7i0}{sSadi_ z!P}d7x`}6~M@M*%8SIyw>6{Jc#)jdCwRfrU6>~1u!4AfsH={T0Fy=+V&Z7z55R5ya zm&5l(=%uiP&91bPQyGfi^RC8$7D_5qdWfV?90xqqhWX<^a+p2;W^}X6yk12J_e* z5SxKEeeG!jJX$vc!uOWz^0ha0p8~U94vlRSq)$QVd5qgj-OC`{3j}RL(6b)fbF^sP z!AMwCdI%(U`J7)-buF1x|xns<~BCv(Vzk{P_tjF(^pE&eFTL9Vbd+`3F Nd6N*>4rkTt{sl;fv@QSu diff --git a/build.rs b/build.rs index ec4ac5f..c16de98 100644 --- a/build.rs +++ b/build.rs @@ -44,10 +44,4 @@ fn main() { fs::copy("hifive1-link.x", out_dir.join("hifive1-link.x")).unwrap(); println!("cargo:rerun-if-changed=hifive1-link.x"); - - // Copy library with flash setup code - let name = env::var("CARGO_PKG_NAME").unwrap(); - fs::copy("bin/flash.a", out_dir.join(format!("lib{}.a", name))).unwrap(); - println!("cargo:rustc-link-lib=static={}", name); - println!("cargo:rerun-if-changed=bin/flash.a"); } diff --git a/examples/gpio4.rs b/examples/gpio4.rs new file mode 100644 index 0000000..343fc12 --- /dev/null +++ b/examples/gpio4.rs @@ -0,0 +1,78 @@ +//! Demonstration on how to configure the GPIO4 interrupt on HiFive boards. +//! You must connect a button to pin 12 (GPIO4) and ground to test this example. + +#![no_main] +#![no_std] + +extern crate panic_halt; + +use hifive1::hal::e310x::PLIC; +use hifive1::{hal::prelude::*, hal::DeviceResources, pin, sprintln}; + +use riscv::register::mstatus; +use riscv_rt::entry; + +/* Handler for the GPIO0 interrupt */ +#[riscv_rt::external_interrupt(ExternalInterrupt::GPIO4)] +fn gpio4_handler() { + sprintln!("We reached the GPIO4 interrupt!"); + /* Clear the GPIO pending interrupt */ + let gpio_block = unsafe { hifive1::hal::e310x::Gpio0::steal() }; + gpio_block.fall_ip().write(|w| w.pin4().set_bit()); +} + +/* Code adapted from https://github.com/riscv-rust/riscv-rust-quickstart/blob/interrupt-test/examples/interrupt.rs*/ +#[entry] +fn main() -> ! { + /* Get the ownership of the device resources singleton */ + let resources = DeviceResources::take().unwrap(); + let peripherals = resources.peripherals; + + /* Configure system clock */ + let sysclock = hifive1::configure_clocks(peripherals.PRCI, peripherals.AONCLK, 64.mhz().into()); + /* Get the board pins */ + let gpio = resources.pins; + + /* Configure stdout for debugging */ + hifive1::stdout::configure( + peripherals.UART0, + pin!(gpio, uart0_tx), + pin!(gpio, uart0_rx), + 115_200.bps(), + sysclock, + ); + + sprintln!("Configuring GPIO..."); + /* Set GPIO4 (pin 12) as input */ + // let gpio4 = pin!(gpio, dig12); + gpio.pin4.into_pull_up_input(); + //let input = gpio4.into_pull_up_input(); + + sprintln!("Configuring priorities..."); + /* Set interrupt source priority */ + let priorities = PLIC::priorities(); + unsafe { priorities.set_priority(ExternalInterrupt::GPIO4, Priority::P7) }; + + let gpio_block = unsafe { hifive1::hal::e310x::Gpio0::steal() }; + unsafe { + /* Clear pending interrupts from previous states */ + gpio_block.fall_ie().write(|w| w.bits(0x00000000)); + gpio_block.rise_ie().write(|w| w.bits(0x00000000)); + gpio_block.fall_ip().write(|w| w.bits(0xffffffff)); + gpio_block.rise_ip().write(|w| w.bits(0xffffffff)); + } + gpio_block.fall_ie().write(|w| w.pin4().set_bit()); + gpio_block.rise_ie().write(|w| w.pin4().clear_bit()); + + /* Activate global interrupts (mie bit) */ + let ctx = PLIC::ctx0(); + unsafe { + ctx.threshold().set_threshold(Priority::P1); + ctx.enables().enable(ExternalInterrupt::GPIO4); + mstatus::set_mie(); + PLIC::enable(); + } + loop { + riscv::asm::wfi(); + } +} diff --git a/examples/mtimer.rs b/examples/mtimer.rs new file mode 100644 index 0000000..75e504a --- /dev/null +++ b/examples/mtimer.rs @@ -0,0 +1,61 @@ +//! This example demonstrates how to configure the CLINT to generate +//! periodic interrupts using the machine timer. + +#![no_main] +#![no_std] + +extern crate panic_halt; + +use hifive1::{ + configure_clocks, + hal::{e310x::CLINT, prelude::*, DeviceResources}, + pin, sprintln, +}; + +const PERIOD_MS: u64 = 1000; +const FREQUENCY_HZ: u64 = 32768; +const CLINT_TICKS_PER_MS: u64 = PERIOD_MS * FREQUENCY_HZ / 1000; + +/// Handler for the machine timer interrupt (handled by the CLINT) +#[riscv_rt::core_interrupt(CoreInterrupt::MachineTimer)] +fn mtimer_handler() { + sprintln!("MTIMER interrupt!"); + CLINT::mtimecmp0().modify(|f| *f += CLINT_TICKS_PER_MS); +} + +#[riscv_rt::entry] +fn main() -> ! { + /* Get the ownership of the device resources singleton */ + let resources = DeviceResources::take().unwrap(); + let peripherals = resources.peripherals; + + /* Configure system clock */ + let sysclock = configure_clocks(peripherals.PRCI, peripherals.AONCLK, 64.mhz().into()); + + /* Configure stdout for printing via UART */ + let gpio = resources.pins; + hifive1::stdout::configure( + peripherals.UART0, + pin!(gpio, uart0_tx), + pin!(gpio, uart0_rx), + 115_200.bps(), + sysclock, + ); + + sprintln!("Configuring CLINT..."); + CLINT::mtimer_disable(); + let mtimer = CLINT::mtimer(); + let (mtimecmp, mtime) = (mtimer.mtimecmp0, mtimer.mtime); + mtime.write(0); + mtimecmp.write(CLINT_TICKS_PER_MS); + + sprintln!("Enabling interrupts..."); + unsafe { + riscv::interrupt::enable(); + CLINT::mtimer_enable(); + } + loop { + sprintln!("Sleeping..."); + riscv::asm::wfi(); + } +} diff --git a/examples/virq.rs b/examples/virq.rs deleted file mode 100644 index c834cf9..0000000 --- a/examples/virq.rs +++ /dev/null @@ -1,89 +0,0 @@ -#![no_main] -#![no_std] - -/* - Demonstration on how to use the feature "virq" from e310x-hal. -This feature enables a kind of vectorized interrupt matching for -all 52 the external interrupts that e310x has. It simply offers a convenient -way to handle each interrupt separately with a function called as the interrupt source. -For example, if an interrupt for GPIO0 is received, and a no mangled function called GPIO0() -exists, that function will automatically handle the exception, and it will be automatically -marked as complete by the PLIC. -This can be applied for all the 52 interrupts declared in e310x/interrupts.rs. -*/ - -extern crate panic_halt; - -use hifive1::{hal::prelude::*, hal::DeviceResources, pin, sprintln}; - -use riscv::register::mstatus; -use riscv_rt::entry; - -/* we have chosen the GPIO4 (a.k.a dig12) for this example */ -const GPIO_N: usize = 4; - -/* Handler for the GPIO0 interrupt */ -#[no_mangle] -#[allow(non_snake_case)] -fn GPIO4() { - sprintln!("We reached the GPIO4 interrupt!"); - /* Clear the GPIO pending interrupt */ - unsafe { - let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); - gpio_block.fall_ip.write(|w| w.bits(1 << GPIO_N)); - } -} - -/* Code adapted from https://github.com/riscv-rust/riscv-rust-quickstart/blob/interrupt-test/examples/interrupt.rs*/ -#[entry] -fn main() -> ! { - /* Get the ownership of the device resources singleton */ - let resources = DeviceResources::take().unwrap(); - let peripherals = resources.peripherals; - - /* Configure system clock */ - let sysclock = hifive1::configure_clocks(peripherals.PRCI, peripherals.AONCLK, 64.mhz().into()); - /* Get the board pins */ - let gpio = resources.pins; - - /* Configure stdout for debugging */ - hifive1::stdout::configure( - peripherals.UART0, - pin!(gpio, uart0_tx), - pin!(gpio, uart0_rx), - 115_200.bps(), - sysclock, - ); - - /* Set GPIO4 (pin 12) as input */ - // let gpio4 = pin!(gpio, dig12); - let input = gpio.pin4.into_pull_up_input(); - //let input = gpio4.into_pull_up_input(); - - /* Wrapper for easy access */ - let mut plic = resources.core_peripherals.plic; - - /* Unsafe block */ - unsafe { - /* Get raw PLIC pointer */ - //let rplic = &*hifive1::hal::e310x::PLIC::ptr(); - hifive1::hal::e310x::PLIC::set_priority( - &mut plic, - hifive1::hal::e310x::Interrupt::GPIO4, - e310x_hal::e310x::Priority::P7, - ); - let gpio_block = &*hifive1::hal::e310x::GPIO0::ptr(); - /* Enable GPIO fall interrupts */ - gpio_block.fall_ie.write(|w| w.bits(1 << GPIO_N)); - gpio_block.rise_ie.write(|w| w.bits(0x0)); - /* Clear pending interrupts from previous states */ - gpio_block.fall_ip.write(|w| w.bits(0xffffffff)); - gpio_block.rise_ip.write(|w| w.bits(0x0fffffff)); - - /* Activate global interrupts (mie bit) */ - mstatus::set_mie(); - plic.set_threshold(e310x_hal::e310x::Priority::P1); - plic.enable_interrupt(hifive1::hal::e310x::Interrupt::GPIO4); - } - loop {} -} diff --git a/flash.S b/flash.S deleted file mode 100644 index 53dd795..0000000 --- a/flash.S +++ /dev/null @@ -1,45 +0,0 @@ -.cfi_sections .debug_frame - -.section .data._setup_is25lp -.global _setup_is25lp -.cfi_startproc -_setup_is25lp: - li a1, 0x10014000 // QSPI0 base address - - // Disable mapped region - sw zero,96(a1) // fctrl.en = 0 - - // Construct ffmt value for 4 dummy cycles - li a2, 0x00BB1447 - - beqz a0, 2f - - // We need to set 8 dummy cycles instead of 4. - // Issue a "Set Read Parameters" command. - - li a0,2 - sw a0,24(a1) // csmode = HOLD - li a0,0xC0 - sw a0,72(a1) // txdata = 0xC0 - li a0,0xF0 - sw a0,72(a1) // txdata = 0xF0 - sw zero,24(a1) // csmode = AUTO - - // Discard two response bytes -1: lw a0,76(a1) - bltz a0,1b -1: lw a0,76(a1) - bltz a0,1b - - addi a2,a2,0x40 // ffmt: 4 -> 8 dummy cycles -2: - sw a2,100(a1) // Write ffmt - - // Enable mapped region - li a0, 1 - sw a0,96(a1) // fctrl.en = 1 - ret - - -.cfi_endproc -.size _setup_is25lp, . - _setup_is25lp diff --git a/src/clock.rs b/src/clock.rs index 05bd348..d91867a 100644 --- a/src/clock.rs +++ b/src/clock.rs @@ -2,7 +2,7 @@ use e310x_hal::{ clock::{AonExt, Clocks, PrciExt}, - e310x::{AONCLK, PRCI}, + e310x::{Aonclk, Prci}, time::Hertz, }; @@ -15,7 +15,7 @@ use e310x_hal::{ /// /// For HiFive1 and HiFive1 Rev B boards external oscillators are enabled for /// both high-frequency and low-frequency clocks. -pub fn configure(prci: PRCI, aonclk: AONCLK, target_coreclk: Hertz) -> Clocks { +pub fn configure(prci: Prci, aonclk: Aonclk, target_coreclk: Hertz) -> Clocks { let coreclk = prci.constrain(); let coreclk = coreclk .use_external(Hertz(16_000_000)) @@ -32,7 +32,7 @@ pub fn configure(prci: PRCI, aonclk: AONCLK, target_coreclk: Hertz) -> Clocks { /// /// For the LoFive and LoFive R1 boards, external oscillator is enabled for /// high-frequency clock. For low-frequency clock internal oscillator is used. -pub fn configure(prci: PRCI, aonclk: AONCLK, target_coreclk: Hertz) -> Clocks { +pub fn configure(prci: Prci, aonclk: Aonclk, target_coreclk: Hertz) -> Clocks { let coreclk = prci.constrain(); let coreclk = coreclk .use_external(Hertz(16_000_000)) diff --git a/src/flash.rs b/src/flash.rs index e138c99..68fbb6e 100644 --- a/src/flash.rs +++ b/src/flash.rs @@ -1,11 +1,62 @@ //! On-board SPI Flash use e310x_hal::clock::Clocks; -use e310x_hal::e310x::QSPI0; +use e310x_hal::e310x::Qspi0; + +#[cfg(target_arch = "riscv32")] +core::arch::global_asm!( + r#" +.cfi_sections .debug_frame + +.section .data._setup_is25lp +.global _setup_is25lp +.cfi_startproc +_setup_is25lp: + li a1, 0x10014000 // QSPI0 base address + + // Disable mapped region + sw zero,96(a1) // fctrl.en = 0 + + // Construct ffmt value for 4 dummy cycles + li a2, 0x00BB1447 + + beqz a0, 2f + + // We need to set 8 dummy cycles instead of 4. + // Issue a "Set Read Parameters" command. + + li a0,2 + sw a0,24(a1) // csmode = HOLD + li a0,0xC0 + sw a0,72(a1) // txdata = 0xC0 + li a0,0xF0 + sw a0,72(a1) // txdata = 0xF0 + sw zero,24(a1) // csmode = AUTO + + // Discard two response bytes +1: lw a0,76(a1) + bltz a0,1b +1: lw a0,76(a1) + bltz a0,1b + + addi a2,a2,0x40 // ffmt: 4 -> 8 dummy cycles +2: + sw a2,100(a1) // Write ffmt + + // Enable mapped region + li a0, 1 + sw a0,96(a1) // fctrl.en = 1 + ret + + +.cfi_endproc +.size _setup_is25lp, . - _setup_is25lp +"# +); /// Configure SPI Flash interface to maximum supported speed #[inline(always)] -pub fn configure_spi_flash(qspi: &QSPI0, clocks: &Clocks) { +pub fn configure_spi_flash(qspi: &Qspi0, clocks: &Clocks) { unsafe { extern "C" { fn _setup_is25lp(dummy8: bool); @@ -17,5 +68,5 @@ pub fn configure_spi_flash(qspi: &QSPI0, clocks: &Clocks) { _setup_is25lp(true) } } - qspi.sckdiv.modify(|_, w| unsafe { w.div().bits(0) }); + qspi.sckdiv().modify(|_, w| unsafe { w.div().bits(0) }); } diff --git a/src/stdout.rs b/src/stdout.rs index 68779d4..59be531 100644 --- a/src/stdout.rs +++ b/src/stdout.rs @@ -3,7 +3,7 @@ use core::fmt; use e310x_hal::{ clock::Clocks, - e310x::UART0, + e310x::Uart0, gpio::gpio0::{Pin16, Pin17}, prelude::*, serial::{Rx, Serial, Tx}, @@ -14,7 +14,7 @@ use riscv::interrupt; static mut STDOUT: Option = None; -struct SerialWrapper(Tx); +struct SerialWrapper(Tx); impl core::fmt::Write for SerialWrapper { fn write_str(&mut self, s: &str) -> fmt::Result { @@ -39,18 +39,18 @@ impl core::fmt::Write for SerialWrapper { /// Configures stdout pub fn configure( - uart: UART0, + uart: Uart0, tx: Pin17, rx: Pin16, baud_rate: Bps, clocks: Clocks, -) -> Rx { +) -> Rx { let tx = tx.into_iof0(); let rx = rx.into_iof0(); let serial = Serial::new(uart, (tx, rx), baud_rate, clocks); let (tx, rx) = serial.split(); - interrupt::free(|_| unsafe { + interrupt::free(|| unsafe { STDOUT.replace(SerialWrapper(tx)); }); rx @@ -58,7 +58,7 @@ pub fn configure( /// Writes string to stdout pub fn write_str(s: &str) { - interrupt::free(|_| unsafe { + interrupt::free(|| unsafe { if let Some(stdout) = STDOUT.as_mut() { let _ = stdout.write_str(s); } @@ -67,7 +67,7 @@ pub fn write_str(s: &str) { /// Writes formatted string to stdout pub fn write_fmt(args: fmt::Arguments) { - interrupt::free(|_| unsafe { + interrupt::free(|| unsafe { if let Some(stdout) = STDOUT.as_mut() { let _ = stdout.write_fmt(args); } From f1c5e01a1dc07f2f857e61030e0297518072a6fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Sat, 19 Oct 2024 12:25:42 +0200 Subject: [PATCH 20/21] point to riscv master --- Cargo.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 90e11dd..f6f71cb 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -12,8 +12,8 @@ edition = "2021" [dependencies] e310x-hal = {git = "https://github.com/greenlsi/e310x-hal"} embedded-hal = "0.2.5" -riscv = { git = "https://github.com/rust-embedded/riscv", branch = "riscv-pac-only", features = ["critical-section-single-hart"]} # TODO use crates.io -riscv-rt = { git = "https://github.com/rust-embedded/riscv", branch = "riscv-pac-only" } # TODO use crates.io +riscv = { git = "https://github.com/rust-embedded/riscv", branch = "master", features = ["critical-section-single-hart"]} # TODO use crates.io +riscv-rt = { git = "https://github.com/rust-embedded/riscv", branch = "master" } # TODO use crates.io nb = "1.0.0" panic-halt = "0.2.0" From 1e0a22d8d0dd7a1d6563afd3b133820e93a79387 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Sun, 20 Oct 2024 10:20:15 +0200 Subject: [PATCH 21/21] point to crates.io --- Cargo.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index f6f71cb..b5e2cd2 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -12,8 +12,8 @@ edition = "2021" [dependencies] e310x-hal = {git = "https://github.com/greenlsi/e310x-hal"} embedded-hal = "0.2.5" -riscv = { git = "https://github.com/rust-embedded/riscv", branch = "master", features = ["critical-section-single-hart"]} # TODO use crates.io -riscv-rt = { git = "https://github.com/rust-embedded/riscv", branch = "master" } # TODO use crates.io +riscv = { version = "0.12.0", features = ["critical-section-single-hart"]} +riscv-rt = "0.13.0" nb = "1.0.0" panic-halt = "0.2.0"