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The spec mentions the following constraint on the misa extensions:
Writing misa may increase IALIGN, e.g., by disabling the “C” extension. If an instruction that
would write misa increases IALIGN, and the subsequent instruction’s address is not IALIGN-bit
aligned, the write to misa is suppressed, leaving misa unchanged.
This means that the warl behavior of any csr field can also depend on a few additional states in the hardware. It might be useful to allow for such dependencies to be specified in the warl function itself and add misa checks to ensure that the above is satisfied if C extension can be disabled at run-time. One might argue that this is a very specific scenario which depends largely on the program flow, but I think this should be specified in the warl function. A list of possible fields which can be allowed are:
IALIGN
XLEN(incase misa.mxl is not implemented and the implementation has a non-standard way of figuring out xlen. Although I am not sure how SAIL will emulate this behavior).
The text was updated successfully, but these errors were encountered:
The spec mentions the following constraint on the misa extensions:
This means that the warl behavior of any csr field can also depend on a few additional states in the hardware. It might be useful to allow for such dependencies to be specified in the warl function itself and add misa checks to ensure that the above is satisfied if
C
extension can be disabled at run-time. One might argue that this is a very specific scenario which depends largely on the program flow, but I think this should be specified in the warl function. A list of possible fields which can be allowed are:The text was updated successfully, but these errors were encountered: