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FPGA-readBridge -hf 0 issue #2

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rokzitko opened this issue Sep 15, 2021 · 2 comments
Open

FPGA-readBridge -hf 0 issue #2

rokzitko opened this issue Sep 15, 2021 · 2 comments

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@rokzitko
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First let me thank you for putting together this very nice solution for developing on DE10* platforms.

I have some issues that I'll split into separate github issues to keep track.

The first one is that on DE10-nano, FPGA-readBridge -hf 0 hangs, right after "Bridge: HPS-to-FPGA". The chip goes into a hard lock, then the watchdog reboots the device after a while. I experience no such issue on DE10-std, though.

Kind regards,
Rok
@robseb
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robseb commented Sep 15, 2021

Is related to MSEL misconfiguration #3

@rokzitko
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rokzitko commented Sep 16, 2021 •
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I am not sure. I use the same MSEL settings. This is the output from DE10std:


**********************************************************************************************************
*                                                                                                        *
*                     ########   ######     ##    ##  #######   ######  ########  #######                *
*                     ##     ## ##    ##     ##  ##  ##     ## ##    ##    ##    ##     ##               *
*                     ##     ## ##            ####   ##     ## ##          ##    ##     ##               *
*                     ########   ######        ##    ##     ## ##          ##    ##     ##               *
*                     ##   ##         ##       ##    ##     ## ##          ##    ##     ##               *
*                     ##    ##  ##    ##       ##    ##     ## ##    ##    ##    ##     ##               *
*                     ##     ##  ######        ##     #######   ######     ##     #######                *
*                                                                                                        *
*                    --    Embedded Yocto based Linux Distro for Intel SoC-FPGAs          --             *
*                    ---        created by Robin Sebastian (github.com/robseb)           ---             *
*                    ---                   Contact: [email protected]                        ---             *
**********************************************************************************************************

-- Git Repository: https://github.com/robseb/rsyocto
-- VERSION:       1_042
-- KERNEL:        "linux-socfpga 5.11"
-- BUILD:         10 Apr 2021
-- FPGA:          Intel Cyclone V
-- BOARD:         Terasic DE10 Standard
-- IMAGE:         "rsYocto_1_042_DE10STD.img"
-- PACKING DATE:  11.04.2021
-- FPGA PROJECT:  "DE10STDrsyocto.qpf"
--FOLDER NAME:    socfpgaPlatformGenerator
 -- MAIN FEATURES:
    python3, pip3, django, sqlite, openSSH Server, apache2, php,
    gcc, gcc++, make, cmake, wget, curl, gdb server, gatord, time, nano,
    minicom, i2c-tools, spi-tools, usbutils, ethtool, iputils, git, can-tools,
    rstools, opkg, update-rc.d, crontab, devmem, iproute2, devmem, iproute2, iw
 -- FPGA:
    Sys_ID, LEDs, Switches, ADC, Seven Segment Display, Display, ...
 -- INCLUDE:
   Intel hwlib for CY5
 -- WEBITERFACE:
   Pinout and Info Page
   ***********************************************************************************************************

[email protected]'s password:
Warning: untrusted X11 forwarding setup failed: xauth key data not generated
Last login: Wed Sep 15 15:06:31 2021 from 192.168.2.155
root@cyclone5:~#  FPGA-readMSEL
-- Read the MSEL-Switch Status with the FPGA Manager of Intel Cyclone V  --
      MSEL-switch postion:
MSEL[4..0]       : 00100 [0x04]
MODE             : Passive Parallel x16 (FPPx16)
POR Delay        : Slow power on
Security         : AES Encryption Disabled
cdratio          : x1
cfgwdth		  : 0
Partial Reconfig.: supported
Data Compression : Disabled

Note: cdratio: Clock-to-data ratio field
      cfgwdth: Configuration data width bit

root@cyclone5:~# FPGA-readBridge -lw 0
	------- Read a FPGA Register via a HPS-to-FPGA Bridge -------
	Bridge:      Lightweight HPS-to-FPGA
	Brige Base:  0xff200000
	Your Offset: 0x0
	Address:     0xff200000
-------------------------------------------------------------------------------------
			      Value: 0 [0x0]
-------------------------------------------------------------------------------------
No  | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Bit |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |
-------------------------------------------------------------------------------------
No  | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Bit |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |
-------------------------------------------------------------------------------------
Reading was successfully

root@cyclone5:~# FPGA-readBridge -hf 0
	------- Read a FPGA Register via a HPS-to-FPGA Bridge -------
	Bridge:      HPS-to-FPGA
	Brige Base:  0xc0000000
	Your Offset: 0x0
	Address:     0xc0000000
-------------------------------------------------------------------------------------
			      Value: 591751049 [0x23456789]
-------------------------------------------------------------------------------------
No  | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Bit |  0 |  0 |  1 |  0 |  0 |  0 |  1 |  1 |  0 |  1 |  0 |  0 |  0 |  1 |  0 |  1 |
-------------------------------------------------------------------------------------
No  | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Bit |  0 |  1 |  1 |  0 |  0 |  1 |  1 |  1 |  1 |  0 |  0 |  0 |  1 |  0 |  0 |  1 |
-------------------------------------------------------------------------------------
Reading was successfully

With DE10-nano, lightweight bridge works, but not the HPS-FPGA bridge:

**********************************************************************************************************
*                                                                                                        *
*                     ########   ######     ##    ##  #######   ######  ########  #######                *
*                     ##     ## ##    ##     ##  ##  ##     ## ##    ##    ##    ##     ##               *
*                     ##     ## ##            ####   ##     ## ##          ##    ##     ##               *
*                     ########   ######        ##    ##     ## ##          ##    ##     ##               *
*                     ##   ##         ##       ##    ##     ## ##          ##    ##     ##               *
*                     ##    ##  ##    ##       ##    ##     ## ##    ##    ##    ##     ##               *
*                     ##     ##  ######        ##     #######   ######     ##     #######                *
*                                                                                                        *
*                    --    Embedded Yocto based Linux Distro for Intel SoC-FPGAs          --             *
*                    ---        created by Robin Sebastian (github.com/robseb)           ---             *
*                    ---                   Contact: [email protected]                        ---             *
**********************************************************************************************************

-- Git Repository: https://github.com/robseb/rsyocto
-- VERSION:       1_042
-- KERNEL:        "linux-socfpga 5.11"
-- BUILD:         10 Apr 2021
-- FPGA:          Intel Cyclone V
-- BOARD:         Terasic DE10 Nano
-- IMAGE:         "rsYocto_1_042_D10NANO.img"
-- PACKING DATE:  11.04.2021
-- FPGA PROJECT:  "DE10NANOrsyocto.qpf"
--FOLDER NAME:    socfpgaPlatformGenerator
 -- MAIN FEATURES:
    python3, pip3, django, sqlite, openSSH Server, apache2, php,
    gcc, gcc++, make, cmake, wget, curl, gdb server, gatord, time, nano,
    minicom, i2c-tools, spi-tools, usbutils, ethtool, iputils, git, can-tools,
    rstools, opkg, update-rc.d, crontab, devmem, iproute2, devmem, iproute2, iw
 -- FPGA:
    Sys_ID, LEDs, Switches, ADC, Seven Segment Display, Display, ...
 -- INCLUDE:
   Intel hwlib for CY5
 -- WEBITERFACE:
   Pinout and Info Page
   ***********************************************************************************************************

[email protected]'s password:
Warning: untrusted X11 forwarding setup failed: xauth key data not generated
root@cyclone5:~# FPGA-readMSEL
-- Read the MSEL-Switch Status with the FPGA Manager of Intel Cyclone V  --
      MSEL-switch postion:
MSEL[4..0]       : 00100 [0x04]
MODE             : Passive Parallel x16 (FPPx16)
POR Delay        : Slow power on
Security         : AES Encryption Disabled
cdratio          : x1
cfgwdth		  : 0
Partial Reconfig.: supported
Data Compression : Disabled

root@cyclone5:~# FPGA-readBridge -lw 0
	------- Read a FPGA Register via a HPS-to-FPGA Bridge -------
	Bridge:      Lightweight HPS-to-FPGA
	Brige Base:  0xff200000
	Your Offset: 0x0
	Address:     0xff200000
-------------------------------------------------------------------------------------
			      Value: 1 [0x1]
-------------------------------------------------------------------------------------
No  | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Bit |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |
-------------------------------------------------------------------------------------
No  | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Bit |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 |
-------------------------------------------------------------------------------------
Reading was successfully
root@cyclone5:~# FPGA-readBridge -hf 0
	------- Read a FPGA Register via a HPS-to-FPGA Bridge -------
	Bridge:      HPS-to-FPGA
	Brige Base:  0xc0000000
	Your Offset: 0x0
client_loop: send disconnect: Broken pipe

The amount of output before the hang is variable.

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@robseb @rokzitko