From 9937d4966f90cb6141764fd795c122659b4a870e Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 22 Oct 2020 14:48:03 -0700 Subject: [PATCH 1/3] Bump ldscript generator for L2 LIM Signed-off-by: Nathaniel Graff --- scripts/ldscript-generator | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ldscript-generator b/scripts/ldscript-generator index 3a1d07eca..24a49b585 160000 --- a/scripts/ldscript-generator +++ b/scripts/ldscript-generator @@ -1 +1 @@ -Subproject commit 3a1d07ecaa90471a798e2b2003d7b33038d6c7ae +Subproject commit 24a49b585207063e863267d3ece8a287dcf1b2d1 From 95804fc93aafe412659cd2043cc5bdc1cd6bd862 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 22 Oct 2020 14:49:54 -0700 Subject: [PATCH 2/3] Regen BSPs for L2 LIM linker scripts Signed-off-by: Nathaniel Graff --- bsp/freedom-e310-arty/metal.default.lds | 24 +++++++-- bsp/freedom-e310-arty/metal.freertos.lds | 39 ++++++++++++--- bsp/freedom-e310-arty/metal.ramrodata.lds | 23 ++++++++- bsp/freedom-e310-arty/metal.scratchpad.lds | 32 +++++++----- bsp/qemu-sifive-e31/metal.default.lds | 28 +++++++++-- bsp/qemu-sifive-e31/metal.freertos.lds | 43 ++++++++++++---- bsp/qemu-sifive-e31/metal.ramrodata.lds | 27 ++++++++-- bsp/qemu-sifive-e31/metal.scratchpad.lds | 30 ++++++++---- bsp/qemu-sifive-s51/metal.default.lds | 28 +++++++++-- bsp/qemu-sifive-s51/metal.freertos.lds | 43 ++++++++++++---- bsp/qemu-sifive-s51/metal.ramrodata.lds | 27 ++++++++-- bsp/qemu-sifive-s51/metal.scratchpad.lds | 30 ++++++++---- bsp/qemu-sifive-u54/metal.default.lds | 26 ++++++++-- bsp/qemu-sifive-u54/metal.freertos.lds | 41 ++++++++++++---- bsp/qemu-sifive-u54/metal.ramrodata.lds | 25 ++++++++-- bsp/qemu-sifive-u54/metal.scratchpad.lds | 32 +++++++----- bsp/qemu-sifive-u54mc/metal.default.lds | 26 ++++++++-- bsp/qemu-sifive-u54mc/metal.freertos.lds | 41 ++++++++++++---- bsp/qemu-sifive-u54mc/metal.ramrodata.lds | 25 ++++++++-- bsp/qemu-sifive-u54mc/metal.scratchpad.lds | 32 +++++++----- bsp/sifive-hifive-unleashed/metal.default.lds | 34 +++++++++++-- .../metal.freertos.lds | 49 +++++++++++++++---- .../metal.ramrodata.lds | 33 +++++++++++-- .../metal.scratchpad.lds | 38 +++++++------- bsp/sifive-hifive1-revb/metal.default.lds | 24 +++++++-- bsp/sifive-hifive1-revb/metal.freertos.lds | 39 ++++++++++++--- bsp/sifive-hifive1-revb/metal.ramrodata.lds | 23 ++++++++- bsp/sifive-hifive1-revb/metal.scratchpad.lds | 32 +++++++----- bsp/sifive-hifive1/metal.default.lds | 24 +++++++-- bsp/sifive-hifive1/metal.freertos.lds | 39 ++++++++++++--- bsp/sifive-hifive1/metal.ramrodata.lds | 23 ++++++++- bsp/sifive-hifive1/metal.scratchpad.lds | 30 ++++++++---- bsp/spike/metal.default.lds | 26 ++++++++-- bsp/spike/metal.freertos.lds | 41 ++++++++++++---- bsp/spike/metal.ramrodata.lds | 25 ++++++++-- bsp/spike/metal.scratchpad.lds | 32 +++++++----- 36 files changed, 897 insertions(+), 237 deletions(-) diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds index b29955b15..53fb37595 100644 --- a/bsp/freedom-e310-arty/metal.default.lds +++ b/bsp/freedom-e310-arty/metal.default.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -159,7 +160,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >rom :rom /* ITIM SECTION @@ -180,10 +180,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -260,7 +278,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/freedom-e310-arty/metal.freertos.lds b/bsp/freedom-e310-arty/metal.freertos.lds index eb8ad6b9f..cb3e8b591 100644 --- a/bsp/freedom-e310-arty/metal.freertos.lds +++ b/bsp/freedom-e310-arty/metal.freertos.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -132,15 +133,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >rom :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >rom .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -169,8 +171,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >rom :rom /* ITIM SECTION @@ -191,10 +191,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -202,6 +220,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >rom :text /* RAM SECTION @@ -218,6 +239,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -257,6 +279,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >ram :ram @@ -264,12 +287,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >ram @@ -281,7 +304,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds index 0b4db2167..3935fa347 100644 --- a/bsp/freedom-e310-arty/metal.ramrodata.lds +++ b/bsp/freedom-e310-arty/metal.ramrodata.lds @@ -28,6 +28,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -172,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -264,7 +283,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds index aed01551b..6a2bcd863 100644 --- a/bsp/freedom-e310-arty/metal.scratchpad.lds +++ b/bsp/freedom-e310-arty/metal.scratchpad.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -72,16 +73,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 ); - PROVIDE( metal_itim_0_memory_start = 0x8000000 ); - PROVIDE( metal_itim_0_memory_end = 0x8000000 + 0x4000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -160,7 +153,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram :rom /* ITIM SECTION @@ -181,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -261,7 +271,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.default.lds b/bsp/qemu-sifive-e31/metal.default.lds index d550a4ac0..a557e74ad 100644 --- a/bsp/qemu-sifive-e31/metal.default.lds +++ b/bsp/qemu-sifive-e31/metal.default.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -75,8 +76,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -156,7 +159,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >rom :rom /* ITIM SECTION @@ -177,10 +179,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -257,7 +277,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.freertos.lds b/bsp/qemu-sifive-e31/metal.freertos.lds index 9b70daa68..0ebb65933 100644 --- a/bsp/qemu-sifive-e31/metal.freertos.lds +++ b/bsp/qemu-sifive-e31/metal.freertos.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -78,8 +79,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -129,15 +132,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >rom :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >rom .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -166,8 +170,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >rom :rom /* ITIM SECTION @@ -188,10 +190,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -199,6 +219,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >rom :text /* RAM SECTION @@ -215,6 +238,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -254,6 +278,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >ram :ram @@ -261,12 +286,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >ram @@ -278,7 +303,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.ramrodata.lds b/bsp/qemu-sifive-e31/metal.ramrodata.lds index bc228a21f..26f3070cd 100644 --- a/bsp/qemu-sifive-e31/metal.ramrodata.lds +++ b/bsp/qemu-sifive-e31/metal.ramrodata.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -79,8 +80,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -169,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -261,7 +282,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-e31/metal.scratchpad.lds b/bsp/qemu-sifive-e31/metal.scratchpad.lds index c55ae5af9..42cf7ba96 100644 --- a/bsp/qemu-sifive-e31/metal.scratchpad.lds +++ b/bsp/qemu-sifive-e31/metal.scratchpad.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -71,14 +72,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -157,7 +152,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram :rom /* ITIM SECTION @@ -178,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -258,7 +270,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.default.lds b/bsp/qemu-sifive-s51/metal.default.lds index d550a4ac0..a557e74ad 100644 --- a/bsp/qemu-sifive-s51/metal.default.lds +++ b/bsp/qemu-sifive-s51/metal.default.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -75,8 +76,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -156,7 +159,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >rom :rom /* ITIM SECTION @@ -177,10 +179,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -257,7 +277,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.freertos.lds b/bsp/qemu-sifive-s51/metal.freertos.lds index 9b70daa68..0ebb65933 100644 --- a/bsp/qemu-sifive-s51/metal.freertos.lds +++ b/bsp/qemu-sifive-s51/metal.freertos.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -78,8 +79,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -129,15 +132,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >rom :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >rom .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -166,8 +170,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >rom :rom /* ITIM SECTION @@ -188,10 +190,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -199,6 +219,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >rom :text /* RAM SECTION @@ -215,6 +238,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -254,6 +278,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >ram :ram @@ -261,12 +286,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >ram @@ -278,7 +303,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.ramrodata.lds b/bsp/qemu-sifive-s51/metal.ramrodata.lds index bc228a21f..26f3070cd 100644 --- a/bsp/qemu-sifive-s51/metal.ramrodata.lds +++ b/bsp/qemu-sifive-s51/metal.ramrodata.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -79,8 +80,10 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); + PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 ); /* ROM SECTION * @@ -169,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -261,7 +282,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-s51/metal.scratchpad.lds b/bsp/qemu-sifive-s51/metal.scratchpad.lds index c55ae5af9..42cf7ba96 100644 --- a/bsp/qemu-sifive-s51/metal.scratchpad.lds +++ b/bsp/qemu-sifive-s51/metal.scratchpad.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -71,14 +72,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -157,7 +152,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram :rom /* ITIM SECTION @@ -178,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -258,7 +270,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.default.lds b/bsp/qemu-sifive-u54/metal.default.lds index 027f0d731..34b473210 100644 --- a/bsp/qemu-sifive-u54/metal.default.lds +++ b/bsp/qemu-sifive-u54/metal.default.lds @@ -22,6 +22,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -74,7 +75,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -157,7 +158,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >testram :rom /* ITIM SECTION @@ -178,10 +178,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -258,7 +276,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.freertos.lds b/bsp/qemu-sifive-u54/metal.freertos.lds index 201c9756e..167072049 100644 --- a/bsp/qemu-sifive-u54/metal.freertos.lds +++ b/bsp/qemu-sifive-u54/metal.freertos.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -77,7 +78,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -130,15 +131,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >testram :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >testram .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -167,8 +169,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >testram :rom /* ITIM SECTION @@ -189,10 +189,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -200,6 +218,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >testram :text /* RAM SECTION @@ -216,6 +237,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -255,6 +277,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >testram :ram @@ -262,12 +285,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >testram @@ -279,7 +302,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.ramrodata.lds b/bsp/qemu-sifive-u54/metal.ramrodata.lds index f4677cb0d..2d9771227 100644 --- a/bsp/qemu-sifive-u54/metal.ramrodata.lds +++ b/bsp/qemu-sifive-u54/metal.ramrodata.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -78,7 +79,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -262,7 +281,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54/metal.scratchpad.lds b/bsp/qemu-sifive-u54/metal.scratchpad.lds index 030e42b01..f078b855a 100644 --- a/bsp/qemu-sifive-u54/metal.scratchpad.lds +++ b/bsp/qemu-sifive-u54/metal.scratchpad.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -70,16 +71,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -158,7 +151,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >testram :rom /* ITIM SECTION @@ -179,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -259,7 +269,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.default.lds b/bsp/qemu-sifive-u54mc/metal.default.lds index 2c52566ff..196fe85f5 100644 --- a/bsp/qemu-sifive-u54mc/metal.default.lds +++ b/bsp/qemu-sifive-u54mc/metal.default.lds @@ -22,6 +22,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -74,7 +75,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -157,7 +158,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >testram :rom /* ITIM SECTION @@ -178,10 +178,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -261,7 +279,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.freertos.lds b/bsp/qemu-sifive-u54mc/metal.freertos.lds index 2a6e15345..6714f51cb 100644 --- a/bsp/qemu-sifive-u54mc/metal.freertos.lds +++ b/bsp/qemu-sifive-u54mc/metal.freertos.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -77,7 +78,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -130,15 +131,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >testram :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >testram .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -167,8 +169,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >testram :rom /* ITIM SECTION @@ -189,10 +189,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -200,6 +218,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >testram :text /* RAM SECTION @@ -216,6 +237,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -255,6 +277,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >testram :ram @@ -262,12 +285,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >testram @@ -282,7 +305,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.ramrodata.lds b/bsp/qemu-sifive-u54mc/metal.ramrodata.lds index 1ecc9f417..be8503f38 100644 --- a/bsp/qemu-sifive-u54mc/metal.ramrodata.lds +++ b/bsp/qemu-sifive-u54mc/metal.ramrodata.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -78,7 +79,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -265,7 +284,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds index 9779d960d..bcdbf9e89 100644 --- a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds +++ b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -70,16 +71,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -158,7 +151,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >testram :rom /* ITIM SECTION @@ -179,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -262,7 +272,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds index 4ed71b1e8..ef3b4288c 100644 --- a/bsp/sifive-hifive-unleashed/metal.default.lds +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -80,9 +81,15 @@ SECTIONS PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); PROVIDE( metal_itim_0_memory_start = 0x1800000 ); PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ + PROVIDE( metal_lim_0_memory_start = 0x8000000 ); + PROVIDE( metal_lim_0_memory_end = 0x8000000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -165,7 +172,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >rom :rom /* ITIM SECTION @@ -186,10 +192,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -270,7 +294,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.freertos.lds b/bsp/sifive-hifive-unleashed/metal.freertos.lds index 9f37ace1a..3ab330982 100644 --- a/bsp/sifive-hifive-unleashed/metal.freertos.lds +++ b/bsp/sifive-hifive-unleashed/metal.freertos.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -83,9 +84,15 @@ SECTIONS PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); PROVIDE( metal_itim_0_memory_start = 0x1800000 ); PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ + PROVIDE( metal_lim_0_memory_start = 0x8000000 ); + PROVIDE( metal_lim_0_memory_end = 0x8000000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -138,15 +145,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >rom :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >rom .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -175,8 +183,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >rom :rom /* ITIM SECTION @@ -197,10 +203,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -208,6 +232,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >rom :text /* RAM SECTION @@ -224,6 +251,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -263,6 +291,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >ram :ram @@ -270,12 +299,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >ram @@ -291,7 +320,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds index 0597a813a..97ee98d9b 100644 --- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -28,6 +28,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -84,9 +85,15 @@ SECTIONS PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); PROVIDE( metal_itim_0_memory_start = 0x1800000 ); PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ + /* User is recommended to enable the full size for manual RTL simulation run! */ + PROVIDE( metal_lim_0_memory_start = 0x8000000 ); + PROVIDE( metal_lim_0_memory_end = 0x8000000 + 0x10000 ); + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -249,10 +256,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -345,7 +370,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds index 8db14f043..f032c1bb7 100644 --- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -72,22 +73,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x1000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x1000000 + 0x2000 ); - PROVIDE( metal_itim_0_memory_start = 0x1800000 ); - PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 ); - PROVIDE( metal_itim_1_memory_start = 0x1808000 ); - PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 ); - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -166,7 +153,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram :rom /* ITIM SECTION @@ -187,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -271,7 +275,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds index 37261aadc..094dcb61e 100644 --- a/bsp/sifive-hifive1-revb/metal.default.lds +++ b/bsp/sifive-hifive1-revb/metal.default.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -159,7 +160,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >rom :rom /* ITIM SECTION @@ -180,10 +180,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -260,7 +278,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.freertos.lds b/bsp/sifive-hifive1-revb/metal.freertos.lds index 581bdaf06..4798504ed 100644 --- a/bsp/sifive-hifive1-revb/metal.freertos.lds +++ b/bsp/sifive-hifive1-revb/metal.freertos.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -132,15 +133,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >rom :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >rom .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -169,8 +171,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >rom :rom /* ITIM SECTION @@ -191,10 +191,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -202,6 +220,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >rom :text /* RAM SECTION @@ -218,6 +239,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -257,6 +279,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >ram :ram @@ -264,12 +287,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >ram @@ -281,7 +304,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds index de816fa10..6803873ce 100644 --- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds +++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds @@ -28,6 +28,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -172,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -264,7 +283,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds index 80c581e33..356726912 100644 --- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds +++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -72,16 +73,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 ); - PROVIDE( metal_itim_0_memory_start = 0x8000000 ); - PROVIDE( metal_itim_0_memory_end = 0x8000000 + 0x2000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -160,7 +153,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram :rom /* ITIM SECTION @@ -181,10 +173,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -261,7 +271,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds index b8ce9b4d6..c5026e650 100644 --- a/bsp/sifive-hifive1/metal.default.lds +++ b/bsp/sifive-hifive1/metal.default.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -156,7 +157,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >rom :rom /* ITIM SECTION @@ -177,10 +177,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -257,7 +275,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.freertos.lds b/bsp/sifive-hifive1/metal.freertos.lds index e52a891f7..974a7cbf8 100644 --- a/bsp/sifive-hifive1/metal.freertos.lds +++ b/bsp/sifive-hifive1/metal.freertos.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -129,15 +130,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >rom :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >rom .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -166,8 +168,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >rom :rom /* ITIM SECTION @@ -188,10 +188,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -199,6 +217,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >rom :text /* RAM SECTION @@ -215,6 +236,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -254,6 +276,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >ram :ram @@ -261,12 +284,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >ram @@ -278,7 +301,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds index 6114d2846..2c63a096e 100644 --- a/bsp/sifive-hifive1/metal.ramrodata.lds +++ b/bsp/sifive-hifive1/metal.ramrodata.lds @@ -27,6 +27,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -169,10 +170,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>rom :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -261,7 +280,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds index ac9521f8c..c53ac0ce2 100644 --- a/bsp/sifive-hifive1/metal.scratchpad.lds +++ b/bsp/sifive-hifive1/metal.scratchpad.lds @@ -24,6 +24,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -71,14 +72,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - PROVIDE( metal_dtim_0_memory_start = 0x80000000 ); - PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -157,7 +152,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >ram :rom /* ITIM SECTION @@ -178,10 +172,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >ram AT>ram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -258,7 +270,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >ram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.default.lds b/bsp/spike/metal.default.lds index 027f0d731..34b473210 100644 --- a/bsp/spike/metal.default.lds +++ b/bsp/spike/metal.default.lds @@ -22,6 +22,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -74,7 +75,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -157,7 +158,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >testram :rom /* ITIM SECTION @@ -178,10 +178,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -258,7 +276,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.freertos.lds b/bsp/spike/metal.freertos.lds index 201c9756e..167072049 100644 --- a/bsp/spike/metal.freertos.lds +++ b/bsp/spike/metal.freertos.lds @@ -25,6 +25,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -77,7 +78,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -130,15 +131,16 @@ SECTIONS PROVIDE_HIDDEN ( metal_destructors_end = .); } >testram :rom - .privileged_functions : ALIGN (4) { + .privileged_functions : ALIGN (32) { __privileged_functions_start__ = .; KEEP(*(privileged_functions)) - . = ALIGN(4); + . = ALIGN(32); __privileged_functions_end__ = .; } >testram .ctors : { + . = ALIGN(32); __unprivileged_section_start__ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) @@ -167,8 +169,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - __unprivileged_section_end__ = .; - } >testram :rom /* ITIM SECTION @@ -189,10 +189,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -200,6 +218,9 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) + *(freertos_system_calls) + . = ALIGN(32); + __unprivileged_section_end__ = .; } >testram :text /* RAM SECTION @@ -216,6 +237,7 @@ SECTIONS */ .data : ALIGN(8) { + . = ALIGN(32); __unprivileged_data_section_start__ = .; *(.data .data.*) *(.gnu.linkonce.d.*) @@ -255,6 +277,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); __unprivileged_data_section_end__ = .; } >testram :ram @@ -262,12 +285,12 @@ SECTIONS PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) ); PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) ); - .privileged_data (NOLOAD) : ALIGN(8) { + .privileged_data (NOLOAD) : ALIGN(32) { __privileged_data_start__ = .; *(privileged_data) /* Non kernel data is kept out of the first _Privileged_Data_Region_Size bytes of SRAM. */ - . = ALIGN(4); + . = ALIGN(32); __privileged_data_end__ = .; } >testram @@ -279,7 +302,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.ramrodata.lds b/bsp/spike/metal.ramrodata.lds index f4677cb0d..2d9771227 100644 --- a/bsp/spike/metal.ramrodata.lds +++ b/bsp/spike/metal.ramrodata.lds @@ -26,6 +26,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -78,7 +79,7 @@ SECTIONS PROVIDE(__metal_eccscrub_bit = 0); /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ + /* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */ /* User is recommended to enable the full size for manual RTL simulation run! */ PROVIDE( metal_memory_0_memory_start = 0x80000000 ); PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); @@ -170,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -262,7 +281,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); diff --git a/bsp/spike/metal.scratchpad.lds b/bsp/spike/metal.scratchpad.lds index 030e42b01..f078b855a 100644 --- a/bsp/spike/metal.scratchpad.lds +++ b/bsp/spike/metal.scratchpad.lds @@ -23,6 +23,7 @@ PHDRS ram PT_LOAD; itim_init PT_LOAD; text PT_LOAD; + lim_init PT_LOAD; } SECTIONS @@ -70,16 +71,8 @@ SECTIONS * certain core features */ PROVIDE(__metal_chicken_bit = 1); - /* The memory_ecc_scrub bit is used by _entry code to enable/disable - * memories scrubbing to zero */ PROVIDE(__metal_eccscrub_bit = 0); - /* The RAM memories map for ECC scrubbing */ - /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */ - /* User is recommended to enable the full size for manual RTL simulation run! */ - PROVIDE( metal_memory_0_memory_start = 0x80000000 ); - PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 ); - /* ROM SECTION * * The following sections contain data which lives in read-only memory, if @@ -158,7 +151,6 @@ SECTIONS *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - } >testram :rom /* ITIM SECTION @@ -179,10 +171,28 @@ SECTIONS PROVIDE( metal_segment_itim_target_start = ADDR(.itim) ); PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) ); + /* LIM SECTION + * + * The following sections contain data which is copied from read-only + * memory into a loosely integrated memory (LIM), which is shared with L2 + * cache, during pre-main program initialization. + * + * Generally, the data copied into the LIM should be performance-critical + * functions which benefit from low instruction-fetch latency. + */ + + .lim : ALIGN(8) { + *(.lim .lim.*) + } >testram AT>testram :lim_init + + PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) ); + PROVIDE( metal_segment_lim_target_start = ADDR(.lim) ); + PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) ); + /* TEXT SECTION * * The following section contains the code of the program, excluding - * everything that's been allocated into the ITIM already + * everything that's been allocated into the ITIM/LIM already */ .text : { @@ -259,7 +269,7 @@ SECTIONS PROVIDE(metal_segment_stack_end = .); } >testram :ram - .heap (NOLOAD) : ALIGN(4) { + .heap (NOLOAD) : ALIGN(8) { PROVIDE( __end = . ); PROVIDE( __heap_start = . ); PROVIDE( metal_segment_heap_target_start = . ); From 6afe4fdc0e2404b2f167d55bf23f8ca6505113dc Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Fri, 23 Oct 2020 14:40:45 -0700 Subject: [PATCH 3/3] Add support for L2 prefetcher, LIM, and perf monitor Signed-off-by: Nathaniel Graff --- .gitmodules | 9 +++++++++ freedom-metal | 2 +- programs.wake | 3 +++ software/example-l2pf | 1 + software/example-l2pm | 1 + software/lim | 1 + 6 files changed, 16 insertions(+), 1 deletion(-) create mode 160000 software/example-l2pf create mode 160000 software/example-l2pm create mode 160000 software/lim diff --git a/.gitmodules b/.gitmodules index 2cf2f2a0b..ab08378f3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -145,3 +145,12 @@ [submodule "scl-metal"] path = scl-metal url = https://github.com/sifive/scl-metal.git +[submodule "software/lim"] + path = software/lim + url = https://github.com/sifive/example-lim.git +[submodule "software/example-l2pf"] + path = software/example-l2pf + url = https://github.com/sifive/example-l2pf.git +[submodule "software/example-l2pm"] + path = software/example-l2pm + url = https://github.com/sifive/example-l2pm.git diff --git a/freedom-metal b/freedom-metal index ad5d451df..f3a9114ad 160000 --- a/freedom-metal +++ b/freedom-metal @@ -1 +1 @@ -Subproject commit ad5d451df1a0d1e67863fda342e840271e07f977 +Subproject commit f3a9114addfcce60711122b3388993123ebae36f diff --git a/programs.wake b/programs.wake index 9431828cc..bc7860be4 100644 --- a/programs.wake +++ b/programs.wake @@ -39,6 +39,9 @@ export def allFreedomESDKExamples sdkTarget = makeFreedomESDKProgram "hpm" "example", makeFreedomESDKProgram "i2c" "example", makeFreedomESDKProgram "itim" "example", + makeFreedomESDKProgram "l2pf" "example", + makeFreedomESDKProgram "l2pm" "example", + makeFreedomESDKProgram "lim" "example", makeFreedomESDKProgram "pmp" "example", makeFreedomESDKProgram "rtc" "example", makeFreedomESDKProgram "spi" "example", diff --git a/software/example-l2pf b/software/example-l2pf new file mode 160000 index 000000000..2aa54fae8 --- /dev/null +++ b/software/example-l2pf @@ -0,0 +1 @@ +Subproject commit 2aa54fae8a46be61d267a3bc786093c10c7d0671 diff --git a/software/example-l2pm b/software/example-l2pm new file mode 160000 index 000000000..e4019e62b --- /dev/null +++ b/software/example-l2pm @@ -0,0 +1 @@ +Subproject commit e4019e62ba381aea79cbdc2289b91fca1e1cf155 diff --git a/software/lim b/software/lim new file mode 160000 index 000000000..4de51db23 --- /dev/null +++ b/software/lim @@ -0,0 +1 @@ +Subproject commit 4de51db23d472b11a426086ce7b04e8860a4e22a