diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c785a02005738..6817e86fffd9f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,7 +14,7 @@ config RISCV
def_bool y
select ACPI_GENERIC_GSI if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
- select ARCH_DMA_DEFAULT_COHERENT
+ select ARCH_DMA_DEFAULT_COHERENT if !SOC_SIFIVE_EIC7700
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
@@ -36,9 +36,11 @@ config RISCV
select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
select ARCH_HAS_SYSCALL_WRAPPER
+ select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT && SOC_SIFIVE_EIC7700
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
select ARCH_HAS_UBSAN_SANITIZE_ALL
select ARCH_HAS_VDSO_DATA
+ select ARCH_KEEP_MEMBLOCK
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
select ARCH_STACKWALK
@@ -64,6 +66,7 @@ config RISCV
select CLONE_BACKWARDS
select COMMON_CLK
select CPU_PM if CPU_IDLE || HIBERNATION
+ select DMA_DIRECT_REMAP if SOC_SIFIVE_EIC7700
select EDAC_SUPPORT
select FRAME_POINTER if PERF_EVENTS || (FUNCTION_TRACER && !DYNAMIC_FTRACE)
select GENERIC_ARCH_TOPOLOGY
@@ -141,6 +144,7 @@ config RISCV
select HAVE_STACKPROTECTOR
select HAVE_SYSCALL_TRACEPOINTS
select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
+ select IOMMU_DMA if IOMMU_SUPPORT && SOC_SIFIVE_EIC7700
select IRQ_DOMAIN
select IRQ_FORCED_THREADING
select KASAN_VMALLOC if KASAN
@@ -268,12 +272,77 @@ config LOCKDEP_SUPPORT
config RISCV_DMA_NONCOHERENT
bool
+ select ARCH_HAS_DMA_CLEAR_UNCACHED if SOC_SIFIVE_EIC7700
select ARCH_HAS_DMA_PREP_COHERENT
+ select ARCH_HAS_DMA_SET_UNCACHED if SOC_SIFIVE_EIC7700
select ARCH_HAS_SETUP_DMA_OPS
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB
+config RISCV_DIE0_CACHED_OFFSET
+ hex "DIE0 memory port addr of U84"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0x80000000
+ help
+ Access to DDR memory through U84 memory port is cached.
+
+config RISCV_DIE0_MEM_MAX_SIZE
+ hex "DIE0 memory size, default 32GB"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0x800000000
+
+config RISCV_DIE0_UNCACHED_OFFSET
+ hex "DIE0 system port addr of U84"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0xc000000000
+ help
+ Access to DDR memory through U84 system port is uncached.
+ Add this offset when allocating memory from memory port(0x80000000~),
+ then memremap to virtual address.
+
+config RISCV_DIE1_CACHED_OFFSET
+ hex "DIE1 memory port addr of U84"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0x2000000000
+ help
+ Access to DIE1 DDR memory through U84 memory port is cached.
+
+config RISCV_DIE1_MEM_MAX_SIZE
+ hex "DIE1 memory size, default 32GB"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0x800000000
+
+config RISCV_DIE1_UNCACHED_OFFSET
+ hex "DIE1 system port addr of U84"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0xe000000000
+ help
+ Access to DIE1 DDR memory through U84 system port is uncached.
+ Add this offset when allocating memory from memory port(0x2000000000~),
+ then memremap to virtual address.
+
+config RISCV_INTERLEAVE_CACHED_OFFSET
+ hex "memory port addr of interleave"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0x4000000000
+ help
+ Access to DDR memory through U84 memory port with interleave is cached.
+
+config RISCV_INTERLEAVE_MEM_MAX_SIZE
+ hex "Interleaving memory size, default 64GB"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0x1000000000
+
+config RISCV_INTERLEAVE_UNCACHED_OFFSET
+ hex "system port addr of interleave"
+ depends on RISCV && ARCH_HAS_DMA_SET_UNCACHED
+ default 0x10000000000
+ help
+ Access to DDR memory through U84 system port with interleave is uncached.
+ Add this offset when allocating memory from memory port(0x4000000000~),
+ then memremap to virtual address.
+
config RISCV_NONSTANDARD_CACHE_OPS
bool
help
@@ -328,7 +397,7 @@ config ARCH_RV64I
bool "RV64I"
select 64BIT
select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
- select SWIOTLB if MMU
+ select SWIOTLB if MMU && !SOC_SIFIVE_EIC7700
endchoice
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 30fd6a5128285..bad861ecdcd39 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -16,9 +16,16 @@ config ARCH_RENESAS
config ARCH_SIFIVE
def_bool SOC_SIFIVE
+config SOC_SIFIVE_EIC7700
+ bool "SiFive eic7700 SoC"
+ select RISCV_NONSTANDARD_CACHE_OPS
+ help
+ This enables support for SiFive EIC7700 platform hardware.
+
config SOC_SIFIVE
bool "SiFive SoCs"
select ERRATA_SIFIVE if !XIP_KERNEL
+ select RISCV_DMA_NONCOHERENT if SOC_SIFIVE_EIC7700
help
This enables support for SiFive SoC platform hardware.
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index f60a280abb157..a0889f1b13750 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
subdir-y += canaan
+subdir-y += eswin
subdir-y += microchip
subdir-y += renesas
subdir-y += sifive
diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
new file mode 100644
index 0000000000000..b386475d14f23
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SIFIVE) += hifive-premier-p550.dtb
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi b/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi
new file mode 100644
index 0000000000000..0ffbfd21e8ec0
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-arch.dtsi
@@ -0,0 +1,539 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Eswin EIC7700 SoC's cpu.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+
+#define UART0_INT 100
+#define UART1_INT 101
+#define UART2_INT 102
+#define UART3_INT 103
+#define UART4_INT 104
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "eic7700-dev";
+
+ L64: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+ L17: cpu@0 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L15>;
+ reg = <0x0>;
+ riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L16>;
+ status = "okay";
+ timebase-frequency = ;
+ tlb-split;
+ clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_0>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L14: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L13: pmu {
+ riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+ 0x0 0x1 0xffffffff 0xfffe07ff 0x78
+ 0x0 0x2 0xffffffff 0xfffe00ff 0x78
+ 0x0 0x3 0xfffffffc 0xff 0x78
+ 0x0 0x4 0xffffffc0 0xff 0x78
+ 0x0 0x5 0xffffffff 0xfffffdff 0x78
+ 0x0 0x6 0xfffffe00 0x110204ff 0x78
+ 0x0 0x7 0xffffffff 0xf00000ff 0x78
+ 0x0 0x8 0xfffffe04 0xff 0x78
+ 0x0 0x9 0xffffffff 0xffffc0ff 0x78
+ 0x0 0xa 0xffffffff 0xf00000ff 0x78
+ 0x0 0xb 0xffffffff 0xfffffcff 0x78
+ 0x0 0xc 0xfffffff0 0xff 0x78
+ 0x0 0xd 0xffffffff 0x800000ff 0x78
+ 0x0 0xe 0xffffffff 0xf80000ff 0x78
+ 0x0 0xf 0xfffffffc 0xff 0x78>;
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+ riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L14 13>;
+ };
+ };
+ L22: cpu@1 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L20>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L21>;
+ status = "okay";
+ timebase-frequency = ;
+ tlb-split;
+ clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_1>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L19: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L18: pmu {
+ riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+ 0x0 0x1 0xffffffff 0xfffe07ff 0x78
+ 0x0 0x2 0xffffffff 0xfffe00ff 0x78
+ 0x0 0x3 0xfffffffc 0xff 0x78
+ 0x0 0x4 0xffffffc0 0xff 0x78
+ 0x0 0x5 0xffffffff 0xfffffdff 0x78
+ 0x0 0x6 0xfffffe00 0x110204ff 0x78
+ 0x0 0x7 0xffffffff 0xf00000ff 0x78
+ 0x0 0x8 0xfffffe04 0xff 0x78
+ 0x0 0x9 0xffffffff 0xffffc0ff 0x78
+ 0x0 0xa 0xffffffff 0xf00000ff 0x78
+ 0x0 0xb 0xffffffff 0xfffffcff 0x78
+ 0x0 0xc 0xfffffff0 0xff 0x78
+ 0x0 0xd 0xffffffff 0x800000ff 0x78
+ 0x0 0xe 0xffffffff 0xf80000ff 0x78
+ 0x0 0xf 0xfffffffc 0xff 0x78>;
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+ riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L19 13>;
+ };
+ };
+ L27: cpu@2 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L25>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L26>;
+ status = "okay";
+ timebase-frequency = ;
+ tlb-split;
+ clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_2>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L24: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L23: pmu {
+ riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+ 0x0 0x1 0xffffffff 0xfffe07ff 0x78
+ 0x0 0x2 0xffffffff 0xfffe00ff 0x78
+ 0x0 0x3 0xfffffffc 0xff 0x78
+ 0x0 0x4 0xffffffc0 0xff 0x78
+ 0x0 0x5 0xffffffff 0xfffffdff 0x78
+ 0x0 0x6 0xfffffe00 0x110204ff 0x78
+ 0x0 0x7 0xffffffff 0xf00000ff 0x78
+ 0x0 0x8 0xfffffe04 0xff 0x78
+ 0x0 0x9 0xffffffff 0xffffc0ff 0x78
+ 0x0 0xa 0xffffffff 0xf00000ff 0x78
+ 0x0 0xb 0xffffffff 0xfffffcff 0x78
+ 0x0 0xc 0xfffffff0 0xff 0x78
+ 0x0 0xd 0xffffffff 0x800000ff 0x78
+ 0x0 0xe 0xffffffff 0xf80000ff 0x78
+ 0x0 0xf 0xfffffffc 0xff 0x78>;
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+ riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L24 13>;
+ };
+ };
+ L32: cpu@3 {
+ clock-frequency = <0>;
+ compatible = "eswin,eic770x", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <4>;
+ hwpf-distanceBits = <6>;
+ hwpf-hitCacheThrdBits = <5>;
+ hwpf-hitMSHRThrdBits = <4>;
+ hwpf-l2pfPoolSize = <10>;
+ hwpf-nIssQEnt = <6>;
+ hwpf-nPrefetchQueueEntries = <8>;
+ hwpf-nStreams = <16>;
+ hwpf-qFullnessThrdBits = <4>;
+ hwpf-windowBits = <6>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <&L30>;
+ reg = <0x3>;
+ riscv,isa = "rv64imafdc_h_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <4096>;
+ riscv,pmpregions = <8>;
+ sifive,buserror = <&L31>;
+ status = "okay";
+ timebase-frequency = ;
+ tlb-split;
+ clocks = <&d0_clock EIC7700_CLK_CPU_EXT_SRC_CORE_CLK_3>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
+ L29: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ L28: pmu {
+ riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xff 0x78
+ 0x0 0x1 0xffffffff 0xfffe07ff 0x78
+ 0x0 0x2 0xffffffff 0xfffe00ff 0x78
+ 0x0 0x3 0xfffffffc 0xff 0x78
+ 0x0 0x4 0xffffffc0 0xff 0x78
+ 0x0 0x5 0xffffffff 0xfffffdff 0x78
+ 0x0 0x6 0xfffffe00 0x110204ff 0x78
+ 0x0 0x7 0xffffffff 0xf00000ff 0x78
+ 0x0 0x8 0xfffffe04 0xff 0x78
+ 0x0 0x9 0xffffffff 0xffffc0ff 0x78
+ 0x0 0xa 0xffffffff 0xf00000ff 0x78
+ 0x0 0xb 0xffffffff 0xfffffcff 0x78
+ 0x0 0xc 0xfffffff0 0xff 0x78
+ 0x0 0xd 0xffffffff 0x800000ff 0x78
+ 0x0 0xe 0xffffffff 0xf80000ff 0x78
+ 0x0 0xf 0xfffffffc 0xff 0x78>;
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x4 0x6 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>;
+ riscv,event-to-mhpmevent = <0x4 0x0 0x202 0x5 0x0 0x4000 0x6 0x0 0x2001 0x10009 0x0 0x102 0x10019 0x0 0x1002 0x10021 0x0 0x802>;
+ compatible = "riscv,pmu0", "riscv,pmu";
+ interrupts-extended = <&L29 13>;
+ };
+ };
+ };
+ L50: memory@80000000 {
+ compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port";
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x7f 0x80000000>;
+ sifive,port-width-bytes = <32>;
+ };
+ SOC: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "SiFive,FU800-soc", "fu800-soc", "sifive-soc", "simple-bus";
+ ranges;
+ L40: authentication-controller {
+ compatible = "sifive,authentication0";
+ sifive,auth-types = "fuse";
+ };
+ L51: axi4-sys-port@40000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+ ranges = <0x40000000 0x0 0x40000000 0x40000000>;
+ sifive,port-width-bytes = <16>;
+ };
+ L52: axi4-sys-port@8000000000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus";
+ ranges = <0x80 0x0 0x80 0x0 0x180 0x0>;
+ sifive,port-width-bytes = <16>;
+ };
+ L46: basic-bus-blocker@200000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x200000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L43: basic-bus-blocker@202000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x202000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L48: basic-bus-blocker@204000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x0 0x204000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L54: burst-bundler@10010000 {
+ compatible = "sifive,burst-bundler0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L16: bus-error-unit@hart0 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <517>;
+ reg = <0x0 0x1700000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L21: bus-error-unit@hart1 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <518>;
+ reg = <0x0 0x1701000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L26: bus-error-unit@hart2 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <519>;
+ reg = <0x0 0x1702000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L31: bus-error-unit@hart3 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <&plic0>;
+ interrupts = <520>;
+ reg = <0x0 0x1703000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L7: cache-controller@2010000 {
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <4096>;
+ cache-size = <4194304>;
+ cache-unified;
+ compatible = "sifive,eic7700";
+ interrupt-parent = <&plic0>;
+ interrupts = <1>, <3>, <4>, <2>;
+ next-level-cache = <&L9 &L10 &L11 &L50>;
+ reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x400000>;
+ reg-names = "control", "sideband";
+ sifive,a-mshr-count = <60>;
+ sifive,bank-count = <4>;
+ sifive,ecc-granularity = <8>;
+ sifive,max-master-id = <13>;
+ sifive,perfmon-counters = <6>;
+ numa-node-id = <0>;
+ };
+
+ L34: debug-controller@0 {
+ compatible = "sifive,debug-100", "riscv,debug-100";
+ debug-attach = "jtag";
+ reg = <0x0 0x0 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L8: error-device@1000 {
+ compatible = "sifive,error0";
+ reg = <0x0 0x1000 0x0 0x3000 0x0 0x5000 0x0 0x13000 0x0 0x19000 0x0 0xe7000 0x0 0x114000 0x0 0xec000 0x0 0x201000 0x0 0x1000 0x0 0x203000 0x0 0x1000 0x0 0x205000 0x0 0x14fb000 0x0 0x1704000 0x0 0x8fc000 0x0 0x2014000 0x0 0x5fec000 0x0 0x8400000 0x0 0x3c00000 0x0 0x10000000 0x0 0x3000 0x0 0x10004000 0x0 0xc000 0x0 0x10011000 0x0 0x1f000 0x0 0x10034000 0x0 0x9fcc000 0x0 0x1a400000 0x0 0x5c00000>;
+ };
+ L9: error-device@10003000 {
+ compatible = "sifive,error0";
+ reg = <0x0 0x10003000 0x0 0x1000>;
+ };
+
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <
+ &L14 0xffffffff &L14 9
+ &L19 0xffffffff &L19 9
+ &L24 0xffffffff &L24 9
+ &L29 0xffffffff &L29 9>;
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <520>;
+ };
+ L53: order-obliterator@10030000 {
+ compatible = "sifive,order-obliterator0";
+ interrupt-parent = <&plic0>;
+ interrupts = <516>;
+ reg = <0x0 0x10030000 0x0 0x4000>;
+ reg-names = "control";
+ };
+ L15: pl2@104000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x104000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L20: pl2@108000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x108000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L25: pl2@10c000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x10c000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L30: pl2@110000 {
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0", "cache";
+ next-level-cache = <&L7>;
+ reg = <0x0 0x110000 0x0 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <16>;
+ sifive,perfmon-counters = <6>;
+ };
+ L10: rom@1a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x0 0x1a000000 0x0 0x400000>;
+ };
+ L11: rom@3a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x0 0x3a000000 0x0 0x400000>;
+ };
+ L6: subsystem_pbus_clock {
+ #clock-cells = <0>;
+ clock-frequency = <10000000>;
+ clock-output-names = "subsystem_pbus_clock";
+ compatible = "fixed-clock";
+ };
+ L61: teststatus@4000 {
+ compatible = "sifive,test0";
+ reg = <0x0 0x4000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L45: tl-address-adjuster@20000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sifive,tl-inter-sys-port", "sifive,tl-port", "simple-external-bus", "simple-bus";
+ ranges = <0x20000000 0x0 0x20000000 0x1a000000 0x3a400000 0x0 0x3a400000 0x5c00000>;
+ sifive,port-width-bytes = <8>;
+ };
+ L42: tl-inter-mem-master-port@80000000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,tl-inter-mem-master-port", "sifive,tl-port", "sifive,inter-mem-master-port", "simple-external-bus", "simple-bus";
+ ranges = <0x0 0x80000000 0x0 0x80000000 0x7f 0x80000000>;
+ sifive,port-width-bytes = <32>;
+ };
+ L55: trace-encoder-0@100000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x100000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L56: trace-encoder-1@101000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x101000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L57: trace-encoder-2@102000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x102000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L58: trace-encoder-3@103000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x103000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ L59: trace-funnel-0@18000 {
+ compatible = "sifive,trace0";
+ reg = <0x0 0x18000 0x0 0x1000>;
+ reg-names = "control";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-noc.dtsi b/arch/riscv/boot/dts/eswin/eic7700-noc.dtsi
new file mode 100644
index 0000000000000..a4e1435488329
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-noc.dtsi
@@ -0,0 +1,2620 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Include file for Die0 NOC monitor of Eswin EIC770x family SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+d0_cfg_noc:d0_cfg_noc{
+ compatible = "eswin,eic7700-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52060000 0 0x4000>;
+
+ interrupts = <446>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 5>;
+
+ sideband_manager@52061000{
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52061000 0 0x10>;
+ SenseIn0 =
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ bf-name =
+ "SBM_CLMM",
+ "SBM_CNOC_AON",
+ "SBM_CNOC_DDRT0_CTRL",
+ "SBM_CNOC_DDRT0_PHY ",
+ "SBM_CNOC_DDRT1_CTRL",
+ "SBM_CNOC_DDRT1_PHY",
+ "SBM_CNOC_DSPT",
+ "SBM_CNOC_GPU",
+ "SBM_CNOC_HSP",
+ "SBM_CNOC_LSP_APB2",
+ "SBM_CNOC_LSP_APB3",
+ "SBM_CNOC_LSP_APB4",
+ "SBM_CNOC_LSP_APB6",
+ "SBM_CNOC_MCPUT_D2D",
+ "SBM_CNOC_NPU",
+ "SBM_CNOC_PCIET_P",
+ "SBM_CNOC_PCIET_X",
+ "SBM_CNOC_TCU",
+ "SBM_CNOC_VC",
+ "SBM_CNOC_VI",
+ "SBM_CNOC_VO";
+ };
+ ErrorLogger0 {
+ compatible = "eswin,eic7700,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0 1>;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 1 4>;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 15 1 >; /*bit 15 will aloways be 0, then we will always get "snoc_cnoc/I/0"*/
+ lut =
+ "snoc_cnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 10 5 >;
+ lut =
+ "clmm/T/0",
+ "cnoc_aon/T/0",
+ "cnoc_ddrt0_ctrl/T/0",
+ "cnoc_ddrt0_phy/T/0",
+ "cnoc_ddrt1_ctrl/T/0",
+ "cnoc_ddrt1_phy/T/0",
+ "cnoc_dspt/T/0",
+ "cnoc_gpu/T/0",
+ "cnoc_hsp/T/0",
+ "cnoc_lsp_apb2/T/0",
+ "cnoc_lsp_apb3/T/0",
+ "cnoc_lsp_apb4/T/0",
+ "cnoc_lsp_apb6/T/0",
+ "cnoc_mcput_d2d/T/0",
+ "cnoc_npu/T/0",
+ "cnoc_pciet_p/T/0",
+ "cnoc_pciet_x/T/0",
+ "cnoc_service/T/0",
+ "cnoc_tcu/T/0",
+ "cnoc_vc/T/0",
+ "cnoc_vi/T/0",
+ "cnoc_vo/T/0",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 8 2 >;
+ };
+
+ SeqId {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0 8 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,eic7700,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger1 whose information are required to calculate real absolute address */
+ AbsoluteAddress {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 8 8 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 46 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x51600000>,
+ /bits/ 64 <0x0 0x0 0x1 0x71600000>,
+ /bits/ 64 <0x0 0x1 0x0 0x51800000>,
+ /bits/ 64 <0x0 0x1 0x1 0x71800000>,
+ /bits/ 64 <0x0 0x1 0x2 0x0 >,
+ /bits/ 64 <0x0 0x1 0x3 0x0 >,
+ /bits/ 64 <0x0 0x2 0x0 0x52300000>,
+ /bits/ 64 <0x0 0x2 0x1 0x72300000>,
+ /bits/ 64 <0x0 0x3 0x0 0x53000000>,
+ /bits/ 64 <0x0 0x3 0x1 0x73000000>,
+ /bits/ 64 <0x0 0x4 0x0 0x52380000>,
+ /bits/ 64 <0x0 0x4 0x1 0x72380000>,
+ /bits/ 64 <0x0 0x5 0x0 0x53800000>,
+ /bits/ 64 <0x0 0x5 0x1 0x73800000>,
+ /bits/ 64 <0x0 0x6 0x0 0x52200000>,
+ /bits/ 64 <0x0 0x6 0x1 0x72200000>,
+ /bits/ 64 <0x0 0x7 0x0 0x51400000>,
+ /bits/ 64 <0x0 0x7 0x1 0x71400000>,
+ /bits/ 64 <0x0 0x8 0x0 0x50400000>,
+ /bits/ 64 <0x0 0x8 0x1 0x70400000>,
+ /bits/ 64 <0x0 0x9 0x0 0x50800000>,
+ /bits/ 64 <0x0 0x9 0x1 0x70800000>,
+ /bits/ 64 <0x0 0xa 0x0 0x50900000>,
+ /bits/ 64 <0x0 0xa 0x1 0x70900000>,
+ /bits/ 64 <0x0 0xb 0x0 0x50a00000>,
+ /bits/ 64 <0x0 0xb 0x1 0x70a00000>,
+ /bits/ 64 <0x0 0xc 0x0 0x50b00000>,
+ /bits/ 64 <0x0 0xc 0x1 0x70b00000>,
+ /bits/ 64 <0x0 0xd 0x0 0x52100000>,
+ /bits/ 64 <0x0 0xd 0x1 0x72100000>,
+ /bits/ 64 <0x0 0xe 0x0 0x51c00000>,
+ /bits/ 64 <0x0 0xe 0x1 0x71c00000>,
+ /bits/ 64 <0x0 0xf 0x0 0x50000000>,
+ /bits/ 64 <0x0 0xf 0x1 0x70000000>,
+ /bits/ 64 <0x0 0x10 0x0 0x54000000>,
+ /bits/ 64 <0x0 0x10 0x1 0x74000000>,
+ /bits/ 64 <0x0 0x11 0x0 0x52060000>,
+ /bits/ 64 <0x0 0x11 0x1 0x72060000>,
+ /bits/ 64 <0x0 0x12 0x0 0x50c00000>,
+ /bits/ 64 <0x0 0x12 0x1 0x70c00000>,
+ /bits/ 64 <0x0 0x13 0x0 0x50100000>,
+ /bits/ 64 <0x0 0x13 0x1 0x70100000>,
+ /bits/ 64 <0x0 0x14 0x0 0x51000000>,
+ /bits/ 64 <0x0 0x14 0x1 0x71000000>,
+ /bits/ 64 <0x0 0x15 0x0 0x50200000>,
+ /bits/ 64 <0x0 0x15 0x1 0x70200000>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,eic7700,register";
+ offset,length = < 0x28 32>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0x0 7 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0",
+ "Prot_1",
+ "Prot_2";
+ };
+ };
+};
+
+d0_llc_noc:d0_llc_noc@52081400 {
+ compatible = "eswin,eic7700-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52081400 0 0x4000>;
+ interrupts = <441>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 4 5>;
+ sideband_manager@52082000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52082000 0 0x10>;
+ SenseIn0 =
+ ,
+ ,
+ ,
+ ;
+ bf-name =
+ "SBM_LNOC_NPU_LLC0",
+ "SBM_LNOC_NPU_LLC1",
+ "SBM_LNOC_DDRT0_P0",
+ "SBM_LNOC_DDRT1_P0";
+ };
+
+ llcnoc_packet_ddr0_p0_req_probe@52080000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52080000 0 0x4000>;
+ clocks = <&d0_clock EIC7700_CLK_DDRT0_P0_ACLK>;
+ clock-names = "clk";
+ interrupts = <445>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p0_req";
+ };
+ llcnoc_packet_ddr1_p0_req_probe@52080800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52080800 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_DDRT1_P0_ACLK>;
+ clock-names = "clk";
+ interrupts = <443>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p0_req";
+ };
+ llcnoc_trans_probe@52081000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52081000 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <441>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "npu_llc0", "npu_llc1";
+ llcnoc_trans_npu_llc0_filter@52081480 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52081480 0 0x80>;
+ };
+ llcnoc_trans_npu_llc1_filter@52081500 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52081500 0 0x80>;
+ };
+ llcnoc_trans_profiler@52081580 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52081580 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,eic7700,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0 1 >;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 1 4 >;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 14 2 >;
+ lut =
+ "npu_lnoc_llc0/I/0",
+ "npu_lnoc_llc1/I/0",
+ "snoc_lnoc/I/0",
+ "RESERVED";
+ };
+
+ TargetFlow {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 12 2 >;
+ lut =
+ "lnoc_ddrt0_p0/T/0",
+ "lnoc_ddrt1_p0/T/0",
+ "lnoc_service/T/0",
+ "RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 8 4 >;
+ };
+
+ SeqId {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0 8 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,eic7700,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 8 8 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 53 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 <0x0 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x0 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x0 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x0 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x0 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x0 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x0 0x0 0x6 0xc000000000 >,
+ /bits/ 64 <0x0 0x0 0x7 0xe000000000 >,
+ /bits/ 64 <0x0 0x0 0x8 0x4000000000 >,
+ /bits/ 64 <0x0 0x0 0x9 0x4000000100 >,
+ /bits/ 64 <0x0 0x0 0xa 0x10000000000 >,
+ /bits/ 64 <0x0 0x0 0xb 0x10000000100 >,
+ /bits/ 64 <0x0 0x0 0xc 0x0 >,
+ /bits/ 64 <0x0 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x0 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x0 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x0 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x0 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x0 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x0 0x1 0x6 0xc000000080 >,
+ /bits/ 64 <0x0 0x1 0x7 0xe000000080 >,
+ /bits/ 64 <0x0 0x1 0x8 0x4000000080 >,
+ /bits/ 64 <0x0 0x1 0x9 0x4000000180 >,
+ /bits/ 64 <0x0 0x1 0xa 0x10000000080 >,
+ /bits/ 64 <0x0 0x1 0xb 0x10000000180 >,
+ /bits/ 64 <0x1 0x0 0x0 0x80000000 >,
+ /bits/ 64 <0x1 0x0 0x1 0x100000000 >,
+ /bits/ 64 <0x1 0x0 0x2 0x200000000 >,
+ /bits/ 64 <0x1 0x0 0x3 0x400000000 >,
+ /bits/ 64 <0x1 0x0 0x4 0x800000000 >,
+ /bits/ 64 <0x1 0x0 0x5 0x2000000000 >,
+ /bits/ 64 <0x1 0x0 0x6 0xc000000000 >,
+ /bits/ 64 <0x1 0x0 0x7 0xe000000000 >,
+ /bits/ 64 <0x1 0x0 0x8 0x4000000000 >,
+ /bits/ 64 <0x1 0x0 0x9 0x4000000100 >,
+ /bits/ 64 <0x1 0x0 0xa 0x10000000000 >,
+ /bits/ 64 <0x1 0x0 0xb 0x10000000100 >,
+ /bits/ 64 <0x1 0x0 0xc 0x0 >,
+ /bits/ 64 <0x1 0x1 0x0 0x80000080 >,
+ /bits/ 64 <0x1 0x1 0x1 0x100000080 >,
+ /bits/ 64 <0x1 0x1 0x2 0x200000080 >,
+ /bits/ 64 <0x1 0x1 0x3 0x400000080 >,
+ /bits/ 64 <0x1 0x1 0x4 0x800000080 >,
+ /bits/ 64 <0x1 0x1 0x5 0x2000000080 >,
+ /bits/ 64 <0x1 0x1 0x6 0xc000000080 >,
+ /bits/ 64 <0x1 0x1 0x7 0xe000000080 >,
+ /bits/ 64 <0x1 0x1 0x8 0x4000000080 >,
+ /bits/ 64 <0x1 0x1 0x9 0x4000000180 >,
+ /bits/ 64 <0x1 0x1 0xa 0x10000000080 >,
+ /bits/ 64 <0x1 0x1 0xb 0x10000000180 >,
+ /bits/ 64 <0x2 0x2 0x0 0x52080000 >,
+ /bits/ 64 <0x2 0x2 0x1 0x72080000 >,
+ /bits/ 64 <0x2 0x2 0x2 0x0 >;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,eic7700,register";
+ offset,length = < 0x24 32>;
+ description = "Register 4 to log errors";
+ addr_msb {
+ compatible = "eswin,eic7700,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,eic7700,register";
+ offset,length = < 0x28 32 >;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0x0 16 >;
+ lut =
+ "Cache_0",
+ "Cache_1",
+ "Cache_2",
+ "Cache_3",
+ "Prot_0",
+ "Prot_1",
+ "Prot_2",
+ "Qos_0",
+ "Qos_1",
+ "Qos_2",
+ "Qos_3",
+ "User_0",
+ "User_1",
+ "User_2",
+ "User_3",
+ "User_4";
+ };
+ };
+};
+
+d0_sys_noc:d0_sys_noc@52002C00 {
+ compatible = "eswin,eic7700-noc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0 0x52002C00 0 0x4000>;
+ interrupts = <431>;
+ interrupt-names = "error";
+ interrupt-parent = <&plic0>;
+ errlogger,idx = <0 1 3 4 5>;
+
+ eswin,qos-configs = "DSPT", "NPU", "SPISLV_TBU3";
+ eswin,DSPT-qos-base = <0x52002C80>;
+ eswin,DSPT-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode 0:fixed 1:limiter 2:bypass 3:regulator*/
+ /* a number of (1/256)th of Bytes/cycle.
+ Ex:zebu zdfi design feature, dsp AXI Clk=1040MHz, BW=12.1875MB/s, register value = (9.375/1040)*256 = 0x03
+ */
+ 0x10 0x03 /* bandwidth. 12.1875MB/s */
+ /*
+ Saturation(B) = ((Requried Bandwidth)*(Windows Time of Bandwidth Calculation))/16
+ Ex:16 byte saturation for BW=12.1875MB/s means 1.313us window time.
+ The desired value is number of saturation bytes divided by 16(ex,1 for 16byte B)
+ */
+ 0x14 0x1 /* saturation, 1.313us*/
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,NPU-qos-base = <0x52002D00>;
+ eswin,NPU-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+
+ eswin,SPISLV_TBU3-qos-base = <0x52002D80>;
+ eswin,SPISLV_TBU3-qos-settings = <
+ 0x8 0x4 /* prio */
+ 0xC 0x2 /* mode */
+ 0x10 0x18 /* bandwidth */
+ 0x14 0x10 /* saturation */
+ 0x18 0x1>; /* QoSEn */
+ sideband_manager@52004000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0 0x52004000 0 0x10>;
+ SenseIn0 =
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ bf-name =
+ "SBM_AON_SNOC_SP0",
+ "SBM_DSPT_SNOC",
+ "SBM_JTAG_SNOC",
+ "SBM_MCPUT_SNOC_D2D ",
+ "SBM_MCPUT_SNOC_MP",
+ "SBM_MCPUT_SNOC_SP0",
+ "SBM_MCPUT_SNOC_SP1",
+ "SBM_NPU_SNOC_SP0",
+ "SBM_NPU_SNOC_SP1",
+ "SBM_PCIET_SNOC_P",
+ "SBM_SPISLV_PCIET_SNOC",
+ "SBM_TBU4_SNOC",
+ "SBM_TCU_SNOC",
+ "SBM_SNOC_AON",
+ "SBM_SNOC_DDR0_P1",
+ "SBM_SNOC_DDR0_P2",
+ "SBM_SNOC_DDR1_P1",
+ "SBM_SNOC_DDR1_P2",
+ "SBM_SNOC_DSPT",
+ "SBM_SNOC_MCPUT_D2D",
+ "SBM_SNOC_NPU",
+ "SBM_SNOC_PCIET";
+ };
+ sysnoc_packet_ddr0_p1_req_probe@52000000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52000000 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_DDRT0_P1_ACLK>;
+ clock-names = "clk";
+ interrupts = <439>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p1_req";
+ };
+ sysnoc_packet_ddr0_p2_req_probe@52000800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52000800 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_DDRT0_P2_ACLK>;
+ clock-names = "clk";
+ interrupts = <437>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr0_p2_req";
+ };
+ sysnoc_packet_ddr1_p1_req_probe@52001000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52001000 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_DDRT1_P1_ACLK>;
+ clock-names = "clk";
+ interrupts = <435>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p1_req";
+ };
+ sysnoc_packet_ddr1_p2_req_probe@52001800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0 0x52001800 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_DDRT1_P2_ACLK>;
+ clock-names = "clk";
+ interrupts = <433>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <1>;
+ counter,nr = <2>;
+ portsel = "ddr1_p2_req";
+ };
+ sysnoc_trans_probe_0@52002000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52002000 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <430>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "dspt_snoc", "npu_sp1";
+ sysnoc_trans_dspt_filter@52002E00 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002E00 0 0x80>;
+ };
+ sysnoc_trans_npu_sp1_filter@52002F80 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002F80 0 0x80>;
+ };
+ sysnoc_trans_profiler@52003180 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52003180 0 0x80>;
+ };
+ };
+ sysnoc_trans_probe_1@52002400 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52002400 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <429>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <3>;
+ counter,nr = <12>;
+ profiler,nr = <1>;
+ portsel = "mcput_mp", "mcput_sp1", "tcu";
+ sysnoc_trans_mcput_mp_filter@52002E80 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002E80 0 0x80>;
+ };
+ sysnoc_trans_mcput_sp1_filter@52002F00 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52002F00 0 0x80>;
+ };
+ sysnoc_trans_tcu_filter@52003100 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52003100 0 0x80>;
+ };
+ sysnoc_trans_profiler@52003200 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52003200 0 0x80>;
+ };
+ };
+ sysnoc_trans_probe_2@52002800 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0 0x52002800 0 0x4000>;
+ clocks =<&d0_clock EIC7700_CLK_NOC_NSP_CLK>;
+ clock-names = "clk";
+ interrupts = <428>;
+ interrupt-names = "stat";
+ interrupt-parent = <&plic0>;
+ filter,nr = <2>;
+ counter,nr = <8>;
+ profiler,nr = <1>;
+ portsel = "spislv_tbu3", "tbu4_snoc";
+ sysnoc_trans_spislv_tbu3_filter@52003000 { /*pcie subsys*/
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52003000 0 0x80>;
+ };
+ sysnoc_trans_tbu4_filter@52003080 { /*aon subsys*/
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0 0x52003080 0 0x80>;
+ };
+ sysnoc_trans_profiler@52003280 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0 0x52003280 0 0x80>;
+ };
+ };
+ ErrorLogger0 {
+ compatible = "eswin,eic7700,register";
+ offset,length = < 0x14 32 >;
+ description = "Register 0 to log errors";
+ lock {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0 1>;
+ lut = "Not Locked", "Locked";
+ };
+ OpCode {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 1 4>;
+ lut = "RD: data read with incrementing address",
+ "RDW: data read with wrapping address",
+ "RDL: allocates monitor in the Target with incrementing address",
+ "RDX: exclusive read with incrementing address",
+ "WR: data write with incrementing address",
+ "WRW: data write with wrapping address",
+ "WRC: conditional write if matching monitor in Target is found",
+ "RSV: reserved",
+ "PRE: preamble packet of linked sequence (locked sequence)",
+ "URG: urgency packet used for QoS (status must be REQ)";
+ };
+ ErrCode {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 8 3 >;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error",
+ "DEC (error source: Initiator NIU): decode error",
+ "UNS (error source: Target NIU): unsupported access type",
+ "DISC (error source: Power Disconnect): disconnected Target or NoC domain",
+ "SEC (error source: Initiator NIU or Firewall): security error",
+ "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator",
+ "TMO (error source: Target NIU): time-out",
+ "RSV: reserved";
+
+ };
+ Len1 {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 16 12 >;
+ };
+ Format {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 31 1 >;
+ lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid";
+ offset,length = < 0x18 32>;
+ description = "Register 1 to log errors";
+ InitFlow {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 19 4 >;
+ lut =
+ "aon_snoc_sp0/I/0",
+ "dspt_snoc/I/0",
+ "jtag_snoc/I/0",
+ "mcput_snoc_d2d/I/0",
+ "mcput_snoc_mp/I/0",
+ "mcput_snoc_sp0/I/0",
+ "mcput_snoc_sp1/I/0",
+ "mnoc_snoc/I/0",
+ "npu_snoc_sp0/I/0",
+ "npu_snoc_sp1/I/0",
+ "pciet_snoc_p/I/0",
+ "rnoc_snoc/I/0",
+ "spislv_tbu3_snoc/I/0",
+ "tbu4_snoc/I/0",
+ "tcu_snoc/I/0",
+ "RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 15 4 >;
+ lut =
+ "snoc_aon/T/0",
+ "snoc_cnoc/T/0",
+ "snoc_ddrt0_p1/T/0",
+ "snoc_ddrt0_p2/T/0",
+ "snoc_ddrt1_p1/T/0",
+ "snoc_ddrt1_p2/T/0",
+ "snoc_dspt/T/0",
+ "snoc_lnoc/T/0",
+ "snoc_mcput_d2d/T/0",
+ "snoc_mnoc/T/0",
+ "snoc_npu/T/0",
+ "snoc_pciet/T/0",
+ "snoc_rnoc/T/0",
+ "snoc_service/T/0",
+ "RESERVED1",
+ "RESERVED2";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 9 6 >;
+ };
+
+ SeqId {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 0 9 >;
+ };
+ };
+
+ ErrorLogger3 {
+ /* This register does not really include a bitfield or its bitfield is 32 bits and it provides an offset address */
+ /* To calculate the absolute address, you must use the initflow:targetflow:subrange from ErrorLogger1 register */
+ /* And use it as an index in the aperture table. Then you must add the value of this register to the value given */
+ /* by the table to get the absolute address. */
+ compatible = "eswin,eic7700,register";
+ offset,length = <0x20 32>;
+ description = "Register 3 to log errors";
+ aperture-link = <1>; /* link to ErrorLogger whose information are required to calculate real absolute address */
+ msb-link = <4>; /*indicate which ErrorLogger contains the msb addrs, -1 means no*/
+ AbsoluteAddress {
+ compatible = "eswin,eic7700,bitfield";
+ offset,length = < 9 14 >; /* bitfield initflow:targeflow:subrange from aperture-link register */
+ aperture-size= < 1181 >; /* Number of line in the aperture table below */
+ aperture-idx,aperture-base = /* Aperture_idx is concatenation of initflow:targetflow:subrange bitfield from ErrorLogger1 */
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
+ /bits/ 64 ,
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+ /bits/ 64 ,
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+ /bits/ 64