diff --git a/bsp/corev_uvmt.h b/bsp/corev_uvmt.h index d7022b3ca..94d73856d 100644 --- a/bsp/corev_uvmt.h +++ b/bsp/corev_uvmt.h @@ -25,25 +25,27 @@ #define CV_VP_REGISTER_BASE 0x00800000 -#define CV_VP_VIRTUAL_PRINTER_OFFSET 0x00000000 -#define CV_VP_RANDOM_NUM_OFFSET 0x00000040 -#define CV_VP_CYCLE_COUNTER_OFFSET 0x00000080 -#define CV_VP_STATUS_FLAGS_OFFSET 0x000000c0 -#define CV_VP_FENCEI_TAMPER_OFFSET 0x00000100 -#define CV_VP_INTR_TIMER_OFFSET 0x00000140 -#define CV_VP_DEBUG_CONTROL_OFFSET 0x00000180 -#define CV_VP_OBI_SLV_RESP_OFFSET 0x000001c0 -#define CV_VP_SIG_WRITER_OFFSET 0x00000200 +#define CV_VP_VIRTUAL_PRINTER_OFFSET 0x00000000 +#define CV_VP_RANDOM_NUM_OFFSET 0x00000040 +#define CV_VP_CYCLE_COUNTER_OFFSET 0x00000080 +#define CV_VP_STATUS_FLAGS_OFFSET 0x000000c0 +#define CV_VP_FENCEI_TAMPER_OFFSET 0x00000100 +#define CV_VP_INTR_TIMER_OFFSET 0x00000140 +#define CV_VP_DEBUG_CONTROL_OFFSET 0x00000180 +#define CV_VP_OBI_SLV_RESP_OFFSET 0x000001c0 +#define CV_VP_SIG_WRITER_OFFSET 0x00000200 +#define CV_VP_OBI_ERR_AWAIT_GOAHEAD_OFFSET 0x00000240 -#define CV_VP_VIRTUAL_PRINTER_BASE (CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET) -#define CV_VP_RANDOM_NUM_BASE (CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET) -#define CV_VP_CYCLE_COUNTER_BASE (CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET) -#define CV_VP_STATUS_FLAGS_BASE (CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET) -#define CV_VP_INTR_TIMER_BASE (CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET) -#define CV_VP_DEBUG_CONTROL_BASE (CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET) -#define CV_VP_OBI_SLV_RESP_BASE (CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET) -#define CV_VP_SIG_WRITER_BASE (CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET) -#define CV_VP_FENCEI_TAMPER_BASE (CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET) +#define CV_VP_CYCLE_COUNTER_BASE (CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET) +#define CV_VP_DEBUG_CONTROL_BASE (CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET) +#define CV_VP_FENCEI_TAMPER_BASE (CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET) +#define CV_VP_INTR_TIMER_BASE (CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET) +#define CV_VP_OBI_ERR_AWAIT_GOAHEAD_BASE (CV_VP_REGISTER_BASE + CV_VP_OBI_ERR_AWAIT_GOAHEAD_OFFSET) +#define CV_VP_OBI_SLV_RESP_BASE (CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET) +#define CV_VP_RANDOM_NUM_BASE (CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET) +#define CV_VP_SIG_WRITER_BASE (CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET) +#define CV_VP_STATUS_FLAGS_BASE (CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET) +#define CV_VP_VIRTUAL_PRINTER_BASE (CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET) // -------------------------------------------------------------------------- // Registers inside the OBI_SLV_RESP VP diff --git a/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv b/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv index 4ebef3b9c..715c024e6 100644 --- a/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv +++ b/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv @@ -153,7 +153,7 @@ Note: Deprioritize as this is furthest from ratification ",cm.jt,jump via table without link,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems,Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems,Check against ISS,Directed Non-Self-Checking,Testcase,DTC: zcmt_test,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,cm.jalt,jump via table and link to ra,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, diff --git a/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json b/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json index 40230e39d..b58b9d3ce 100644 --- a/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json +++ b/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json @@ -656,7 +656,7 @@ "Pass/Fail Criteria": "Check against ISS", "Test Type": "Directed Non-Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "Coverage hole, evaluate priority", + "Link to Coverage": "DTC: zcmt_test", "": "" }, { diff --git a/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx b/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx index 18948feb0..c1dccad20 100644 Binary files a/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx and b/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx differ diff --git a/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv b/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv index ff2ed0e20..5c9e6559a 100644 --- a/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv +++ b/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv @@ -58,7 +58,7 @@ CLIC 8675ec,Interrupt CSR,mtvt,"Function ptr reads treated as instruction fetch, Note, instruction fetch is treated as an implicit read, thus do not require PMP read permissions, but execute permission is required. -Both the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ",Assertion Check,"ENV capability, not specific test",Functional Coverage,TODO: Directed clic test should add case to test this +Both the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ",Assertion Check,"ENV capability, not specific test",Functional Coverage,"clic::invalid_mtvt_ptr_exec_mret, minhv_pma_block.c" UM v0.3.0 Common,Interrupt CSR,mtvt,"Always aligned to 2^(max(6, 2+SMCLIC_ID_WIDTH)","Assert that mtvt [max(6, 2+SMCLIC_ID_WIDTH)-1:0] = 0",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mtvt_alignment_correct CLIC 8675ec,Interrupt CSR,mtvt,"Determine alignment by software access, Write ones to lower order bits and read back",Test that correct alignment can be inferred by writing to these fields and read back.,Self Checking Test,Directed Self-Checking,Testcase,clic :: w_mtvt_rd_alignment diff --git a/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json b/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json index 8eda35f47..ed0491458 100644 --- a/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json +++ b/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json @@ -338,7 +338,7 @@ "Pass/Fail Criteria": "Assertion Check", "Test Type": "ENV capability, not specific test", "Coverage Method": "Functional Coverage", - "Link to Coverage": "TODO: Directed clic test should add case to test this" + "Link to Coverage": "clic::invalid_mtvt_ptr_exec_mret, minhv_pma_block.c" }, { "Requirement Location": "UM v0.3.0 Common", diff --git a/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx b/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx index 49e6523ea..9af84b660 100644 Binary files a/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx and b/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx differ diff --git a/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv b/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv index b73b1938c..55569d0bc 100644 --- a/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv +++ b/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv @@ -319,7 +319,7 @@ COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cro COV: *.pma_cov_instr_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_allow_jvt_*","TODO missing random test? Note: This is not maximally comprehensive, but the modelling that would otherwise be required is disproportionately complex." -Zce spec. proposal,,,"Instruction fetch exceptions occurring when executing an address in the jump table should lead to mepc being set to the C.TBLJ* instruction, and mtval to the address in the jump table entry",Verify that an instruction fetch exception resulting from a jump table entry leads to mepc being set to the C.TBLJ* instruction and mtval to the address in the jump table entry.,Self Checking Test,Directed Self-Checking,Testcase,DTC: TODO,TODO missing directed test? +Zce spec. proposal,,,"Instruction fetch exceptions occurring when executing an address in the jump table should lead to mepc being set to the C.TBLJ* instruction, and mtval to the address in the jump table entry",Verify that an instruction fetch exception resulting from a jump table entry leads to mepc being set to the C.TBLJ* instruction and mtval to the address in the jump table entry.,Self Checking Test,Directed Self-Checking,Testcase,Covered in Zc verif plan, Risc-V Debug spec.,Debug mode,Single step PMA exceptions,"Any instruction fetch exception that occurs while single stepping, causes debug mode to be re-entered after PC is changed to the exception handler and the appropriate tval and cause registers are updated","Verify that instruction fetches to PMA IO regions fails, the appropriate CSRs and PC is updated to the appropriate values and debug mode is reentered. ",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma_debug/, ,,Program buffer PMA exceptions,Exceptions in the program buffer should cause the program buffer code to end and cmderr set to 3 (exception error),"Verify that program buffer code attempting to fetch instructions from PMA IO region fails, PC is set to dm_exception_addr_i and cmderr is set to 3 (exception error). No other registers should be changed due to this exception.",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma_debug/, 40s UM 0.8.0,DebugRange,DebugRange,"""CV32E40S overrules the PMA and PMP settings for the Debug Module region when it is in debug mode""","Attempt access within/outside the dm region, in both dmode/not, check that the combo within/dmode never gets blocked and that the other combos follow the ordinary rules.",Assertion Check,Constrained-Random,Code Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_dm_region diff --git a/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json b/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json index 15f4039e8..44b443062 100644 --- a/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json +++ b/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json @@ -692,8 +692,8 @@ "Pass/Fail Criteria": "Self Checking Test", "Test Type": "Directed Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "DTC: TODO", - "Comment": "TODO missing directed test?" + "Link to Coverage": "Covered in Zc verif plan", + "Comment": "" }, { "Requirement Location": "Risc-V Debug spec.", diff --git a/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx b/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx index d65209864..2728600b5 100644 Binary files a/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx and b/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx differ diff --git a/env/corev-dv/cv32e40x_asm_program_gen.sv b/env/corev-dv/cv32e40x_asm_program_gen.sv index a1688f4ad..c99fd63d6 100644 --- a/env/corev-dv/cv32e40x_asm_program_gen.sv +++ b/env/corev-dv/cv32e40x_asm_program_gen.sv @@ -19,17 +19,19 @@ //----------------------------------------------------------------------------------------- // CV32E40X CORE-V assembly program generator - extension of the RISC-V assembly program generator. // -// Overrides gen_program_header() and gen_test_done() +// Overrides gen_program_header() and gen_test_done() and other riscv-dv functions. //----------------------------------------------------------------------------------------- class cv32e40x_asm_program_gen extends corev_asm_program_gen; `uvm_object_utils(cv32e40x_asm_program_gen) + function new (string name = ""); super.new(name); endfunction + virtual function void gen_program_header(); string instr[]; cv32e40x_instr_gen_config corev_cfg; @@ -164,6 +166,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("trap_vec_init", hart), instr); endfunction : trap_vector_init + virtual function void gen_illegal_instr_handler(int hart); string instr[$]; string load_instr = (XLEN == 32) ? "lw" : "ld"; @@ -206,6 +209,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("illegal_instr_handler", hart), instr); endfunction + virtual function void gen_instr_fault_handler(int hart); string instr[$]; string load_instr = (XLEN == 32) ? "lw" : "ld"; @@ -243,6 +247,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("instr_fault_handler", hart), instr); endfunction + // TODO: handshake correct csr based on delegation virtual function void gen_load_fault_handler(int hart); string instr[$]; @@ -264,6 +269,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("load_fault_handler", hart), instr); endfunction + // TODO: handshake correct csr based on delegation virtual function void gen_store_fault_handler(int hart); string instr[$]; @@ -284,6 +290,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("store_fault_handler", hart), instr); endfunction + virtual function void gen_interrupt_vector_table(int hart, string mode, privileged_reg_t status, @@ -355,6 +362,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; end endfunction : gen_interrupt_vector_table + // Setup EPC before entering target privileged mode virtual function void setup_epc(int hart); string instr[$]; @@ -373,6 +381,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("mepc_setup", hart), instr); endfunction + // Interrupt handler routine // Override from risc-dv: // 1. Remove MIP read, since interrupts are auto-cleared, mip will not track through the ISS @@ -527,6 +536,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; endfunction : gen_interrupt_handler_section + // Override gen_stack_section to add debugger stack generation section // Implmeneted as a post-step to super.gen_stack_section() virtual function void gen_stack_section(int hart); @@ -546,6 +556,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; endfunction : gen_stack_section + // Override of init_gpr to remove cfg.dp from initiailization if a debug section is generated virtual function void init_gpr(); string str; @@ -571,6 +582,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; end endfunction + // generate NMI handler. // will be placed at a fixed address in memory, set in linker file virtual function void gen_nmi_handler_section(int hart); @@ -598,8 +610,10 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; nmi_handler_instr); endfunction : gen_nmi_handler_section + virtual function void gen_section(string label, string instr[$]); string str; + if(label == "mtvec_handler" && cfg.mtvec_mode == VECTORED) begin str = ".section .mtvec_handler, \"ax\""; instr_stream.push_back(str); @@ -609,6 +623,7 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; str = format_string($sformatf("%0s:", label), LABEL_STR_LEN); instr_stream.push_back(str); end + foreach(instr[i]) begin str = {indent, instr[i]}; instr_stream.push_back(str); @@ -618,7 +633,25 @@ class cv32e40x_asm_program_gen extends corev_asm_program_gen; instr_stream.push_back(str); end end + instr_stream.push_back(""); endfunction : gen_section + + virtual function void gen_init_section(int hart); + string instrs[]; + string label; + + super.gen_init_section(hart); + + // After the "init" section, bus errors can safely occur without havoc + label = get_label("obi_err_goahead", hart); + instrs = { + $sformatf("li x%0d, 0x%08x", cfg.gpr[0], CV_VP_OBI_ERR_AWAIT_GOAHEAD_BASE), + $sformatf("sw x0, 0(x%0d)", cfg.gpr[0]) + }; + gen_section(label, instrs); + endfunction + + endclass : cv32e40x_asm_program_gen diff --git a/env/uvme/uvme_cv32e40x_cfg.sv b/env/uvme/uvme_cv32e40x_cfg.sv index 18f833390..d49901c5b 100644 --- a/env/uvme/uvme_cv32e40x_cfg.sv +++ b/env/uvme/uvme_cv32e40x_cfg.sv @@ -29,18 +29,20 @@ class uvme_cv32e40x_cfg_c extends uvma_core_cntrl_cfg_c; rand int unsigned sys_clk_period; cv32e40x_pkg::b_ext_e b_ext; cv32e40x_pkg::a_ext_e a_ext; - bit obi_memory_instr_random_err_enabled = 0; - bit obi_memory_instr_one_shot_err_enabled = 0; - bit obi_memory_data_random_err_enabled = 0; - bit obi_memory_data_one_shot_err_enabled = 0; - bit iss_suppress_invalid_msg = 0; - bit nmi_timeout_instr_plusarg_valid = 0; - bit irq_min_limit_plusarg_valid = 0; - bit single_step_min_limit_plusarg_valid = 0; - bit irq_single_step_threshold_plusarg_valid = 0; - bit clic_irq_clear_on_ack_plusarg_valid = 0; + bit obi_memory_data_one_shot_err_enabled = 0; + bit obi_memory_data_random_err_await_goahead = 0; + bit obi_memory_data_random_err_enabled = 0; + bit obi_memory_instr_one_shot_err_enabled = 0; + bit obi_memory_instr_random_err_await_goahead = 0; + bit obi_memory_instr_random_err_enabled = 0; + bit iss_suppress_invalid_msg = 0; + bit nmi_timeout_instr_plusarg_valid = 0; + bit irq_min_limit_plusarg_valid = 0; + bit single_step_min_limit_plusarg_valid = 0; + bit irq_single_step_threshold_plusarg_valid = 0; + bit clic_irq_clear_on_ack_plusarg_valid = 0; rand bit clic_irq_clear_on_ack; - rand bit buserr_scoreboarding_enabled = 1; + rand bit buserr_scoreboarding_enabled = 1; rand int unsigned fetch_toggle_initial_delay; rand int unsigned nmi_timeout_instr; rand int unsigned single_step_min_limit; @@ -61,24 +63,26 @@ class uvme_cv32e40x_cfg_c extends uvma_core_cntrl_cfg_c; rand uvma_pma_cfg_c#(ILEN,XLEN) pma_cfg; `uvm_object_utils_begin(uvme_cv32e40x_cfg_c) - `uvm_field_int ( enabled, UVM_DEFAULT ) - `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT ) - `uvm_field_int ( cov_model_enabled, UVM_DEFAULT ) - `uvm_field_int ( trn_log_enabled, UVM_DEFAULT ) - `uvm_field_int ( buserr_scoreboarding_enabled, UVM_DEFAULT ) - `uvm_field_int ( sys_clk_period, UVM_DEFAULT | UVM_DEC ) - `uvm_field_enum (b_ext_e, b_ext, UVM_DEFAULT ) - `uvm_field_enum (a_ext_e, a_ext, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_instr_random_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_instr_one_shot_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_data_random_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_data_one_shot_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( iss_suppress_invalid_msg, UVM_DEFAULT ) - `uvm_field_int ( fetch_toggle_initial_delay, UVM_DEFAULT ) - `uvm_field_int ( nmi_timeout_instr, UVM_DEFAULT | UVM_DEC ) - `uvm_field_int ( single_step_min_limit, UVM_DEFAULT | UVM_DEC ) - `uvm_field_int ( irq_min_limit, UVM_DEFAULT | UVM_DEC ) - `uvm_field_int ( irq_single_step_threshold, UVM_DEFAULT | UVM_DEC ) + `uvm_field_int ( enabled, UVM_DEFAULT ) + `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT ) + `uvm_field_int ( cov_model_enabled, UVM_DEFAULT ) + `uvm_field_int ( trn_log_enabled, UVM_DEFAULT ) + `uvm_field_int ( buserr_scoreboarding_enabled, UVM_DEFAULT ) + `uvm_field_int ( sys_clk_period, UVM_DEFAULT | UVM_DEC ) + `uvm_field_enum(b_ext_e, b_ext, UVM_DEFAULT ) + `uvm_field_enum(a_ext_e, a_ext, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_data_one_shot_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_data_random_err_await_goahead, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_data_random_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_instr_one_shot_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_instr_random_err_await_goahead,UVM_DEFAULT ) + `uvm_field_int ( obi_memory_instr_random_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( iss_suppress_invalid_msg, UVM_DEFAULT ) + `uvm_field_int ( fetch_toggle_initial_delay, UVM_DEFAULT ) + `uvm_field_int ( nmi_timeout_instr, UVM_DEFAULT | UVM_DEC ) + `uvm_field_int ( single_step_min_limit, UVM_DEFAULT | UVM_DEC ) + `uvm_field_int ( irq_min_limit, UVM_DEFAULT | UVM_DEC ) + `uvm_field_int ( irq_single_step_threshold, UVM_DEFAULT | UVM_DEC ) `uvm_field_object(isacov_cfg , UVM_DEFAULT) `uvm_field_object(clknrst_cfg , UVM_DEFAULT) @@ -334,6 +338,19 @@ class uvme_cv32e40x_cfg_c extends uvma_core_cntrl_cfg_c; obi_memory_data_cfg.drv_slv_err_one_shot_mode == obi_memory_data_one_shot_err_enabled; } + + constraint obi_memory_data_random_err_await_goahead_cons { + if (obi_memory_data_random_err_await_goahead) { + obi_memory_data_cfg.random_err_await_goahead == 1; + } + } + + constraint obi_memory_instr_random_err_await_goahead_cons { + if (obi_memory_instr_random_err_await_goahead) { + obi_memory_instr_cfg.random_err_await_goahead == 1; + } + } + /** * Creates sub-configuration objects. */ @@ -377,13 +394,18 @@ function uvme_cv32e40x_cfg_c::new(string name="uvme_cv32e40x_cfg"); core_name = "CV32E40X"; + + // Read Plusargs + if ($test$plusargs("USE_ISS")) begin use_iss = 1; end + if ($test$plusargs("trn_log_disabled")) begin trn_log_enabled = 0; trn_log_enabled.rand_mode(0); end + if ($test$plusargs("buserr_sb_disabled")) begin buserr_scoreboarding_enabled = 0; buserr_scoreboarding_enabled.rand_mode(0); @@ -392,27 +414,42 @@ function uvme_cv32e40x_cfg_c::new(string name="uvme_cv32e40x_cfg"); if ($test$plusargs("obi_memory_instr_random_err")) begin obi_memory_instr_random_err_enabled = 1; end + if ($test$plusargs("obi_memory_instr_one_shot_err")) begin obi_memory_instr_one_shot_err_enabled = 1; end + if ($test$plusargs("obi_memory_data_random_err")) begin obi_memory_data_random_err_enabled = 1; end + + if ($test$plusargs("obi_memory_data_random_err_await_goahead")) begin + obi_memory_data_random_err_await_goahead = 1; + end + + if ($test$plusargs("obi_memory_instr_random_err_await_goahead")) begin + obi_memory_instr_random_err_await_goahead = 1; + end + if ($test$plusargs("obi_memory_data_one_shot_err")) begin obi_memory_data_one_shot_err_enabled = 1; end + if ($value$plusargs("nmi_timeout_instr=%d", nmi_timeout_instr)) begin nmi_timeout_instr_plusarg_valid = 1; nmi_timeout_instr.rand_mode(0); end + if ($value$plusargs("irq_single_step_threshold=%0d", irq_single_step_threshold)) begin irq_single_step_threshold_plusarg_valid = 1; irq_single_step_threshold.rand_mode(0); end + if ($value$plusargs("irq_min_limit=%0d", irq_min_limit)) begin irq_min_limit_plusarg_valid = 1; irq_min_limit.rand_mode(0); end + if ($value$plusargs("single_step_min_limit=%0d", single_step_min_limit)) begin single_step_min_limit_plusarg_valid = 1; single_step_min_limit.rand_mode(0); @@ -429,6 +466,8 @@ function uvme_cv32e40x_cfg_c::new(string name="uvme_cv32e40x_cfg"); end + // Create Configs + isacov_cfg = uvma_isacov_cfg_c::type_id::create("isacov_cfg"); clknrst_cfg = uvma_clknrst_cfg_c::type_id::create("clknrst_cfg"); interrupt_cfg = uvma_interrupt_cfg_c::type_id::create("interrupt_cfg"); @@ -442,6 +481,8 @@ function uvme_cv32e40x_cfg_c::new(string name="uvme_cv32e40x_cfg"); pma_cfg = uvma_pma_cfg_c#(ILEN,XLEN)::type_id::create("pma_cfg"); + // Assign loggers and configs + obi_memory_instr_cfg.mon_logger_name = "OBII"; obi_memory_data_cfg.mon_logger_name = "OBID"; diff --git a/env/uvme/uvme_cv32e40x_env.sv b/env/uvme/uvme_cv32e40x_env.sv index d2a7fbb88..aa6d71a1b 100644 --- a/env/uvme/uvme_cv32e40x_env.sv +++ b/env/uvme/uvme_cv32e40x_env.sv @@ -762,6 +762,37 @@ function void uvme_cv32e40x_env_c::install_vp_register_seqs(uvma_obi_memory_slv_ vp_seq.cv32e40x_cntxt = cntxt; end + begin + uvma_obi_memory_vp_base_seq_c#( + .ACHK_WIDTH (ENV_PARAM_DATA_ACHK_WIDTH), + .ADDR_WIDTH (ENV_PARAM_DATA_ADDR_WIDTH), + .AUSER_WIDTH (ENV_PARAM_DATA_AUSER_WIDTH), + .DATA_WIDTH (ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH (ENV_PARAM_DATA_ID_WIDTH), + .RCHK_WIDTH (ENV_PARAM_DATA_RCHK_WIDTH), + .RUSER_WIDTH (ENV_PARAM_DATA_RUSER_WIDTH), + .WUSER_WIDTH (ENV_PARAM_DATA_WUSER_WIDTH) + ) new_created_base_seq; + + uvme_cv32e40s_vp_obi_err_await_goahead_seq_c casted_seq_handle; + + new_created_base_seq = data_slv_seq.register_vp_vseq( + "vp_obi_err_await_goahead", + CV_VP_OBI_ERR_AWAIT_GOAHEAD_BASE, + uvme_cv32e40s_vp_obi_err_await_goahead_seq_c::get_type() + ); + + if (!$cast(casted_seq_handle, new_created_base_seq)) begin + `uvm_fatal( + "CV32E40SVPSEQ", + $sformatf("Could not cast/assign vp_obi_err_await_goahead") + ); + end + + casted_seq_handle.obi_memory_cfg_instr = cfg.obi_memory_instr_cfg; + casted_seq_handle.obi_memory_cfg_data = cfg.obi_memory_data_cfg; + end + endfunction : install_vp_register_seqs `endif // __UVME_CV32E40X_ENV_SV__ diff --git a/env/uvme/uvme_cv32e40x_pkg.sv b/env/uvme/uvme_cv32e40x_pkg.sv index 13b652bf1..33d042cab 100644 --- a/env/uvme/uvme_cv32e40x_pkg.sv +++ b/env/uvme/uvme_cv32e40x_pkg.sv @@ -74,10 +74,11 @@ package uvme_cv32e40x_pkg; `include "uvme_cv32e40x_nmi_timeout_vseq.sv" `include "uvme_cv32e40x_irq_ss_timeout_vseq.sv" `include "uvme_cv32e40x_vp_debug_control_seq.sv" + `include "uvme_cv32e40x_vp_fencei_tamper_seq.sv" `include "uvme_cv32e40x_vp_interrupt_timer_seq.sv" + `include "uvme_cv32e40x_vp_obi_err_await_goahead_seq.sv" `include "uvme_cv32e40x_vp_sig_writer_seq.sv" `include "uvme_cv32e40x_vp_status_flags_seq.sv" - `include "uvme_cv32e40x_vp_fencei_tamper_seq.sv" `include "uvme_cv32e40x_interrupt_noise_vseq.sv" `include "uvme_cv32e40x_clic_noise_vseq.sv" `include "uvme_cv32e40x_vseq_lib.sv" diff --git a/env/uvme/vseq/uvme_cv32e40x_vp_obi_err_await_goahead_seq.sv b/env/uvme/vseq/uvme_cv32e40x_vp_obi_err_await_goahead_seq.sv new file mode 100644 index 000000000..8acbc0606 --- /dev/null +++ b/env/uvme/vseq/uvme_cv32e40x_vp_obi_err_await_goahead_seq.sv @@ -0,0 +1,59 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +class uvme_cv32e40s_vp_obi_err_await_goahead_seq_c + extends uvma_obi_memory_vp_base_seq_c #( + .AUSER_WIDTH (ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH (ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH (ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH (ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH (ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH (ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH (ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH (ENV_PARAM_DATA_RCHK_WIDTH) + ); + + `uvm_object_utils( uvme_cv32e40s_vp_obi_err_await_goahead_seq_c ) + + uvma_obi_memory_cfg_c obi_memory_cfg_instr; + uvma_obi_memory_cfg_c obi_memory_cfg_data; + + + function new(string name="uvme_cv32e40s_vp_obi_err_await_goahead_seq_c"); + super.new(name); + endfunction + + + function int unsigned get_num_words(); + return 1; + endfunction + + + virtual task vp_body(uvma_obi_memory_mon_trn_c mon_trn); + uvma_obi_memory_slv_seq_item_c slv_rsp; + + obi_memory_cfg_instr.random_err_await_goahead = 0; + obi_memory_cfg_data.random_err_await_goahead = 0; + + `uvm_create(slv_rsp) + `uvm_send(slv_rsp) + endtask + + +endclass diff --git a/regress/cv32e40x_full.yaml b/regress/cv32e40x_full.yaml index 281b09a64..abc6ef561 100644 --- a/regress/cv32e40x_full.yaml +++ b/regress/cv32e40x_full.yaml @@ -548,3 +548,10 @@ tests: builds: [ uvmt_cv32e40x_clic ] dir: cv32e40x/sim/uvmt cmd: make test TEST=mhpmcounter3_dcsr_stopcount + + minhv_pma_block: + description: test minhv=1 and pma block of mepc address + builds: [ uvmt_cv32e40x_pma_2 ] + dir: cv32e40x/sim/uvmt + cmd: make test TEST=minhv_pma_block + diff --git a/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv b/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv index efadb6b15..29663524d 100644 --- a/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv +++ b/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv @@ -53,9 +53,8 @@ module uvmt_cv32e40x_dut_wrap uvma_interrupt_if_t interrupt_if, uvma_clic_if_t clic_if, uvma_wfe_wu_if_t wfe_wu_if, - uvme_cv32e40x_core_cntrl_if_t core_cntrl_if, - uvmt_cv32e40x_core_status_if_t core_status_if, uvmt_cv32e40x_vp_status_if_t vp_status_if, + uvme_cv32e40x_core_cntrl_if_t core_cntrl_if, uvma_obi_memory_if_t obi_instr_if, uvma_obi_memory_if_t obi_data_if, uvma_fencei_if_t fencei_if @@ -168,7 +167,7 @@ module uvmt_cv32e40x_dut_wrap .debug_pc_o ( debug_pc ), .fetch_enable_i ( core_cntrl_if.fetch_en ), - .core_sleep_o ( core_status_if.core_busy ) + .core_sleep_o () ); endmodule : uvmt_cv32e40x_dut_wrap diff --git a/tb/uvmt/uvmt_cv32e40x_tb.sv b/tb/uvmt/uvmt_cv32e40x_tb.sv index 070ed6f5c..f884b6518 100644 --- a/tb/uvmt/uvmt_cv32e40x_tb.sv +++ b/tb/uvmt/uvmt_cv32e40x_tb.sv @@ -84,8 +84,6 @@ module uvmt_cv32e40x_tb; .exit_valid(), .exit_value()); // Status information generated by the Virtual Peripherals in the DUT WRAPPER memory. uvme_cv32e40x_core_cntrl_if_t core_cntrl_if(); - uvmt_cv32e40x_core_status_if_t core_status_if(.core_busy(), - .sec_lvl()); // Core status outputs // RVVI SystemVerilog Interface `ifndef FORMAL @@ -105,7 +103,6 @@ module uvmt_cv32e40x_tb; .interrupt_if (interrupt_if), .vp_status_if (vp_status_if), .core_cntrl_if (core_cntrl_if), - .core_status_if (core_status_if), .obi_instr_if (obi_instr_if), .obi_data_if (obi_data_if), .fencei_if (fencei_if), @@ -171,52 +168,55 @@ module uvmt_cv32e40x_tb; // "rvfi_instr_if" bind cv32e40x_wrapper - uvma_rvfi_instr_if_t#(uvmt_cv32e40x_base_test_pkg::ILEN, - uvmt_cv32e40x_base_test_pkg::XLEN) rvfi_instr_if(.clk(clk_i), - .reset_n(rst_ni), - - .rvfi_valid(rvfi_i.rvfi_valid[0]), - .rvfi_order(rvfi_i.rvfi_order[uvma_rvfi_pkg::ORDER_WL*0+:uvma_rvfi_pkg::ORDER_WL]), - .rvfi_insn(rvfi_i.rvfi_insn[uvmt_cv32e40x_base_test_pkg::ILEN*0+:uvmt_cv32e40x_base_test_pkg::ILEN]), - .rvfi_trap(rvfi_i.rvfi_trap), - .rvfi_halt(rvfi_i.rvfi_halt[0]), - .rvfi_intr(rvfi_i.rvfi_intr), - .rvfi_dbg(rvfi_i.rvfi_dbg), - .rvfi_dbg_mode(rvfi_i.rvfi_dbg_mode), - .rvfi_nmip(rvfi_i.rvfi_nmip), - .rvfi_mode(rvfi_i.rvfi_mode[uvma_rvfi_pkg::MODE_WL*0+:uvma_rvfi_pkg::MODE_WL]), - .rvfi_ixl(rvfi_i.rvfi_ixl[uvma_rvfi_pkg::IXL_WL*0+:uvma_rvfi_pkg::IXL_WL]), - .rvfi_pc_rdata(rvfi_i.rvfi_pc_rdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_pc_wdata(rvfi_i.rvfi_pc_wdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_rs1_addr(rvfi_i.rvfi_rs1_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rs1_rdata(rvfi_i.rvfi_rs1_rdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_rs2_addr(rvfi_i.rvfi_rs2_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rs2_rdata(rvfi_i.rvfi_rs2_rdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_rs3_addr('0), - .rvfi_rs3_rdata('0), - .rvfi_rd1_addr(rvfi_i.rvfi_rd_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rd1_wdata(rvfi_i.rvfi_rd_wdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_rd2_addr('0), - .rvfi_rd2_wdata('0), - .rvfi_gpr_rdata(rvfi_i.rvfi_gpr_rdata[32*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_gpr_rmask(rvfi_i.rvfi_gpr_rmask[32*0 +:32]), - .rvfi_gpr_wdata(rvfi_i.rvfi_gpr_wdata[32*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_gpr_wmask(rvfi_i.rvfi_gpr_wmask[32*0 +:32]), - .rvfi_mem_addr(rvfi_i.rvfi_mem_addr[ uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_mem_rdata(rvfi_i.rvfi_mem_rdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_mem_rmask(rvfi_i.rvfi_mem_rmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8]), - .rvfi_mem_wdata(rvfi_i.rvfi_mem_wdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN]), - .rvfi_mem_wmask(rvfi_i.rvfi_mem_wmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8]), - .rvfi_instr_prot(rvfi_i.rvfi_instr_prot), - .rvfi_instr_memtype(rvfi_i.rvfi_instr_memtype), - .rvfi_instr_dbg(rvfi_i.rvfi_instr_dbg), - .rvfi_mem_prot(rvfi_i.rvfi_mem_prot), - .rvfi_mem_exokay(rvfi_i.rvfi_mem_exokay), - .rvfi_mem_err(rvfi_i.rvfi_mem_err), - .rvfi_mem_atop(rvfi_i.rvfi_mem_atop), - .rvfi_mem_memtype(rvfi_i.rvfi_mem_memtype), - .rvfi_mem_dbg(rvfi_i.rvfi_mem_dbg) - ); + uvma_rvfi_instr_if_t#( + uvmt_cv32e40x_base_test_pkg::ILEN, + uvmt_cv32e40x_base_test_pkg::XLEN + ) rvfi_instr_if( + .clk (clk_i), + .reset_n (rst_ni), + + .rvfi_valid (rvfi_i.rvfi_valid[0]), + .rvfi_order (rvfi_i.rvfi_order[uvma_rvfi_pkg::ORDER_WL*0+:uvma_rvfi_pkg::ORDER_WL]), + .rvfi_insn (rvfi_i.rvfi_insn[uvmt_cv32e40x_base_test_pkg::ILEN*0+:uvmt_cv32e40x_base_test_pkg::ILEN]), + .rvfi_trap (rvfi_i.rvfi_trap), + .rvfi_halt (rvfi_i.rvfi_halt[0]), + .rvfi_intr (rvfi_i.rvfi_intr), + .rvfi_dbg (rvfi_i.rvfi_dbg), + .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), + .rvfi_nmip (rvfi_i.rvfi_nmip), + .rvfi_mode (rvfi_i.rvfi_mode[uvma_rvfi_pkg::MODE_WL*0+:uvma_rvfi_pkg::MODE_WL]), + .rvfi_ixl (rvfi_i.rvfi_ixl[uvma_rvfi_pkg::IXL_WL*0+:uvma_rvfi_pkg::IXL_WL]), + .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_pc_wdata (rvfi_i.rvfi_pc_wdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_rs1_addr (rvfi_i.rvfi_rs1_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), + .rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_rs2_addr (rvfi_i.rvfi_rs2_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), + .rvfi_rs2_rdata (rvfi_i.rvfi_rs2_rdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_rs3_addr ('0), + .rvfi_rs3_rdata ('0), + .rvfi_rd1_addr (rvfi_i.rvfi_rd_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), + .rvfi_rd1_wdata (rvfi_i.rvfi_rd_wdata[uvmt_cv32e40x_base_test_pkg::XLEN*0+:uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_rd2_addr ('0), + .rvfi_rd2_wdata ('0), + .rvfi_gpr_rdata (rvfi_i.rvfi_gpr_rdata[32*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_gpr_rmask (rvfi_i.rvfi_gpr_rmask[32*0 +:32]), + .rvfi_gpr_wdata (rvfi_i.rvfi_gpr_wdata[32*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_gpr_wmask (rvfi_i.rvfi_gpr_wmask[32*0 +:32]), + .rvfi_mem_addr (rvfi_i.rvfi_mem_addr[ uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_mem_rdata (rvfi_i.rvfi_mem_rdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_mem_rmask (rvfi_i.rvfi_mem_rmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8]), + .rvfi_mem_wdata (rvfi_i.rvfi_mem_wdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN]), + .rvfi_mem_wmask (rvfi_i.rvfi_mem_wmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40x_base_test_pkg::XLEN/8]), + .rvfi_instr_prot (rvfi_i.rvfi_instr_prot), + .rvfi_instr_memtype (rvfi_i.rvfi_instr_memtype), + .rvfi_instr_dbg (rvfi_i.rvfi_instr_dbg), + .rvfi_mem_prot (rvfi_i.rvfi_mem_prot), + .rvfi_mem_exokay (rvfi_i.rvfi_mem_exokay), + .rvfi_mem_err (rvfi_i.rvfi_mem_err), + .rvfi_mem_atop (rvfi_i.rvfi_mem_atop), + .rvfi_mem_memtype (rvfi_i.rvfi_mem_memtype), + .rvfi_mem_dbg (rvfi_i.rvfi_mem_dbg) + ); // RVFI CSR binds `RVFI_CSR_BIND(jvt) @@ -576,7 +576,6 @@ module uvmt_cv32e40x_tb; // Fence.i assertions - `ifndef COREV_ASSERT_OFF bind cv32e40x_wrapper uvmt_cv32e40x_fencei_assert #( @@ -597,7 +596,6 @@ module uvmt_cv32e40x_tb; ); `endif - // RVFI Asserts & Covers `ifndef COREV_ASSERT_OFF @@ -978,7 +976,6 @@ module uvmt_cv32e40x_tb; // Support Logic - bind cv32e40x_wrapper uvmt_cv32e40x_support_logic u_support_logic(.rvfi (rvfi_instr_if), .in_support_if (support_logic_module_i_if.driver_mp), .out_support_if (support_logic_module_o_if.master_mp), @@ -1012,7 +1009,6 @@ module uvmt_cv32e40x_tb; ); end : gen_rv32e_assert `endif - `ifndef COREV_ASSERT_OFF bind cv32e40x_wrapper uvmt_cv32e40x_triggers_assert_cov debug_trigger_assert_i( .tdata1_array (uvmt_cv32e40x_tb.tdata1_array), @@ -1239,7 +1235,6 @@ module uvmt_cv32e40x_tb; // Virtual Peripheral Status interface uvm_config_db#(virtual uvmt_cv32e40x_vp_status_if_t )::set(.cntxt(null), .inst_name("*"), .field_name("vp_status_vif"), .value(vp_status_if) ); uvm_config_db#(virtual uvme_cv32e40x_core_cntrl_if_t )::set(.cntxt(null), .inst_name("*"), .field_name("core_cntrl_vif"), .value(core_cntrl_if) ); - uvm_config_db#(virtual uvmt_cv32e40x_core_status_if_t )::set(.cntxt(null), .inst_name("*"), .field_name("core_status_vif"), .value(core_status_if) ); uvm_config_db#(virtual uvmt_cv32e40x_debug_cov_assert_if_t )::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"),.value(dut_wrap.cv32e40x_wrapper_i.debug_cov_assert_if)); uvm_config_db#(virtual uvmt_cv32e40x_support_logic_module_o_if_t )::set(.cntxt(null), .inst_name("*.env"), .field_name("support_logic_vif"),.value(dut_wrap.cv32e40x_wrapper_i.support_logic_module_o_if)); diff --git a/tests/cfg/pma_test_cfg_2.yaml b/tests/cfg/pma_test_cfg_2.yaml index 11a88b811..8c6491e3f 100644 --- a/tests/cfg/pma_test_cfg_2.yaml +++ b/tests/cfg/pma_test_cfg_2.yaml @@ -2,6 +2,7 @@ name: pma_test_cfg_2 description: PMA configuration for the PMA_TEST_CFG_2 test case compile_flags: > +define+PMA_TEST_CFG_2 + +define+CLIC_EN +define+ZBA_ZBB_ZBC_ZBS plusargs: > +enable_pma=1 diff --git a/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml b/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml index 467563d1e..ff832c3fe 100644 --- a/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml +++ b/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml @@ -5,6 +5,7 @@ description: > plusargs: > +random_fetch_toggle +obi_memory_data_random_err_enabled + +obi_memory_data_random_err_await_goahead +obi_memory_data_one_shot_err_enabled +gen_irq_noise +gen_random_debug diff --git a/tests/programs/custom/mhpmcounter_write_test/mhpmcounter_write_test.c b/tests/programs/custom/mhpmcounter_write_test/mhpmcounter_write_test.c index 5fe485438..1111a0355 100644 --- a/tests/programs/custom/mhpmcounter_write_test/mhpmcounter_write_test.c +++ b/tests/programs/custom/mhpmcounter_write_test/mhpmcounter_write_test.c @@ -241,4 +241,5 @@ int main() if (is_failure) return EXIT_FAILURE; return EXIT_SUCCESS; -} \ No newline at end of file +} + diff --git a/tests/programs/custom/mhpmcounter_write_test/test.yaml b/tests/programs/custom/mhpmcounter_write_test/test.yaml index c4c044f50..9f061158d 100644 --- a/tests/programs/custom/mhpmcounter_write_test/test.yaml +++ b/tests/programs/custom/mhpmcounter_write_test/test.yaml @@ -1,4 +1,4 @@ name: mhpmcounter_write_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > - Write to mhpmcounters. Is only verifyed by ISS, should be verifyed that we get excpected behaviour? \ No newline at end of file + Write to mhpmcounters. Is only verifyed by ISS, should be verifyed that we get excpected behaviour? diff --git a/tests/programs/custom/minhv_pma_block/minhv_pma_block.c b/tests/programs/custom/minhv_pma_block/minhv_pma_block.c new file mode 100644 index 000000000..cafc28a3f --- /dev/null +++ b/tests/programs/custom/minhv_pma_block/minhv_pma_block.c @@ -0,0 +1,172 @@ +// +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Kristine Døsvik +// +// Test minhv=1 and pma block of mepc address. +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include "bsp.h" + +#define RND_ADDRS_IN_PMA_CFG_2_IO_REGION 0xE0100010 + +extern volatile uint32_t recovery_pt_mret; +volatile uint32_t g_entered_trap_handler; +volatile uint32_t g_trapped_mcause; + +int execute_from_io_region(); +__attribute__((interrupt ("machine"))) void u_sw_irq_handler(void); +void trap_handler(void); + + +int main(int argc, char **argv){ + + int is_failure = 0; + + is_failure += execute_from_io_region(); + + if(is_failure){ + return EXIT_FAILURE; + } else { + return EXIT_SUCCESS; + } +} + + +int execute_from_io_region() { + + volatile uint32_t io_addr = RND_ADDRS_IN_PMA_CFG_2_IO_REGION; + volatile uint32_t mcause_excode = 0x0; + volatile uint32_t mcause_excode_expected = EXC_CAUSE_INSTR_ACC_FAULT; //Execution attempt from I/O region. + volatile uint32_t mret_dont_trap = 0; + volatile uint32_t test_fail = 0; + g_entered_trap_handler = 0; + + // Load an IO memory address into mepc + __asm__ volatile ( R"( + csrrw zero, mepc, %[io_addr] + )" :: [io_addr] "r"(io_addr)); + + // Set minhv and mpp = M + __asm__ volatile ( R"( + lui t0, 0x70000 + csrrs zero, mcause, t0 + )"::: "t0"); + + __asm__ volatile ( R"( + mret + )":::); + + // Mret traps. + + // This should never execute (deliberate dead code), as the mret make the pc take a jump + mret_dont_trap += 1; + + // Execution should continue here + __asm__ volatile ( R"( + .global recovery_pt_mret + recovery_pt_mret: add x0, x0, x0 + )":::); + + + mcause_excode = g_trapped_mcause & 0x7ff; + + printf("Mret traps: %08lx, expected: 1\n", g_entered_trap_handler); + printf("Mret dont trap: %08lx, expected: 0\n", mret_dont_trap); + printf("mcause excode: %08lx, expected: %08lx (execution attempt from I/O region).\n", mcause_excode, mcause_excode_expected); + test_fail += (g_entered_trap_handler != 1) || mret_dont_trap || (mcause_excode != mcause_excode_expected); + + printf("g_trapped_mcause: %08lx", g_trapped_mcause); + + return test_fail; +} + + +__attribute__((interrupt ("machine"))) +void u_sw_irq_handler(void) { + __asm__ volatile (R"( + # Backup all GPRs + sw a0, -4(sp) + sw a1, -8(sp) + sw a2, -12(sp) + sw a3, -16(sp) + sw a4, -20(sp) + sw a5, -24(sp) + sw a6, -28(sp) + sw a7, -32(sp) + sw t0, -36(sp) + sw t1, -40(sp) + sw t2, -44(sp) + sw t3, -48(sp) + sw t4, -52(sp) + sw t5, -56(sp) + sw t6, -60(sp) + addi sp, sp, -64 + cm.push {ra, s0-s11}, -64 + + # Call the handler actual + call ra, trap_handler + + # Restore all GPRs + cm.pop {ra, s0-s11}, 64 + addi sp, sp, 64 + lw a0, -4(sp) + lw a1, -8(sp) + lw a2, -12(sp) + lw a3, -16(sp) + lw a4, -20(sp) + lw a5, -24(sp) + lw a6, -28(sp) + lw a7, -32(sp) + lw t0, -36(sp) + lw t1, -40(sp) + lw t2, -44(sp) + lw t3, -48(sp) + lw t4, -52(sp) + lw t5, -56(sp) + lw t6, -60(sp) + + # Restore "sp" + # csrr sp, dscratch0 + + # Done + mret + )"); +} + +void trap_handler(void) { + + g_entered_trap_handler += 1; + + __asm__ volatile ( R"( + # Get recovery mepc and replace mepc + la t0, recovery_pt_mret + csrrw zero, mepc, t0 + + # read and clear mcause except mpp, which is set + 4: lui t0, 0x30000 + csrrw %[g_trapped_mcause], mcause, t0 + + )" : [g_trapped_mcause]"=r"(g_trapped_mcause) :: "t0"); + + return; +} + diff --git a/tests/programs/custom/minhv_pma_block/test.yaml b/tests/programs/custom/minhv_pma_block/test.yaml new file mode 100644 index 000000000..4f43e93d6 --- /dev/null +++ b/tests/programs/custom/minhv_pma_block/test.yaml @@ -0,0 +1,8 @@ +name: minhv_pma_block +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Use CFG=p,a_test_cfg_2. Test minhv=1 and pma block of mepc address +plusargs: > + +clic_irq_clear_on_ack=0 +cflags: > + -mno-relax diff --git a/tests/programs/custom/zc_test/zc_test.c b/tests/programs/custom/zc_test/zc_test.c index 3bac064f2..34c751b67 100644 --- a/tests/programs/custom/zc_test/zc_test.c +++ b/tests/programs/custom/zc_test/zc_test.c @@ -111,6 +111,17 @@ void m_external_irq_handler(void) { } +static void +test_mva01s_same_register(void) +{ + printf("test_mva01s_same_register: start\n"); + __asm__ volatile( + "cm.mva01s s2, s2" + : : : "s2" + ); + printf("test_mva01s_same_register: done\n"); +} + int main(int argc, char *argv[]) { @@ -120,10 +131,15 @@ int main(int argc, char *argv[]) test_instr_num = 0; + // Setup + printf("Enabling irq. \n"); enable_all_irq(); + + // Test: PushPop + printf("\n\nTesting push/pop instructions. \n"); test_active = pushpop; @@ -138,11 +154,13 @@ int main(int argc, char *argv[]) interrupt_push_pop(i); } + + // Test: Popret + printf("\n\nTesting popret instructions. \n"); test_active = popret; test_instr_num = 0; - for (int i = PUSH_RLIST_MIN; i <= PUSH_RLIST_MAX; i++) { glb_irq_line = 0x1 << EX_IRQ_LINE; @@ -154,11 +172,13 @@ int main(int argc, char *argv[]) interrupt_popret(i); } + + // Test: Popretz + printf("\n\nTesting popretz instructions. \n"); test_active = popretz; test_instr_num = 0; - for (int i = PUSH_RLIST_MIN; i <= PUSH_RLIST_MAX; i++) { glb_irq_line = 0x1 << EX_IRQ_LINE; @@ -171,6 +191,8 @@ int main(int argc, char *argv[]) } + // Test: Mvsa01 + printf("\n\nTesting mvsa01 instructions. \n"); test_active = mvsa; test_instr_num = 0; @@ -191,12 +213,18 @@ int main(int argc, char *argv[]) i = iteratorVault; } + + // Test: Mva01s + printf("\n\nTesting mva01s instructions. \n"); + test_active = mvas; test_instr_num = 0; + //creating random values for the target registers rnd0 = vp_random_num(0xFFFFFFFE, 0x0); rnd1 = vp_random_num(0xFFFFFFFE, 0x0); + for (int i = 0; i < MVAS_INSTR_SIZE; i++) { glb_irq_line = 0x1 << EX_IRQ_LINE; @@ -212,6 +240,13 @@ int main(int argc, char *argv[]) } + // Test: Mva01s - Same Register (Sanity check of RTL bugfix.) + + test_mva01s_same_register(); + + + // ErrorCheck & Exit + if(exp_irq != ex_traps_entered) { printf("\tERROR: %u interrupts taken, expected %u", (unsigned int)ex_traps_entered, (unsigned int)exp_irq); failureCount += 1; diff --git a/tests/uvmt/base-tests/uvmt_cv32e40x_base_test_constants.sv b/tests/uvmt/base-tests/uvmt_cv32e40x_base_test_constants.sv index 3da1b6564..77087ee7d 100644 --- a/tests/uvmt/base-tests/uvmt_cv32e40x_base_test_constants.sv +++ b/tests/uvmt/base-tests/uvmt_cv32e40x_base_test_constants.sv @@ -55,25 +55,27 @@ parameter PC_CHECKED_HEARTBEAT = 10_000; parameter CV_VP_REGISTER_BASE = 32'h0080_0000; parameter CV_VP_REGISTER_SIZE = 32'h0000_1000; -parameter CV_VP_VIRTUAL_PRINTER_OFFSET = 32'h0000_0000; -parameter CV_VP_RANDOM_NUM_OFFSET = 32'h0000_0040; -parameter CV_VP_CYCLE_COUNTER_OFFSET = 32'h0000_0080; -parameter CV_VP_STATUS_FLAGS_OFFSET = 32'h0000_00c0; -parameter CV_VP_FENCEI_TAMPER_OFFSET = 32'h0000_0100; -parameter CV_VP_INTR_TIMER_OFFSET = 32'h0000_0140; -parameter CV_VP_DEBUG_CONTROL_OFFSET = 32'h0000_0180; -parameter CV_VP_OBI_SLV_RESP_OFFSET = 32'h0000_01c0; -parameter CV_VP_SIG_WRITER_OFFSET = 32'h0000_0200; - -parameter CV_VP_VIRTUAL_PRINTER_BASE = CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET; -parameter CV_VP_RANDOM_NUM_BASE = CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET; -parameter CV_VP_CYCLE_COUNTER_BASE = CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET; -parameter CV_VP_STATUS_FLAGS_BASE = CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET; -parameter CV_VP_INTR_TIMER_BASE = CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET; -parameter CV_VP_DEBUG_CONTROL_BASE = CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET; -parameter CV_VP_OBI_SLV_RESP_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET; -parameter CV_VP_SIG_WRITER_BASE = CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET; -parameter CV_VP_FENCEI_TAMPER_BASE = CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET; +parameter CV_VP_VIRTUAL_PRINTER_OFFSET = 32'h0000_0000; +parameter CV_VP_RANDOM_NUM_OFFSET = 32'h0000_0040; +parameter CV_VP_CYCLE_COUNTER_OFFSET = 32'h0000_0080; +parameter CV_VP_STATUS_FLAGS_OFFSET = 32'h0000_00c0; +parameter CV_VP_FENCEI_TAMPER_OFFSET = 32'h0000_0100; +parameter CV_VP_INTR_TIMER_OFFSET = 32'h0000_0140; +parameter CV_VP_DEBUG_CONTROL_OFFSET = 32'h0000_0180; +parameter CV_VP_OBI_SLV_RESP_OFFSET = 32'h0000_01c0; +parameter CV_VP_SIG_WRITER_OFFSET = 32'h0000_0200; +parameter CV_VP_OBI_ERR_AWAIT_GOAHEAD_OFFSET = 32'h0000_0240; + +parameter CV_VP_VIRTUAL_PRINTER_BASE = CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET; +parameter CV_VP_RANDOM_NUM_BASE = CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET; +parameter CV_VP_CYCLE_COUNTER_BASE = CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET; +parameter CV_VP_STATUS_FLAGS_BASE = CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET; +parameter CV_VP_INTR_TIMER_BASE = CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET; +parameter CV_VP_OBI_ERR_AWAIT_GOAHEAD_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_ERR_AWAIT_GOAHEAD_OFFSET; +parameter CV_VP_DEBUG_CONTROL_BASE = CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET; +parameter CV_VP_OBI_SLV_RESP_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET; +parameter CV_VP_SIG_WRITER_BASE = CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET; +parameter CV_VP_FENCEI_TAMPER_BASE = CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET;