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add simple picorv32 example #5

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12 changes: 12 additions & 0 deletions picorv32/README.md
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# PicoRV32

Open the serial port, 115200 8N1, and press S1.

```
Hello World! If you can read this message then
the PicoRV32 CPU seems to be working just fine.

TEST PASSED!


```
2,146 changes: 2,146 additions & 0 deletions picorv32/fpga_project.fs

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14 changes: 14 additions & 0 deletions picorv32/fpga_project.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18" pn="GW2AR-LV18QN88C8/I7">gw2ar18-000</Device>
<FileList>
<File path="src/picorv32.v" type="file.verilog" enable="1"/>
<File path="src/simpleuart.v" type="file.verilog" enable="1"/>
<File path="src/top.v" type="file.verilog" enable="1"/>
<File path="src/fpga_project.cst" type="file.cst" enable="1"/>
<File path="src/fpga_project.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>
105 changes: 105 additions & 0 deletions picorv32/impl/project_process_config.json
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{
"Allow_Duplicate_Modules" : false,
"Annotated_Properties_for_Analyst" : true,
"BACKGROUND_PROGRAMMING" : "off",
"CMSER" : false,
"CMSER_CHECKSUM" : false,
"CMSER_MODE" : "auto",
"COMPRESS" : false,
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Conversion" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Default_Enum_Encoding" : "default",
"Disable_Insert_Pad" : false,
"ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"FSM Compiler" : true,
"Fanout_Guide" : 10000,
"Frequency" : "Auto",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"Implicit_Initial_Value_Support" : false,
"IncludePath" : [

],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true,
"Multiple_File_Compilation_Unit" : true,
"Number_of_Critical_Paths" : "",
"Number_of_Start/End_Points" : "",
"OUTPUT_BASE_NAME" : "fpga_project",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"Pipelining" : true,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"Push_Tristates" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : false,
"Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false,
"Resolve_Mixed_Drivers" : false,
"Resource_Sharing" : true,
"Retiming" : false,
"Route_Maxfan" : 23,
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SSPI" : false,
"STOP_CMSER" : false,
"Show_All_Warnings" : false,
"Synthesis On/Off Implemented as Translate On/Off" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "system",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"Update_Compile_Point_Timing_Data" : false,
"Use_Clock_Period_for_Unconstrainted IO" : false,
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"Write_Vendor_Constraint_File" : true,
"show_all_warnings" : false,
"turn_off_bg" : false
}
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