Is there anyway to just generate verilog design?

[tissue3]

I would like to see some area estimation result instead of getting actual bitstreams because it takes too long time. I wonder if there a way for spatial to just generate verilog but not bitstream, so I can use Vivado to synthesis the design.
I've tried to synthesis Top.v in verilog-aws with the following code and got a lot of syntax errors.

[mattfel1]

Hi. There was a bit of refactoring that has been ongoing for the past few weeks, but here is what you should do assuming you are on the latest version of spatial or spatial-quickstart. If you are getting weird, random errors we most likely just need to play around with the .ivy2 cache to get everything up to date.

You can generate the raw verilog for your app with any backend, but if you are using AWS_F1, you just need to run make aws-F1-hw. If you look at the makefile, you can just comment out this line of that target and you should have everything you need. python aws.sw-resources/gen_aws_design.py $(AWS_HOME)/hdk/cl/examples/${app_name}. You really just need the sbt "runMain spatialIP.Instantiator --verilog --testArgs aws" command to shake the verilog out of the generated Chisel.

All of the app's verilog will get written to verilog/SpatialIP.v. You will also probably need some of the hardware templates that it copies into that directory to actually synthesize (SRAMVerilogAWS.v, RetimeShiftRegister.sv, etc).

We are just starting to put together (informal) guides on modifying parts of core Spatial here. https://github.com/stanford-ppl/spatial/blob/master/resources/AddingBackend.md. If you just look at the figure at the end of this document it should help explain what comes out of the make [AWS-F1-]hw in the generated directory. If you don't have DRAM streams or are using pure AXI stream interfaces and you just want the "AccelUnit" IP, you can export FRINGELESS=1 to make it not include any of the DMA Fringe stuff. This may only work for the VCS target right now and is very experimental though.

If your goal is to get some P&R or synth numbers for a Xilinx board that isn't going to get dropped into the FPGA ecosystem, I recommend using the Zynq, ZCU, or KCU1500 backends. If you are targeting a different board and already have the tcl scripts set up and just need verilog, we would be happy to incorporate it in the compiler as well.