From 8a69f770b4e7b5682f7720ecd6771851d0c7004d Mon Sep 17 00:00:00 2001
From: Jan Teske <jteske@posteo.net>
Date: Sun, 8 Mar 2020 11:13:53 +0100
Subject: [PATCH 1/2] Fix `MonoTimer`s frequency

This commit sets `MonoTimer`'s frequency to HCLK.

The `MonoTimer` internally counts the cycles of the Cortex core.
The core's clock is HCLK, but SYSCLK was used for the timer's frequency
before this commit.
---
 CHANGELOG.md | 2 ++
 src/time.rs  | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index b1d40d97..02678782 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Fixed
 
+- Fix wrong frequency reported by `MonoTimer`
 - Fix period retrieval for timers
 
 ### Changed
@@ -22,6 +23,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Improve `SPI` documentation
 - Improve `RCC` and `AFIO` register documentation
 
+
 ## [v0.6.0] - 2020-06-06
 
 ### Breaking changes
diff --git a/src/time.rs b/src/time.rs
index 6d37382b..e69439eb 100644
--- a/src/time.rs
+++ b/src/time.rs
@@ -241,7 +241,7 @@ impl MonoTimer {
         drop(dwt);
 
         MonoTimer {
-            frequency: clocks.sysclk(),
+            frequency: clocks.hclk(),
         }
     }
 

From 48eb5fee677648b7d727b45709c03e5b8ec2f3ab Mon Sep 17 00:00:00 2001
From: TheZoq2 <frans.skarman@protonmail.com>
Date: Wed, 24 Jun 2020 23:09:32 +0200
Subject: [PATCH 2/2] Fix Timer::syst

---
 CHANGELOG.md | 2 +-
 src/timer.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 02678782..f9d60dc3 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Fixed
 
 - Fix wrong frequency reported by `MonoTimer`
+- Fix wrong timings generated by `Timer::syst` 
 - Fix period retrieval for timers
 
 ### Changed
@@ -23,7 +24,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Improve `SPI` documentation
 - Improve `RCC` and `AFIO` register documentation
 
-
 ## [v0.6.0] - 2020-06-06
 
 ### Breaking changes
diff --git a/src/timer.rs b/src/timer.rs
index d60239f4..840bee7c 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -163,7 +163,7 @@ impl Timer<SYST> {
         syst.set_clock_source(SystClkSource::Core);
         Self {
             tim: syst,
-            clk: clocks.sysclk(),
+            clk: clocks.hclk(),
         }
     }