diff --git a/CHANGELOG.md b/CHANGELOG.md
index 30893f4a..02a314e3 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -3,6 +3,18 @@
 ## [Unreleased]
 
 * MSRV increased to Rust 1.66.1 [#473]
+* Upgraded to embedded-hal v1.0.0-rc.3
+
+* delay: `delay_ms` and 'delay_us` methods now require importing: `use embedded_hal::delay::DelayNs;`
+
+* pwm: Renamed `get_max_duty` -> `max_duty_cycle`; `set_duty` -> `set_duty_cycle`
+* pwm: `enable` method now returns type `Result<(), PwmError>`
+* pwm: LPTIMs can return a `NotEnabled` error from `set_duty_cycle`
+
+* serial: Implement embedded-io `Read` and `Write` traits
+* serial: Rename methods `read` -> `read_byte`; `write` -> `write_byte`
+
+* rng: Use the `fill` method instead of the old `read` method
 
 ## [v0.15.1] 2023-11-03
 
diff --git a/Cargo.toml b/Cargo.toml
index b8a8c9cf..9a8df597 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -28,8 +28,10 @@ rustdoc-args = ["--cfg", "docsrs"]
 
 [dependencies]
 fugit = "0.3.5"
-embedded-hal = { version = "0.2.6", features = ["unproven"] }
+embedded-hal-02 = { package = "embedded-hal", version = "0.2.7", features = ["unproven"] }
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
 embedded-dma = "0.2.0"
+embedded-io = "0.6.1"
 cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
 defmt = { version = ">=0.2.0,<0.4", optional = true }
 stm32h7 = { version = "^0.15.1", default-features = false }
diff --git a/examples/blinky-stm32h747i-disco.rs b/examples/blinky-stm32h747i-disco.rs
index d520cf61..38d060f0 100644
--- a/examples/blinky-stm32h747i-disco.rs
+++ b/examples/blinky-stm32h747i-disco.rs
@@ -6,6 +6,8 @@
 use cortex_m_rt::entry;
 use stm32h7xx_hal::{pac, prelude::*};
 
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
+
 use log::info;
 
 #[macro_use]
@@ -53,13 +55,13 @@ fn main() -> ! {
             led2.set_low();
             led3.set_high();
             led4.set_low();
-            delay.delay_ms(500_u16);
+            delay.delay_ms(500);
 
             led1.set_low();
             led2.set_high();
             led3.set_low();
             led4.set_high();
-            delay.delay_ms(500_u16);
+            delay.delay_ms(500);
         }
     }
 }
diff --git a/examples/blinky.rs b/examples/blinky.rs
index 4ce8f973..5a553f00 100644
--- a/examples/blinky.rs
+++ b/examples/blinky.rs
@@ -5,13 +5,14 @@
 #![no_std]
 
 use cortex_m_rt::entry;
+#[macro_use]
+mod utilities;
+
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::{pac, prelude::*};
 
 use log::info;
 
-#[macro_use]
-mod utilities;
-
 #[entry]
 fn main() -> ! {
     utilities::logger::init();
@@ -42,9 +43,9 @@ fn main() -> ! {
 
     loop {
         led.set_high();
-        delay.delay_ms(500_u16);
+        delay.delay_ms(500);
 
         led.set_low();
-        delay.delay_ms(500_u16);
+        delay.delay_ms(500);
     }
 }
diff --git a/examples/blinky_random.rs b/examples/blinky_random.rs
index d9129016..f51d704e 100644
--- a/examples/blinky_random.rs
+++ b/examples/blinky_random.rs
@@ -7,6 +7,7 @@
 #![no_std]
 
 use cortex_m_rt::entry;
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::{pac, prelude::*};
 
 #[macro_use]
diff --git a/examples/blinky_timer.rs b/examples/blinky_timer.rs
index 89cfd543..2635c7c3 100644
--- a/examples/blinky_timer.rs
+++ b/examples/blinky_timer.rs
@@ -10,7 +10,8 @@ mod utilities;
 extern crate nb;
 
 use cortex_m_rt::entry;
-use stm32h7xx_hal::{pac, prelude::*, time::MilliSeconds};
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
+use stm32h7xx_hal::{pac, prelude::*};
 
 use log::info;
 
@@ -50,13 +51,12 @@ fn main() -> ! {
         for _ in 0..5 {
             // 20ms wait with timer
             led.toggle();
-            timer.start(MilliSeconds::from_ticks(20).into_rate());
+            timer.start(50.Hz()).unwrap();
             block!(timer.wait()).ok();
 
-            // Delay for 500ms. Timer must operate correctly on next
-            // use.
+            // Delay for 500ms. Timer must operate correctly on next use.
             led.toggle();
-            delay.delay_ms(500_u16);
+            delay.delay_ms(500);
         }
     }
 }
diff --git a/examples/can-echo.rs b/examples/can-echo.rs
index 83d8650c..5c466fa4 100644
--- a/examples/can-echo.rs
+++ b/examples/can-echo.rs
@@ -18,6 +18,7 @@ use crate::hal::{
     rcc,
     rcc::rec,
 };
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use fdcan::{
     config::NominalBitTiming,
     filter::{StandardFilter, StandardFilterSlot},
@@ -135,7 +136,7 @@ fn main() -> ! {
             info!("Received Header: {:#X?}", rxheader);
             info!("received data: {:X?}", &buffer);
 
-            delay.delay_ms(1_u16);
+            delay.delay_ms(1);
             block!(can.transmit(rxheader.unwrap().to_tx_header(None), &buffer))
                 .unwrap();
             info!("Transmit: {:X?}", buffer);
diff --git a/examples/can-fd.rs b/examples/can-fd.rs
index ddfa0810..47f11b13 100644
--- a/examples/can-fd.rs
+++ b/examples/can-fd.rs
@@ -30,6 +30,7 @@ use crate::hal::{
     rcc,
     rcc::rec,
 };
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use fdcan::{
     config::{DataBitTiming, FrameTransmissionConfig, NominalBitTiming},
     filter::{StandardFilter, StandardFilterSlot},
@@ -167,7 +168,7 @@ fn main() -> ! {
             info!("Received Header: {:#X?}", rxheader);
             info!("received data: {:X?}", &buffer);
 
-            delay.delay_ms(1_u16);
+            delay.delay_ms(1);
             block!(can.transmit(rxheader.unwrap().to_tx_header(None), &buffer))
                 .unwrap();
             info!("Transmit: {:X?}", buffer);
diff --git a/examples/dac.rs b/examples/dac.rs
index ff5583b9..42daf69d 100644
--- a/examples/dac.rs
+++ b/examples/dac.rs
@@ -4,7 +4,7 @@
 
 use cortex_m::asm;
 use cortex_m_rt::entry;
-use stm32h7xx_hal::hal::Direction;
+use stm32h7xx_hal::qei::Direction;
 #[macro_use]
 mod utilities;
 use stm32h7xx_hal::{pac, prelude::*};
diff --git a/examples/display-dsi-command-teartest-stm32h747i-disco.rs b/examples/display-dsi-command-teartest-stm32h747i-disco.rs
index e14907da..5e60d8b0 100644
--- a/examples/display-dsi-command-teartest-stm32h747i-disco.rs
+++ b/examples/display-dsi-command-teartest-stm32h747i-disco.rs
@@ -27,6 +27,8 @@ use log::info;
 use otm8009a::Otm8009AConfig;
 use stm32h7xx_hal::dsi::{ColorCoding, DsiChannel, DsiConfig, DsiPllConfig};
 
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
+
 extern crate cortex_m;
 extern crate cortex_m_rt as rt;
 use cortex_m_rt::{entry, exception};
diff --git a/examples/display-dsi-video-stm32h747i-disco.rs b/examples/display-dsi-video-stm32h747i-disco.rs
index e27fc9b4..cc4ede07 100644
--- a/examples/display-dsi-video-stm32h747i-disco.rs
+++ b/examples/display-dsi-video-stm32h747i-disco.rs
@@ -22,6 +22,8 @@ use log::info;
 use otm8009a::Otm8009AConfig;
 use stm32h7xx_hal::dsi::{ColorCoding, DsiChannel, DsiConfig, DsiPllConfig};
 
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
+
 extern crate cortex_m;
 extern crate cortex_m_rt as rt;
 use cortex_m_rt::{entry, exception};
diff --git a/examples/display-dsi-video-teartest-stm32h747i-disco.rs b/examples/display-dsi-video-teartest-stm32h747i-disco.rs
index 4b95ac8c..d020ecbf 100644
--- a/examples/display-dsi-video-teartest-stm32h747i-disco.rs
+++ b/examples/display-dsi-video-teartest-stm32h747i-disco.rs
@@ -30,6 +30,8 @@ extern crate cortex_m;
 extern crate cortex_m_rt as rt;
 use cortex_m_rt::{entry, exception};
 
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
+
 use crate::utilities_display::display_target::BufferedDisplay;
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::ltdc;
diff --git a/examples/embedded-graphics.rs b/examples/embedded-graphics.rs
index cbdc2386..ff9e97d4 100644
--- a/examples/embedded-graphics.rs
+++ b/examples/embedded-graphics.rs
@@ -21,6 +21,7 @@ extern crate cortex_m_rt as rt;
 use core::sync::atomic::{AtomicU32, Ordering};
 use cortex_m_rt::{entry, exception};
 
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::rcc::CoreClocks;
 use stm32h7xx_hal::{ltdc, xspi};
@@ -205,7 +206,7 @@ fn main() -> ! {
     let mut lcd_disp_ctrl = gpiod.pd10.into_push_pull_output();
     let mut lcd_bl_ctrl = gpiog.pg15.into_push_pull_output();
 
-    delay.delay_ms(40u8);
+    delay.delay_ms(40);
 
     let mut ltdc = ltdc::Ltdc::new(dp.LTDC, ccdr.peripheral.LTDC, &ccdr.clocks);
 
diff --git a/examples/gpio_with_input.rs b/examples/gpio_with_input.rs
index 3273d3d3..0492bb05 100644
--- a/examples/gpio_with_input.rs
+++ b/examples/gpio_with_input.rs
@@ -7,7 +7,7 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::{pac, prelude::*};
 
 use log::info;
@@ -45,10 +45,10 @@ fn main() -> ! {
 
     loop {
         led.set_high();
-        delay.delay_ms(100_u16);
+        delay.delay_ms(100);
 
         led.set_low();
-        delay.delay_ms(100_u16);
+        delay.delay_ms(100);
 
         let is_high = led.with_input(|x| x.is_high());
         info!("LED pin high? {}", is_high);
diff --git a/examples/i2c.rs b/examples/i2c.rs
index aed5c3b5..3e3f0e4b 100644
--- a/examples/i2c.rs
+++ b/examples/i2c.rs
@@ -1,11 +1,12 @@
 #![no_main]
 #![no_std]
 
+use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
-use stm32h7xx_hal::{pac, prelude::*};
 
-use cortex_m_rt::entry;
+use embedded_hal_1::i2c::*; // this example uses embedded-hal v1.0
+use stm32h7xx_hal::{pac, prelude::*};
 
 use log::info;
 
diff --git a/examples/i2c4_bdma.rs b/examples/i2c4_bdma.rs
index e6402567..76e41686 100644
--- a/examples/i2c4_bdma.rs
+++ b/examples/i2c4_bdma.rs
@@ -8,19 +8,18 @@
 
 use core::mem::MaybeUninit;
 
+use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
 
+use embedded_hal_1::i2c::*; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::dma::{
     bdma::{BdmaConfig, StreamsTuple},
     PeripheralToMemory, Transfer,
 };
-
 use stm32h7xx_hal::prelude::*;
 use stm32h7xx_hal::{i2c, pac, pac::interrupt, rcc::LowPowerMode};
 
-use cortex_m_rt::entry;
-
 use log::info;
 
 // The BDMA can only interact with SRAM4.
diff --git a/examples/pwm.rs b/examples/pwm.rs
index 13d4a530..f127aaa6 100644
--- a/examples/pwm.rs
+++ b/examples/pwm.rs
@@ -4,9 +4,12 @@
 
 use cortex_m::asm;
 use cortex_m_rt::entry;
+
+use embedded_hal_1::pwm::*; // this example uses embedded-hal v1.0
+use stm32h7xx_hal::{pac, prelude::*};
+
 #[macro_use]
 mod utilities;
-use stm32h7xx_hal::{pac, prelude::*};
 
 use log::info;
 
@@ -47,23 +50,23 @@ fn main() -> ! {
             .pwm(pins, 10.kHz(), ccdr.peripheral.TIM1, &ccdr.clocks);
 
     // Output PWM on PA8
-    let max = pwm.get_max_duty();
-    pwm.set_duty(max / 2);
+    let max = pwm.max_duty_cycle();
+    pwm.set_duty_cycle(max / 2).unwrap();
 
     info!("50%");
-    pwm.enable();
+    pwm.enable().unwrap();
     asm::bkpt();
 
     info!("25%");
-    pwm.set_duty(max / 4);
+    pwm.set_duty_cycle(max / 4).unwrap();
     asm::bkpt();
 
     info!("12.5%");
-    pwm.set_duty(max / 8);
+    pwm.set_duty_cycle(max / 8).unwrap();
     asm::bkpt();
 
     info!("100%");
-    pwm.set_duty(max);
+    pwm.set_duty_cycle(max).unwrap();
     asm::bkpt();
 
     let mut pwm = dp.TIM12.pwm(
@@ -74,9 +77,9 @@ fn main() -> ! {
     );
 
     // Output PWM on PB14
-    let max = pwm.get_max_duty();
-    pwm.set_duty(max / 2);
-    pwm.enable();
+    let max = pwm.max_duty_cycle();
+    pwm.set_duty_cycle(max / 2).unwrap();
+    pwm.enable().unwrap();
 
     loop {
         cortex_m::asm::nop()
diff --git a/examples/pwm_advanced.rs b/examples/pwm_advanced.rs
index 36d38a49..26550b2c 100644
--- a/examples/pwm_advanced.rs
+++ b/examples/pwm_advanced.rs
@@ -45,7 +45,7 @@
 //! If you momentarily pull PE15 low, LD2 will turn on and you will get no PWM on PE8-PE14, even if you pull PE15 high again
 //! If PE15 is high and you press the USER button, TIM1 PWM will resume on PE8-PE14
 
-#![deny(warnings)]
+//#![deny(warnings)]
 #![no_main]
 #![no_std]
 
@@ -55,6 +55,8 @@ mod utilities;
 use stm32h7xx_hal::pwm::{FaultMonitor, Polarity};
 use stm32h7xx_hal::{pac, prelude::*};
 
+use embedded_hal_1::pwm::*; // this example uses embedded-hal v1.0
+
 use log::info;
 
 #[entry]
@@ -122,16 +124,16 @@ fn main() -> ! {
     let mut t1c4 = t1c4.into_active_low();
 
     // Output TIM1 PWM
-    let period = t1c1.get_max_duty();
-    t1c1.set_duty(period / 2);
-    t1c2.set_duty(period / 8 * 7);
-    t1c3.set_duty(period / 8);
-    t1c4.set_duty(period / 2);
+    let period = t1c1.max_duty_cycle();
+    t1c1.set_duty_cycle(period / 2).unwrap();
+    t1c2.set_duty_cycle(period / 8 * 7).unwrap();
+    t1c3.set_duty_cycle(period / 8).unwrap();
+    t1c4.set_duty_cycle(period / 2).unwrap();
 
-    t1c1.enable();
-    t1c2.enable();
-    t1c3.enable();
-    t1c4.enable();
+    t1c1.enable().unwrap();
+    t1c2.enable().unwrap();
+    t1c3.enable().unwrap();
+    t1c4.enable().unwrap();
 
     // Configure TIM2 PWM
     let (_t2control, (mut t2c2, mut t2c1, mut t2c3, t2c4)) = dp
@@ -154,16 +156,16 @@ fn main() -> ! {
     let mut t2c4 = t2c4.into_active_low();
 
     // Output TIM2 PWM
-    let period = t2c1.get_max_duty();
-    t2c1.set_duty(period / 4 * 3);
-    t2c2.set_duty(period / 2);
-    t2c3.set_duty(period / 4);
-    t2c4.set_duty(period / 4 * 3);
+    let period = t2c1.max_duty_cycle();
+    t2c1.set_duty_cycle(period / 4 * 3).unwrap();
+    t2c2.set_duty_cycle(period / 2).unwrap();
+    t2c3.set_duty_cycle(period / 4).unwrap();
+    t2c4.set_duty_cycle(period / 4 * 3).unwrap();
 
-    t2c1.enable();
-    t2c2.enable();
-    t2c3.enable();
-    t2c4.enable();
+    t2c1.enable().unwrap();
+    t2c2.enable().unwrap();
+    t2c3.enable().unwrap();
+    t2c4.enable().unwrap();
 
     // Configure TIM3 PWM
     let (_t3control, (mut t3c3, mut t3c2)) = dp
@@ -178,12 +180,12 @@ fn main() -> ! {
         .finalize();
 
     // Output TIM3 PWM
-    let period = t3c2.get_max_duty();
-    t3c2.set_duty(period / 3);
-    t3c3.set_duty(period / 3 * 2);
+    let period = t3c2.max_duty_cycle();
+    t3c2.set_duty_cycle(period / 3).unwrap();
+    t3c3.set_duty_cycle(period / 3 * 2).unwrap();
 
-    t3c2.enable();
-    t3c3.enable();
+    t3c2.enable().unwrap();
+    t3c3.enable().unwrap();
 
     // Configure TIM4 PWM
     let (_t4control, t4c4) = dp
@@ -199,10 +201,10 @@ fn main() -> ! {
     let mut t4c4 = t4c4.into_active_low();
 
     // Output TIM4 PWM
-    let period = t4c4.get_max_duty();
-    t4c4.set_duty(period / 10 * 4);
+    let period = t4c4.max_duty_cycle();
+    t4c4.set_duty_cycle(period / 10 * 4).unwrap();
 
-    t4c4.enable();
+    t4c4.enable().unwrap();
 
     // Configure TIM5 PWM
     let t5builder = dp
@@ -218,10 +220,10 @@ fn main() -> ! {
     let (_t5control, mut t5c4) = t5builder.finalize();
 
     // Output TIM5 PWM
-    let period = t5c4.get_max_duty();
-    t5c4.set_duty(period / 5 * 4);
+    let period = t5c4.max_duty_cycle();
+    t5c4.set_duty_cycle(period / 5 * 4).unwrap();
 
-    t5c4.enable();
+    t5c4.enable().unwrap();
 
     // Configure TIM8 PWM
     let (mut t8control, (t8c1, mut t8c2, t8c3, t8c4)) = dp
@@ -247,16 +249,16 @@ fn main() -> ! {
     let mut t8c4 = t8c4.into_active_low();
 
     // Output TIM8 PWM
-    let period = t8c1.get_max_duty();
-    t8c1.set_duty(period / 2);
-    t8c2.set_duty(period / 10);
-    t8c3.set_duty(period / 4);
-    t8c4.set_duty(period / 4 * 3);
+    let period = t8c1.max_duty_cycle();
+    t8c1.set_duty_cycle(period / 2).unwrap();
+    t8c2.set_duty_cycle(period / 10).unwrap();
+    t8c3.set_duty_cycle(period / 4).unwrap();
+    t8c4.set_duty_cycle(period / 4 * 3).unwrap();
 
-    t8c1.enable();
-    t8c2.enable();
-    t8c3.enable();
-    t8c4.enable();
+    t8c1.enable().unwrap();
+    t8c2.enable().unwrap();
+    t8c3.enable().unwrap();
+    t8c4.enable().unwrap();
 
     // Configure TIM12 PWM
     let (mut t12c2, t12c1) = dp.TIM12.pwm(
@@ -269,12 +271,12 @@ fn main() -> ! {
     let mut t12c1 = t12c1.into_active_low();
 
     // Output TIM12 PWM
-    let period = t12c1.get_max_duty();
-    t12c1.set_duty(period / 4);
-    t12c2.set_duty(period / 10 * 4);
+    let period = t12c1.max_duty_cycle();
+    t12c1.set_duty_cycle(period / 4).unwrap();
+    t12c2.set_duty_cycle(period / 10 * 4).unwrap();
 
-    t12c1.enable();
-    t12c2.enable();
+    t12c1.enable().unwrap();
+    t12c2.enable().unwrap();
 
     // Configure TIM13 PWM
     let (_t13control, t13c1) = dp
@@ -290,10 +292,10 @@ fn main() -> ! {
     let mut t13c1 = t13c1.into_active_low();
 
     // Output TIM13 PWM
-    let period = t13c1.get_max_duty();
-    t13c1.set_duty(period / 10 * 3);
+    let period = t13c1.max_duty_cycle();
+    t13c1.set_duty_cycle(period / 10 * 3).unwrap();
 
-    t13c1.enable();
+    t13c1.enable().unwrap();
 
     // Configure TIM14 PWM
     let (_t14control, mut t14c1) = dp
@@ -307,10 +309,10 @@ fn main() -> ! {
         .finalize();
 
     // Output TIM14 PWM
-    let period = t14c1.get_max_duty();
-    t14c1.set_duty(period / 5);
+    let period = t14c1.max_duty_cycle();
+    t14c1.set_duty_cycle(period / 5).unwrap();
 
-    t14c1.enable();
+    t14c1.enable().unwrap();
 
     // Configure TIM15 PWM
     let (mut t15control, (t15c1, mut t15c2)) = dp
@@ -331,12 +333,12 @@ fn main() -> ! {
         .into_comp_active_low();
 
     // Output TIM15 PWM
-    let period = t15c1.get_max_duty();
-    t15c1.set_duty(period / 4);
-    t15c2.set_duty(period / 2);
+    let period = t15c1.max_duty_cycle();
+    t15c1.set_duty_cycle(period / 4).unwrap();
+    t15c2.set_duty_cycle(period / 2).unwrap();
 
-    t15c1.enable();
-    t15c2.enable();
+    t15c1.enable().unwrap();
+    t15c2.enable().unwrap();
 
     // Configure TIM16 PWM
     let (mut t16control, t16c1) = dp
@@ -353,10 +355,10 @@ fn main() -> ! {
     let mut t16c1 = t16c1.into_active_low();
 
     // Output TIM16 PWM
-    let period = t16c1.get_max_duty();
-    t16c1.set_duty(period / 4);
+    let period = t16c1.max_duty_cycle();
+    t16c1.set_duty_cycle(period / 4).unwrap();
 
-    t16c1.enable();
+    t16c1.enable().unwrap();
 
     // Configure TIM17 PWM
     let (_t17control, t17c1) = dp
@@ -373,10 +375,10 @@ fn main() -> ! {
     let mut t17c1 = t17c1.into_complementary(gpiof.pf9.into_alternate());
 
     // Output TIM16 PWM
-    let period = t17c1.get_max_duty();
-    t17c1.set_duty(period / 2);
+    let period = t17c1.max_duty_cycle();
+    t17c1.set_duty_cycle(period / 2).unwrap();
 
-    t17c1.enable();
+    t17c1.enable().unwrap();
 
     info!("");
     info!("PWM channels enabled; see examples/pwm_advanced.rs for list of channels, pins, and settings");
diff --git a/examples/pwm_lptim.rs b/examples/pwm_lptim.rs
index 99cc9566..19513cf0 100644
--- a/examples/pwm_lptim.rs
+++ b/examples/pwm_lptim.rs
@@ -8,6 +8,8 @@ use cortex_m::asm;
 use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
+
+use embedded_hal_1::pwm::*; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::{pac, prelude::*, rcc::rec};
 
 use log::info;
@@ -44,26 +46,26 @@ fn main() -> ! {
             .kernel_clk_mux(rec::Lptim2ClkSel::Lsi),
         &ccdr.clocks,
     );
-    pwm.enable(); // must be enabled before use
+    pwm.enable().unwrap(); // must be enabled before use
 
     // Output PWM on PB13
-    let max = pwm.get_max_duty();
-    pwm.set_duty(max / 2);
+    let max = pwm.max_duty_cycle();
+    pwm.set_duty_cycle(max / 2).unwrap();
 
     info!("50%");
-    pwm.enable();
+    pwm.enable().unwrap();
     asm::bkpt();
 
     info!("25%");
-    pwm.set_duty(max / 4);
+    pwm.set_duty_cycle(max / 4).unwrap();
     asm::bkpt();
 
     info!("12.5%");
-    pwm.set_duty(max / 8);
+    pwm.set_duty_cycle(max / 8).unwrap();
     asm::bkpt();
 
     info!("100%");
-    pwm.set_duty(max);
+    pwm.set_duty_cycle(max).unwrap();
     asm::bkpt();
 
     loop {
diff --git a/examples/reset_reason.rs b/examples/reset_reason.rs
index 12b3518d..32115d75 100644
--- a/examples/reset_reason.rs
+++ b/examples/reset_reason.rs
@@ -8,6 +8,8 @@
 use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
+
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::{pac, prelude::*, rcc::ResetReason};
 
 use log::info;
@@ -48,7 +50,7 @@ fn main() -> ! {
 
     // delay 10s
     let mut delay = cp.SYST.delay(ccdr.clocks);
-    delay.delay_ms(10_000u16);
+    delay.delay_ms(10_000);
 
     // system reset
     stm32h7xx_hal::pac::SCB::sys_reset()
diff --git a/examples/sdmmc.rs b/examples/sdmmc.rs
index 206a6c0b..fde9f292 100644
--- a/examples/sdmmc.rs
+++ b/examples/sdmmc.rs
@@ -11,6 +11,7 @@
 mod utilities;
 
 use cortex_m_rt::entry;
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::sdmmc::{SdCard, Sdmmc};
 use stm32h7xx_hal::{pac, prelude::*};
@@ -114,7 +115,7 @@ fn main() -> ! {
 
         info!("Waiting for card...");
 
-        delay.delay_ms(1000u32);
+        delay.delay_ms(1000);
         led.toggle();
     }
 
diff --git a/examples/sdmmc_fat.rs b/examples/sdmmc_fat.rs
index c451de98..9dc5a76a 100644
--- a/examples/sdmmc_fat.rs
+++ b/examples/sdmmc_fat.rs
@@ -2,6 +2,7 @@
 #![no_std]
 
 use {
+    embedded_hal_1::delay::DelayNs, // this example uses embedded-hal v1.0 // this example uses embedded-hal v1.0
     embedded_sdmmc::{Controller, Mode, VolumeIdx},
     stm32h7xx_hal::sdmmc::{SdCard, Sdmmc},
     stm32h7xx_hal::{pac, prelude::*, rcc},
diff --git a/examples/serial-advanced.rs b/examples/serial-advanced.rs
index 5b517b98..271bf446 100644
--- a/examples/serial-advanced.rs
+++ b/examples/serial-advanced.rs
@@ -8,10 +8,9 @@ use cortex_m_rt::entry;
 mod utilities;
 use log::info;
 
+use embedded_io::Write;
 use stm32h7xx_hal::{pac, prelude::*, serial::config::Config};
 
-use core::fmt::Write;
-
 #[entry]
 fn main() -> ! {
     utilities::logger::init();
diff --git a/examples/serial-halfduplex.rs b/examples/serial-halfduplex.rs
index 2709359a..bb457697 100644
--- a/examples/serial-halfduplex.rs
+++ b/examples/serial-halfduplex.rs
@@ -71,15 +71,15 @@ fn main() -> ! {
     loop {
         // Tx from usart3
         for c in "Hello, world!".chars() {
-            block!(usart3.write(c as u8)).unwrap();
-            let received = block!(usart6.read()).unwrap();
+            block!(usart3.write_byte(c as u8)).unwrap();
+            let received = block!(usart6.read_byte()).unwrap();
             info!("usart6 rx {}", received as char);
         }
 
         // Tx from usart6
         for c in "Hello, world!".chars() {
-            block!(usart6.write(c as u8)).unwrap();
-            let received = block!(usart3.read()).unwrap();
+            block!(usart6.write_byte(c as u8)).unwrap();
+            let received = block!(usart3.read_byte()).unwrap();
             info!("usart3 rx {}", received as char);
         }
     }
diff --git a/examples/serial-inverted-loopback.rs b/examples/serial-inverted-loopback.rs
index 7a766dc2..2f522a53 100644
--- a/examples/serial-inverted-loopback.rs
+++ b/examples/serial-inverted-loopback.rs
@@ -12,10 +12,9 @@ use cortex_m_rt::entry;
 mod utilities;
 use log::info;
 
+use embedded_io::Write;
 use stm32h7xx_hal::{pac, prelude::*, serial};
 
-use core::fmt::Write;
-
 use nb::block;
 
 #[entry]
@@ -60,9 +59,9 @@ fn main() -> ! {
 
     loop {
         // Echo what is received on the serial link.
-        let received = block!(rx.read()).unwrap();
+        let received = block!(rx.read_byte()).unwrap();
         asm::delay(1000);
         info!("rx {}", received as char);
-        block!(tx.write(received)).ok();
+        block!(tx.write_byte(received)).ok();
     }
 }
diff --git a/examples/serial.rs b/examples/serial.rs
index dd417835..8eeac82c 100644
--- a/examples/serial.rs
+++ b/examples/serial.rs
@@ -10,10 +10,9 @@ use cortex_m_rt::entry;
 mod utilities;
 use log::info;
 
+use embedded_io::Write;
 use stm32h7xx_hal::{pac, prelude::*};
 
-use core::fmt::Write;
-
 use nb::block;
 
 #[entry]
@@ -55,7 +54,7 @@ fn main() -> ! {
 
     loop {
         // Echo what is received on the serial link.
-        let received = block!(rx.read()).unwrap();
-        block!(tx.write(received)).ok();
+        let received = block!(rx.read_byte()).unwrap();
+        block!(tx.write_byte(received)).ok();
     }
 }
diff --git a/examples/spi.rs b/examples/spi.rs
index 941ba9ba..f4fe99d9 100644
--- a/examples/spi.rs
+++ b/examples/spi.rs
@@ -5,12 +5,13 @@
 use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
+
+use embedded_hal_1::spi::*; // this example uses embedded-hal v1.0
+use nb::block;
 use stm32h7xx_hal::{pac, prelude::*, spi};
 
 use log::info;
 
-use nb::block;
-
 #[entry]
 fn main() -> ! {
     utilities::logger::init();
diff --git a/examples/spi_hardware_cs.rs b/examples/spi_hardware_cs.rs
index 458af1ea..0fcec790 100644
--- a/examples/spi_hardware_cs.rs
+++ b/examples/spi_hardware_cs.rs
@@ -16,12 +16,13 @@
 use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
+
+use embedded_hal_1::spi::*; // this example uses embedded-hal v1.0
+use nb::block;
 use stm32h7xx_hal::{pac, prelude::*, spi};
 
 use log::info;
 
-use nb::block;
-
 #[entry]
 fn main() -> ! {
     utilities::logger::init();
diff --git a/examples/spi_send_frames.rs b/examples/spi_send_frames.rs
index c1fc5c5e..67517f2b 100644
--- a/examples/spi_send_frames.rs
+++ b/examples/spi_send_frames.rs
@@ -11,7 +11,8 @@ use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
 use core::num::NonZeroU16;
-use spi::Spi;
+
+use embedded_hal_1::spi::*; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::{pac, prelude::*, spi};
 
 use log::info;
@@ -51,7 +52,7 @@ fn main() -> ! {
     info!("");
 
     // Initialise the SPI peripheral.
-    let mut spi: Spi<_, _, u8> = dp.SPI1.spi(
+    let mut spi: spi::Spi<_, _, u8> = dp.SPI1.spi(
         // Give ownership of the pins
         (sck, miso, mosi, hcs),
         // Create a config with the hardware chip select given
diff --git a/examples/temperature.rs b/examples/temperature.rs
index 1684a4ae..76acfe72 100644
--- a/examples/temperature.rs
+++ b/examples/temperature.rs
@@ -11,6 +11,7 @@ use cortex_m_rt::entry;
 #[macro_use]
 mod utilities;
 
+use embedded_hal_1::delay::DelayNs; // this example uses embedded-hal v1.0
 use stm32h7xx_hal::{
     adc,
     delay::Delay,
@@ -73,7 +74,7 @@ fn main() -> ! {
     // Setup Temperature Sensor on the disabled ADC
     let mut channel = adc::Temperature::new();
     channel.enable(&adc);
-    delay.delay_us(25_u16);
+    delay.delay_us(25);
     let mut adc = adc.enable();
 
     let vdda = 2.500; // Volts
diff --git a/examples/usb_phy_serial_interrupt.rs b/examples/usb_phy_serial_interrupt.rs
index 90b2533a..cad06ea3 100644
--- a/examples/usb_phy_serial_interrupt.rs
+++ b/examples/usb_phy_serial_interrupt.rs
@@ -11,6 +11,7 @@ use {
     core::cell::RefCell,
     core::mem::MaybeUninit,
     cortex_m::interrupt::{free as interrupt_free, Mutex},
+    embedded_hal_1::delay::DelayNs, // this example uses embedded-hal v1.0
     stm32h7xx_hal::{
         interrupt, pac,
         prelude::*,
@@ -110,10 +111,10 @@ unsafe fn main() -> ! {
     // clock source. Sometimes you have to enable them by yourself.
     // This is the case on the Arduino Portenta H7.
     let mut oscen = gpioh.ph1.into_push_pull_output();
-    delay.delay_ms(10u32);
+    delay.delay_ms(10);
     oscen.set_high();
     // Wait for osc to be stable
-    delay.delay_ms(100u32);
+    delay.delay_ms(100);
 
     // Set USB OTG pin floating
     let mut _usb_otg = gpioj.pj6.into_floating_input();
@@ -121,9 +122,9 @@ unsafe fn main() -> ! {
     // Reset USB Phy
     let mut usb_phy_rst = gpioj.pj4.into_push_pull_output();
     usb_phy_rst.set_low();
-    delay.delay_ms(10u8);
+    delay.delay_ms(10);
     usb_phy_rst.set_high();
-    delay.delay_ms(10u8);
+    delay.delay_ms(10);
 
     // Enable USB OTG_HS interrupt
     cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OTG_HS);
diff --git a/src/adc.rs b/src/adc.rs
index 2acb56f1..0ce9bffd 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -11,8 +11,7 @@
 //! - [Using ADC1 and ADC2 in parallel](https://github.com/stm32-rs/stm32h7xx-hal/blob/master/examples/adc12_parallel.rs)
 //! - [Using ADC1 through DMA](https://github.com/stm32-rs/stm32h7xx-hal/blob/master/examples/adc_dma.rs)
 
-use crate::hal::adc::{Channel, OneShot};
-use crate::hal::blocking::delay::DelayUs;
+use crate::hal::delay::DelayNs;
 
 use core::convert::Infallible;
 use core::marker::PhantomData;
@@ -186,6 +185,11 @@ impl AdcCalLinear {
     }
 }
 
+/// A marker trait to identify MCU pins that can be used as inputs to an ADC channel
+pub trait Channel<ADC> {
+    type ID;
+    fn channel() -> Self::ID;
+}
 macro_rules! adc_pins {
     ($ADC:ident, $($input:ty => $chan:expr),+ $(,)*) => {
         $(
@@ -364,7 +368,7 @@ pub trait AdcExt<ADC>: Sized {
     fn adc(
         self,
         f_adc: impl Into<Hertz>,
-        delay: &mut impl DelayUs<u8>,
+        delay: &mut impl DelayNs,
         prec: Self::Rec,
         clocks: &CoreClocks,
     ) -> Adc<ADC, Disabled>;
@@ -421,7 +425,7 @@ pub fn adc12(
     adc1: ADC1,
     adc2: ADC2,
     f_adc: impl Into<Hertz>,
-    delay: &mut impl DelayUs<u8>,
+    delay: &mut impl DelayNs,
     prec: rec::Adc12,
     clocks: &CoreClocks,
 ) -> (Adc<ADC1, Disabled>, Adc<ADC2, Disabled>) {
@@ -500,7 +504,7 @@ macro_rules! adc_hal {
 
 	            fn adc(self,
                        f_adc: impl Into<Hertz>,
-                       delay: &mut impl DelayUs<u8>,
+                       delay: &mut impl DelayNs,
                        prec: rec::$Rec,
                        clocks: &CoreClocks) -> Adc<$ADC, Disabled>
 	            {
@@ -513,7 +517,7 @@ macro_rules! adc_hal {
                 ///
                 /// Sets all configurable parameters to one-shot defaults,
                 /// performs a boot-time calibration.
-                pub fn $adcX(adc: $ADC, f_adc: impl Into<Hertz>, delay: &mut impl DelayUs<u8>,
+                pub fn $adcX(adc: $ADC, f_adc: impl Into<Hertz>, delay: &mut impl DelayNs,
                              prec: rec::$Rec, clocks: &CoreClocks
                 ) -> Self {
                     // Consume ADC register block, produce Self with default
@@ -631,13 +635,14 @@ macro_rules! adc_hal {
                 /// Disables Deeppowerdown-mode and enables voltage regulator
                 ///
                 /// Note: After power-up, a [`calibration`](#method.calibrate) shall be run
-                pub fn power_up(&mut self, delay: &mut impl DelayUs<u8>) {
+                pub fn power_up(&mut self, delay: &mut impl DelayNs) {
                     // Refer to RM0433 Rev 7 - Chapter 25.4.6
                     self.rb.cr.modify(|_, w|
                         w.deeppwd().clear_bit()
                             .advregen().set_bit()
                     );
-                    delay.delay_us(10_u8);
+
+                    delay.delay_us(10);
 
                     // check LDORDY bit if present
                     $(
@@ -884,6 +889,17 @@ macro_rules! adc_hal {
                     nb::Result::Ok(result)
                 }
 
+                /// Perform an ADC conversion on the specified pin
+                pub fn read<PIN, T>(&mut self, pin: &mut PIN) -> nb::Result<T, Infallible>
+                where
+                    PIN: Channel<$ADC, ID = u8>,
+                    T: From<u32>
+                {
+                    self.start_conversion(pin);
+                    let res = block!(self.read_sample()).unwrap();
+                    Ok(res.into())
+                }
+
                 fn check_conversion_conditions(&self) {
                     let cr = self.rb.cr.read();
                     // Ensure that no conversions are ongoing
@@ -1111,20 +1127,6 @@ macro_rules! adc_hal {
                     &mut self.rb
                 }
             }
-
-            impl<WORD, PIN> OneShot<$ADC, WORD, PIN> for Adc<$ADC, Enabled>
-            where
-                WORD: From<u32>,
-                PIN: Channel<$ADC, ID = u8>,
-            {
-                type Error = ();
-
-                fn read(&mut self, pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
-                    self.start_conversion(pin);
-                    let res = block!(self.read_sample()).unwrap();
-                    Ok(res.into())
-                }
-            }
         )+
     }
 }
diff --git a/src/dac.rs b/src/dac.rs
index 0617739b..72e563c9 100644
--- a/src/dac.rs
+++ b/src/dac.rs
@@ -9,7 +9,7 @@ use core::marker::PhantomData;
 use core::mem::MaybeUninit;
 
 use crate::gpio::{self, Analog};
-use crate::hal::blocking::delay::DelayUs;
+use crate::hal::delay::DelayNs;
 use crate::rcc::{rec, ResetEnable};
 #[cfg(not(feature = "rm0455"))]
 use crate::stm32::DAC as DAC1;
@@ -127,7 +127,7 @@ macro_rules! dac {
                 delay: &mut T,
             ) -> $CX<$DAC, Disabled>
             where
-                T: DelayUs<u32>,
+                T: DelayNs,
             {
                 let dac = unsafe { &(*$DAC::ptr()) };
                 dac.cr.modify(|_, w| w.$en().clear_bit());
@@ -136,7 +136,7 @@ macro_rules! dac {
                 let mut trim = 0;
                 while true {
                     dac.ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
-                    delay.delay_us(64_u32);
+                    delay.delay_us(64);
                     if dac.sr.read().$cal_flag().bit() {
                         break;
                     }
diff --git a/src/delay.rs b/src/delay.rs
index 31478806..2f7cb067 100644
--- a/src/delay.rs
+++ b/src/delay.rs
@@ -37,19 +37,21 @@
 //!
 //! - [Blinky](https://github.com/stm32-rs/stm32h7xx-hal/blob/master/examples/blinky.rs)
 
-use cast::u32;
 use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::SYST;
-use embedded_hal::{
-    blocking::delay::{DelayMs, DelayUs},
-    timer::CountDown,
-};
 use void::Void;
 
-use crate::nb::block;
+use crate::block;
 use crate::rcc::CoreClocks;
+use crate::stm32::{LPTIM1, LPTIM2, LPTIM3};
+#[cfg(not(feature = "rm0455"))]
+use crate::stm32::{LPTIM4, LPTIM5};
+use crate::stm32::{
+    TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5,
+    TIM6, TIM7, TIM8,
+};
 use crate::time::Hertz;
-use fugit::RateExtU32;
+use crate::timer::{Enabled, LpTimer, Timer};
 
 pub trait DelayExt {
     fn delay(self, clocks: CoreClocks) -> Delay;
@@ -76,7 +78,7 @@ pub struct Countdown<'a> {
 }
 
 impl<'a> Countdown<'a> {
-    /// Create a new [CountDown] measured in microseconds.
+    /// Create a new [Countdown] measured in microseconds.
     pub fn new(syst: &'a mut SYST, clocks: CoreClocks) -> Self {
         Self {
             syst,
@@ -110,12 +112,11 @@ impl<'a> Countdown<'a> {
     }
 }
 
-impl<'a> CountDown for Countdown<'a> {
-    type Time = fugit::MicrosDurationU32;
-
-    fn start<T>(&mut self, count: T)
+impl<'a> Countdown<'a> {
+    /// Starts a new count down
+    pub fn start<T>(&mut self, count: T)
     where
-        T: Into<Self::Time>,
+        T: Into<fugit::MicrosDurationU32>,
     {
         let us = count.into().ticks();
 
@@ -135,7 +136,8 @@ impl<'a> CountDown for Countdown<'a> {
         self.start_wait();
     }
 
-    fn wait(&mut self) -> nb::Result<(), Void> {
+    /// Non-blockingly “waits” until the count down finishes
+    pub fn wait(&mut self) -> nb::Result<(), Void> {
         if self.finished {
             return Ok(());
         }
@@ -163,42 +165,12 @@ impl Delay {
     }
 }
 
-impl DelayMs<u32> for Delay {
-    fn delay_ms(&mut self, ms: u32) {
-        self.delay_us(ms * 1_000);
-    }
-}
-
-impl DelayMs<u16> for Delay {
-    fn delay_ms(&mut self, ms: u16) {
-        self.delay_ms(u32(ms));
-    }
-}
-
-impl DelayMs<u8> for Delay {
-    fn delay_ms(&mut self, ms: u8) {
-        self.delay_ms(u32(ms));
-    }
-}
-
-impl DelayUs<u32> for Delay {
-    fn delay_us(&mut self, us: u32) {
+impl Delay {
+    /// Internal method to delay cycles with systick
+    fn systick_delay_cycles(&mut self, mut total_rvr: u64) {
         // The SysTick Reload Value register supports values between 1 and 0x00FFFFFF.
         const MAX_RVR: u32 = 0x00FF_FFFF;
 
-        // With c_ck up to 480e6, we need u64 for delays > 8.9s
-
-        let mut total_rvr = if cfg!(not(feature = "revision_v")) {
-            // See errata ES0392 §2.2.3. Revision Y does not have the /8 divider
-            u64::from(us) * u64::from(self.clocks.c_ck().raw() / 1_000_000)
-        } else if cfg!(feature = "cm4") {
-            // CM4 derived from HCLK
-            u64::from(us) * u64::from(self.clocks.hclk().raw() / 8_000_000)
-        } else {
-            // Normally divide by 8
-            u64::from(us) * u64::from(self.clocks.c_ck().raw() / 8_000_000)
-        };
-
         while total_rvr != 0 {
             let current_rvr = if total_rvr <= MAX_RVR.into() {
                 total_rvr as u32
@@ -218,44 +190,100 @@ impl DelayUs<u32> for Delay {
             self.syst.disable_counter();
         }
     }
+    /// Internal method that returns the clock frequency of systick
+    fn systick_clock(&self) -> u64 {
+        if cfg!(not(feature = "revision_v")) {
+            // See errata ES0392 §2.2.3. Revision Y does not have the /8 divider
+            u64::from(self.clocks.c_ck().raw())
+        } else if cfg!(feature = "cm4") {
+            // CM4 derived from HCLK
+            u64::from(self.clocks.hclk().raw() / 8)
+        } else {
+            // Normally divide by 8
+            u64::from(self.clocks.c_ck().raw() / 8)
+        }
+    }
+}
+
+impl embedded_hal_1::delay::DelayNs for Delay {
+    fn delay_ns(&mut self, ns: u32) {
+        // With c_ck up to 480e6, 1 cycle is always > 2ns
+
+        self.systick_delay_cycles(u64::from(ns + 1) / 2);
+    }
+    fn delay_us(&mut self, us: u32) {
+        // With c_ck up to 480e6, we need u64 for delays > 8.9s
+
+        let total_rvr =
+            u64::from(us) * ((self.systick_clock() + 999_999) / 1_000_000);
+        self.systick_delay_cycles(total_rvr);
+    }
+}
+
+// embedded_hal_02 implementations
+//
+
+impl embedded_hal_02::blocking::delay::DelayMs<u32> for Delay {
+    fn delay_ms(&mut self, ms: u32) {
+        // With c_ck up to 480e6, we need u64 for delays > 8.9s
+        let total_rvr = u64::from(ms) * ((self.systick_clock() + 999) / 1_000);
+        self.systick_delay_cycles(total_rvr);
+    }
+}
+
+impl embedded_hal_02::blocking::delay::DelayMs<u16> for Delay {
+    fn delay_ms(&mut self, ms: u16) {
+        self.delay_ms(cast::u32(ms));
+    }
 }
 
-impl DelayUs<u16> for Delay {
+impl embedded_hal_02::blocking::delay::DelayMs<u8> for Delay {
+    fn delay_ms(&mut self, ms: u8) {
+        self.delay_ms(cast::u32(ms));
+    }
+}
+
+impl embedded_hal_02::blocking::delay::DelayUs<u32> for Delay {
+    fn delay_us(&mut self, us: u32) {
+        // With c_ck up to 480e6, we need u64 for delays > 8.9s
+        let total_rvr =
+            u64::from(us) * ((self.systick_clock() + 999_999) / 1_000_000);
+        self.systick_delay_cycles(total_rvr);
+    }
+}
+
+impl embedded_hal_02::blocking::delay::DelayUs<u16> for Delay {
     fn delay_us(&mut self, us: u16) {
-        self.delay_us(u32(us))
+        self.delay_us(cast::u32(us))
     }
 }
 
-impl DelayUs<u8> for Delay {
+impl embedded_hal_02::blocking::delay::DelayUs<u8> for Delay {
     fn delay_us(&mut self, us: u8) {
-        self.delay_us(u32(us))
+        self.delay_us(cast::u32(us))
     }
 }
 
-/// CountDown Timer as a delay provider
-pub struct DelayFromCountDownTimer<T>(T);
+/// Delay that implements [embedded_hal::blocking::delay] traits
+pub struct DelayFromCountDownTimer<TIM>(TIM);
 
-impl<T> DelayFromCountDownTimer<T> {
-    /// Creates delay provider from a CountDown timer
-    pub fn new(timer: T) -> Self {
+impl<TIM> DelayFromCountDownTimer<TIM> {
+    /// Creates a delay from a timer resource
+    pub fn new(timer: TIM) -> Self {
         Self(timer)
     }
-
-    /// Releases the Timer
-    pub fn free(self) -> T {
+    /// Free the timer resource for other uses
+    pub fn free(self) -> TIM {
         self.0
     }
 }
 
 macro_rules! impl_delay_from_count_down_timer  {
-    ($(($Delay:ident, $delay:ident, $num:expr)),+) => {
+    ($($TIMX:ty),+) => {
         $(
-
-            impl<T> $Delay<u32> for DelayFromCountDownTimer<T>
-            where
-                T: CountDown<Time = Hertz>,
+            impl DelayFromCountDownTimer<$TIMX>
             {
-                fn $delay(&mut self, t: u32) {
+                fn delay_us_internal(&mut self, t: u32) {
                     let mut time_left = t;
 
                     // Due to the LpTimer having only a 3 bit scaler, it is
@@ -264,37 +292,77 @@ macro_rules! impl_delay_from_count_down_timer  {
                     // Assuming the fastest clk_hz = 480Mhz this is roughly ~17ms,
                     // or a frequency of ~57.2Hz. We use a 60Hz frequency for each
                     // loop step here to ensure that we stay within these bounds.
-                    let looping_delay = $num / 60;
-                    let looping_delay_hz = Hertz::from_raw($num / looping_delay);
+                    let looping_delay = 1_000_000 / 60;
+                    let looping_delay_hz = Hertz::from_raw(1_000_000 / looping_delay);
 
-                    self.0.start(looping_delay_hz);
+                    let _ = self.0.start(looping_delay_hz); // This method is infallible
                     while time_left > looping_delay {
                         block!(self.0.wait()).ok();
                         time_left -= looping_delay;
                     }
 
                     if time_left > 0 {
-                        self.0.start(($num / time_left).Hz());
+                        // This method is infallible
+                        let _ = self.0.start(Hertz::from_raw(1_000_000 / time_left));
                         block!(self.0.wait()).ok();
                     }
                 }
             }
 
-            impl<T> $Delay<u16> for DelayFromCountDownTimer<T>
-            where
-                T: CountDown<Time = Hertz>,
-            {
-                fn $delay(&mut self, t: u16) {
-                    self.$delay(t as u32);
+            impl embedded_hal_1::delay::DelayNs for DelayFromCountDownTimer<$TIMX> {
+                fn delay_ns(&mut self, ns: u32) {
+                    // TODO(): This delay is 1000x longer than the intended duration!
+                    self.delay_us_internal(ns);
+                }
+                fn delay_us(&mut self, us: u32) {
+                    self.delay_us_internal(us);
                 }
             }
+            // embedded_hal_02 implementations
+            //
 
-            impl<T> $Delay<u8> for DelayFromCountDownTimer<T>
-            where
-                T: CountDown<Time = Hertz>,
+            impl embedded_hal_02::blocking::delay::DelayMs<u32>
+                for DelayFromCountDownTimer<$TIMX>
+            {
+                fn delay_ms(&mut self, ms: u32) {
+                    for _ in 0..1000 {
+                        self.delay_us_internal(ms);
+                    }
+                }
+            }
+            impl embedded_hal_02::blocking::delay::DelayMs<u16>
+                for DelayFromCountDownTimer<$TIMX>
+            {
+                fn delay_ms(&mut self, ms: u16) {
+                    self.delay_ms(cast::u32(ms));
+                }
+            }
+            impl embedded_hal_02::blocking::delay::DelayMs<u8>
+                for DelayFromCountDownTimer<$TIMX>
+            {
+                fn delay_ms(&mut self, ms: u8) {
+                    self.delay_ms(cast::u32(ms));
+                }
+            }
+            impl embedded_hal_02::blocking::delay::DelayUs<u32>
+                for DelayFromCountDownTimer<$TIMX>
+            {
+                fn delay_us(&mut self, us: u32) {
+                    self.delay_us_internal(us);
+                }
+            }
+            impl embedded_hal_02::blocking::delay::DelayUs<u16>
+                for DelayFromCountDownTimer<$TIMX>
             {
-                fn $delay(&mut self, t: u8) {
-                    self.$delay(t as u32);
+                fn delay_us(&mut self, us: u16) {
+                    self.delay_us(cast::u32(us))
+                }
+            }
+            impl embedded_hal_02::blocking::delay::DelayUs<u8>
+                for DelayFromCountDownTimer<$TIMX>
+            {
+                fn delay_us(&mut self, us: u8) {
+                    self.delay_us(cast::u32(us))
                 }
             }
         )+
@@ -302,6 +370,15 @@ macro_rules! impl_delay_from_count_down_timer  {
 }
 
 impl_delay_from_count_down_timer! {
-    (DelayMs, delay_ms, 1_000),
-    (DelayUs, delay_us, 1_000_000)
+    Timer<TIM1>, Timer<TIM8>,
+    Timer<TIM2>, Timer<TIM3>, Timer<TIM4>,
+    Timer<TIM5>, Timer<TIM6>, Timer<TIM7>,
+    Timer<TIM12>, Timer<TIM13>, Timer<TIM14>, Timer<TIM15>, Timer<TIM16>, Timer<TIM17>
+}
+impl_delay_from_count_down_timer! {
+    LpTimer<LPTIM1, Enabled>, LpTimer<LPTIM2, Enabled>, LpTimer<LPTIM3, Enabled>
+}
+#[cfg(not(feature = "rm0455"))]
+impl_delay_from_count_down_timer! {
+    LpTimer<LPTIM4, Enabled>, LpTimer<LPTIM5, Enabled>
 }
diff --git a/src/gpio.rs b/src/gpio.rs
index 3419e22c..f2b404ab 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -76,8 +76,9 @@ pub use exti::ExtiPin;
 mod dynamic;
 pub use dynamic::{Dynamic, DynamicPin};
 mod hal_02;
+mod hal_1;
 
-pub use embedded_hal::digital::v2::PinState;
+pub use embedded_hal_1::digital::PinState;
 
 use core::fmt;
 
@@ -458,7 +459,6 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, Output<MODE>> {
     pub fn set_low(&mut self) {
         self._set_low()
     }
-
     /// Is the pin in drive high or low mode?
     #[inline(always)]
     pub fn get_state(&self) -> PinState {
diff --git a/src/gpio/hal_02.rs b/src/gpio/hal_02.rs
index f8d62f69..73618ef3 100644
--- a/src/gpio/hal_02.rs
+++ b/src/gpio/hal_02.rs
@@ -2,13 +2,28 @@ use core::convert::Infallible;
 
 use super::{
     dynamic::PinModeError, marker, DynamicPin, ErasedPin, Input, OpenDrain,
-    Output, PartiallyErasedPin, Pin, PinMode, PinState,
+    Output, PartiallyErasedPin, Pin, PinMode,
 };
 
-use embedded_hal::digital::v2::{
-    InputPin, IoPin, OutputPin, StatefulOutputPin, ToggleableOutputPin,
+use embedded_hal_02::digital::v2::{
+    InputPin, IoPin, OutputPin, PinState, StatefulOutputPin,
+    ToggleableOutputPin,
 };
 
+impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
+    /// Set the output of the pin regardless of its mode.
+    /// Primarily used to set the output value of the pin
+    /// before changing its mode to an output to avoid
+    /// a short spike of an incorrect value
+    #[inline(always)]
+    fn _set_state_02(&mut self, state: PinState) {
+        match state {
+            PinState::High => self._set_high(),
+            PinState::Low => self._set_low(),
+        }
+    }
+}
+
 // Implementations for `Pin`
 
 impl<const P: char, const N: u8, MODE> OutputPin for Pin<P, N, Output<MODE>> {
@@ -78,7 +93,7 @@ impl<const P: char, const N: u8> IoPin<Self, Self>
         Ok(self)
     }
     fn into_output_pin(mut self, state: PinState) -> Result<Self, Self::Error> {
-        self.set_state(state);
+        self._set_state_02(state);
         Ok(self)
     }
 }
@@ -93,7 +108,7 @@ where
         Ok(self.into_input())
     }
     fn into_output_pin(mut self, state: PinState) -> Result<Self, Self::Error> {
-        self.set_state(state);
+        self._set_state_02(state);
         Ok(self)
     }
 }
@@ -111,7 +126,7 @@ where
         mut self,
         state: PinState,
     ) -> Result<Pin<P, N, Output<Otype>>, Self::Error> {
-        self._set_state(state);
+        self._set_state_02(state);
         Ok(self.into_mode())
     }
 }
diff --git a/src/gpio/hal_1.rs b/src/gpio/hal_1.rs
new file mode 100644
index 00000000..6132c8f5
--- /dev/null
+++ b/src/gpio/hal_1.rs
@@ -0,0 +1,213 @@
+use super::{
+    dynamic::PinModeError, marker, DynamicPin, ErasedPin, Output,
+    PartiallyErasedPin, Pin,
+};
+
+use embedded_hal_1::digital::{ErrorKind, ErrorType};
+use embedded_hal_1::digital::{InputPin, OutputPin, StatefulOutputPin};
+
+/// Error type for GPIO
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[non_exhaustive]
+pub enum GpioError {
+    /// [DynamicPin] For operations unsupported in current mode
+    IncorrectMode,
+    /// Error
+    Other,
+}
+impl embedded_hal_1::digital::Error for GpioError {
+    fn kind(&self) -> ErrorKind {
+        ErrorKind::Other
+    }
+}
+impl From<PinModeError> for GpioError {
+    fn from(_: PinModeError) -> GpioError {
+        GpioError::IncorrectMode
+    }
+}
+
+// Implementations for `Pin`
+
+impl<const P: char, const N: u8, M> ErrorType for Pin<P, N, M> {
+    type Error = GpioError;
+}
+
+impl<const P: char, const N: u8, MODE> OutputPin for Pin<P, N, Output<MODE>> {
+    #[inline(always)]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high();
+        Ok(())
+    }
+
+    #[inline(always)]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low();
+        Ok(())
+    }
+}
+
+impl<const P: char, const N: u8, MODE> StatefulOutputPin
+    for Pin<P, N, Output<MODE>>
+{
+    #[inline(always)]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(!self._is_set_low())
+    }
+
+    #[inline(always)]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_set_low())
+    }
+    #[inline(always)]
+    fn toggle(&mut self) -> Result<(), Self::Error> {
+        self.toggle();
+        Ok(())
+    }
+}
+
+impl<const P: char, const N: u8, MODE> InputPin for Pin<P, N, MODE>
+where
+    MODE: marker::Readable,
+{
+    #[inline(always)]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(!self._is_low())
+    }
+
+    #[inline(always)]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self._is_low())
+    }
+}
+
+// Implementations for `ErasedPin`
+
+impl<M> ErrorType for ErasedPin<M> {
+    type Error = GpioError;
+}
+
+impl<MODE> OutputPin for ErasedPin<Output<MODE>> {
+    #[inline(always)]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high();
+        Ok(())
+    }
+
+    #[inline(always)]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low();
+        Ok(())
+    }
+}
+
+impl<MODE> StatefulOutputPin for ErasedPin<Output<MODE>> {
+    #[inline(always)]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(ErasedPin::is_set_high(self))
+    }
+
+    #[inline(always)]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(ErasedPin::is_set_low(self))
+    }
+    #[inline(always)]
+    fn toggle(&mut self) -> Result<(), Self::Error> {
+        self.toggle();
+        Ok(())
+    }
+}
+
+impl<MODE> InputPin for ErasedPin<MODE>
+where
+    MODE: marker::Readable,
+{
+    #[inline(always)]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(ErasedPin::is_high(self))
+    }
+
+    #[inline(always)]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(ErasedPin::is_low(self))
+    }
+}
+
+// Implementations for `PartiallyErasedPin`
+
+impl<const P: char, M> ErrorType for PartiallyErasedPin<P, M> {
+    type Error = GpioError;
+}
+
+impl<const P: char, MODE> OutputPin for PartiallyErasedPin<P, Output<MODE>> {
+    #[inline(always)]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high();
+        Ok(())
+    }
+
+    #[inline(always)]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low();
+        Ok(())
+    }
+}
+
+impl<const P: char, MODE> StatefulOutputPin
+    for PartiallyErasedPin<P, Output<MODE>>
+{
+    #[inline(always)]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(PartiallyErasedPin::is_set_high(self))
+    }
+
+    #[inline(always)]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(PartiallyErasedPin::is_set_low(self))
+    }
+    #[inline(always)]
+    fn toggle(&mut self) -> Result<(), Self::Error> {
+        self.toggle();
+        Ok(())
+    }
+}
+
+impl<const P: char, MODE> InputPin for PartiallyErasedPin<P, MODE>
+where
+    MODE: marker::Readable,
+{
+    #[inline(always)]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(PartiallyErasedPin::is_high(self))
+    }
+
+    #[inline(always)]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(PartiallyErasedPin::is_low(self))
+    }
+}
+
+// Implementations for `DynamicPin`
+
+impl<const P: char, const N: u8> ErrorType for DynamicPin<P, N> {
+    type Error = GpioError;
+}
+
+impl<const P: char, const N: u8> OutputPin for DynamicPin<P, N> {
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high()?;
+        Ok(())
+    }
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low()?;
+        Ok(())
+    }
+}
+
+impl<const P: char, const N: u8> InputPin for DynamicPin<P, N> {
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(DynamicPin::is_high(self)?)
+    }
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(DynamicPin::is_low(self)?)
+    }
+}
diff --git a/src/i2c.rs b/src/i2c.rs
index 7f0bebaf..a9385ba8 100644
--- a/src/i2c.rs
+++ b/src/i2c.rs
@@ -9,7 +9,8 @@ use core::cmp;
 use core::marker::PhantomData;
 
 use crate::gpio::{self, Alternate, OpenDrain};
-use crate::hal::blocking::i2c::{Read, Write, WriteRead};
+use crate::hal;
+use crate::hal::i2c::{Operation, SevenBitAddress};
 use crate::rcc::{rec, CoreClocks, ResetEnable};
 use crate::stm32::{I2C1, I2C2, I2C3, I2C4};
 use crate::time::Hertz;
@@ -47,6 +48,7 @@ pub enum Stop {
 }
 
 /// I2C error
+// TODO(EH1): Tweak error types to match EH
 #[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[non_exhaustive]
@@ -62,6 +64,19 @@ pub enum Error {
     // Timeout, // SMBUS mode only
     // Alert, // SMBUS mode only
 }
+impl hal::i2c::Error for Error {
+    fn kind(&self) -> hal::i2c::ErrorKind {
+        use hal::i2c::{ErrorKind, NoAcknowledgeSource};
+
+        match self {
+            Error::Bus => ErrorKind::Bus,
+            Error::Arbitration => ErrorKind::ArbitrationLoss,
+            Error::NotAcknowledge => {
+                ErrorKind::NoAcknowledge(NoAcknowledgeSource::Unknown)
+            }
+        }
+    }
+}
 
 /// A trait to represent the SCL Pin of an I2C Port
 pub trait PinScl<I2C> {}
@@ -474,9 +489,8 @@ macro_rules! i2c {
 
                 /// Master restart
                 ///
-                /// Performs an I2C restart following a write phase and prepare
-                /// to receive `length` bytes. The I2C peripheral is configured
-                /// to provide an automatic stop.
+                /// Performs an I2C restart following a write phase and prepares
+                /// to receive `length` bytes.
                 ///
                 /// ```
                 /// Master: ...  SR  SAD+R  ...  (SP)
@@ -486,15 +500,15 @@ macro_rules! i2c {
                     assert!(length < 256 && length > 0);
 
                     self.i2c.cr2.write(|w| {
-                        w.sadd()
+                        w.start()
+                            .set_bit()
+                            .sadd()
                             .bits(u16(addr << 1 | 1))
                             .add10().clear_bit()
                             .rd_wrn()
                             .read()
                             .nbytes()
                             .bits(length as u8)
-                            .start()
-                            .set_bit()
                             .autoend()
                             .bit(stop == Stop::Automatic)
                     });
@@ -511,6 +525,97 @@ macro_rules! i2c {
                 pub fn master_stop(&mut self) {
                     self.i2c.cr2.write(|w| w.stop().set_bit());
                 }
+
+                /// Internal implementation for I2C transaction
+                fn master_read_bytes(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
+                    for byte in buffer {
+                        // Wait until we have received something
+                        busy_wait!(self.i2c, rxne, is_not_empty);
+
+                        *byte = self.i2c.rxdr.read().rxdata().bits();
+                    }
+                    Ok(())
+                }
+                /// Internal implementation for I2C transaction
+                fn master_write_bytes(&mut self, buffer: &[u8]) -> Result<(), Error> {
+                    for byte in buffer {
+                        // Wait until we are allowed to send data (START has
+                        // been ACKed or last byte when through)
+                        busy_wait!(self.i2c, txis, is_empty);
+
+                        // Put byte on the wire
+                        self.i2c.txdr.write(|w| w.txdata().bits(*byte));
+                    }
+
+                    // Wait until the write finishes
+                    busy_wait!(self.i2c, tc, is_complete);
+
+                    Ok(())
+                }
+                /// Internal implementation for I2C transaction
+                fn software_stop_and_wait(&mut self) -> Result<(), Error> {
+                    // Stop
+                    self.master_stop();
+
+                    // Wait for stop
+                    busy_wait!(self.i2c, busy, is_not_busy);
+                    Ok(())
+                }
+            }
+
+            impl hal::i2c::ErrorType for I2c<$I2CX> {
+                type Error = Error;
+            }
+            impl hal::i2c::I2c<SevenBitAddress> for I2c<$I2CX> {
+                fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>])
+                               -> Result<(), Self::Error>
+                {
+                    let mut ops = operations.iter_mut();
+
+                    if let Some(mut prev_op) = ops.next() {
+                        // Generate start ST
+                        match &prev_op {
+                            Operation::Read(rb) => self.master_read(addr, rb.len(), Stop::Software),
+                            Operation::Write(wb) => self.master_write(addr, wb.len(), Stop::Software),
+                        };
+
+                        // And execute operation
+                        match &mut prev_op {
+                            Operation::Read(rb) => self.master_read_bytes(rb)?,
+                            Operation::Write(wb) => self.master_write_bytes(wb)?,
+                        };
+
+                        for op in ops {
+                            // If operation type changes we must generate SR and SAD+R/W
+                            match (&prev_op, &op) {
+                                (Operation::Read(_), Operation::Write(wb)) => {
+                                    // SR  SAD+W
+                                    self.master_write(addr, wb.len(), Stop::Software);
+                                }
+                                (Operation::Write(_), Operation::Read(rb)) => {
+                                    // Wait until the write finishes before beginning to read
+                                    busy_wait!(self.i2c, tc, is_complete);
+
+                                    // SR  SAD+R
+                                    self.master_re_start(addr, rb.len(), Stop::Software);
+                                },
+                                _ => {}
+                            }
+                            prev_op = op;
+
+                            // Execute operation
+                            match &mut prev_op {
+                                Operation::Read(rb) => self.master_read_bytes(rb)?,
+                                Operation::Write(wb) => self.master_write_bytes(wb)?,
+                            };
+                        }
+
+                        // Generate SP
+                        self.software_stop_and_wait()?;
+                    }
+                    // Fallthrough is success
+                    Ok(())
+                }
             }
 
             impl I2cExt<$I2CX> for $I2CX {
@@ -557,116 +662,148 @@ macro_rules! i2c {
                 }
             }
 
-            impl Write for I2c<$I2CX> {
-                type Error = Error;
-
-                fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
-                    // TODO support transfers of more than 255 bytes
-                    assert!(bytes.len() < 256 && bytes.len() > 0);
+            // impl Write for I2c<$I2CX> {
+            //     type Error = Error;
 
-                    // I2C start
-                    //
-                    // ST SAD+W
-                    self.master_write(addr, bytes.len(), Stop::Software);
+            //     fn try_write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
+            //         // TODO support transfers of more than 255 bytes
+            //         assert!(bytes.len() < 256 && bytes.len() > 0);
 
-                    for byte in bytes {
-                        // Wait until we are allowed to send data
-                        // (START has been ACKed or last byte when
-                        // through)
-                        busy_wait!(self.i2c, txis, is_empty);
+            //         // I2C start
+            //         //
+            //         // ST SAD+W
+            //         self.master_write(addr, bytes.len(), Stop::Software);
 
-                        // Put byte on the wire
-                        self.i2c.txdr.write(|w| w.txdata().bits(*byte));
-                    }
-
-                    // Wait until the write finishes
-                    busy_wait!(self.i2c, tc, is_complete);
+            //         for byte in bytes {
+            //             // Wait until we are allowed to send data
+            //             // (START has been ACKed or last byte when
+            //             // through)
+            //             busy_wait!(self.i2c, txis, is_empty);
 
-                    // Stop
-                    self.master_stop();
+            //             // Put byte on the wire
+            //             self.i2c.txdr.write(|w| w.txdata().bits(*byte));
+            //         }
+
+            //         // Wait until the write finishes
+            //         busy_wait!(self.i2c, tc, is_complete);
+
+            //         // Stop
+            //         self.master_stop();
+
+            //         // Wait for stop
+            //         busy_wait!(self.i2c, busy, is_not_busy);
+
+            //         Ok(())
+            //     }
+            // }
 
-                    // Wait for stop
-                    busy_wait!(self.i2c, busy, is_not_busy);
 
-                    Ok(())
-                }
-            }
 
-            impl WriteRead for I2c<$I2CX> {
-                type Error = Error;
 
-                fn write_read(
-                    &mut self,
-                    addr: u8,
-                    bytes: &[u8],
-                    buffer: &mut [u8],
-                ) -> Result<(), Error> {
-                    // TODO support transfers of more than 255 bytes
-                    assert!(bytes.len() < 256 && bytes.len() > 0);
-                    assert!(buffer.len() < 256 && buffer.len() > 0);
-
-                    // I2C start
-                    //
-                    // ST SAD+W
-                    self.master_write(addr, bytes.len(), Stop::Software);
-
-                    for byte in bytes {
-                        // Wait until we are allowed to send data
-                        // (START has been ACKed or last byte went through)
-                        busy_wait!(self.i2c, txis, is_empty);
 
-                        // Put byte on the wire
-                        self.i2c.txdr.write(|w| w.txdata().bits(*byte));
-                    }
+            //         // TODO support transfers of more than 255 bytes
+            //         assert!(bytes.len() < 256 && bytes.len() > 0);
+            //         assert!(buffer.len() < 256 && buffer.len() > 0);
 
-                    // Wait until the write finishes before beginning to read.
-                    busy_wait!(self.i2c, tc, is_complete);
+            //         // I2C start
+            //         //
+            //         // ST SAD+W
+            //         self.master_write(addr, bytes.len(), Stop::Software);
 
-                    // I2C re-start
-                    //
-                    // SR  SAD+R
-                    self.master_re_start(addr, buffer.len(), Stop::Automatic);
+            //         for byte in bytes {
+            //             // Wait until we are allowed to send data
+            //             // (START has been ACKed or last byte went through)
+            //             busy_wait!(self.i2c, txis, is_empty);
 
-                    for byte in buffer {
-                        // Wait until we have received something
-                        busy_wait!(self.i2c, rxne, is_not_empty);
+            //             // Put byte on the wire
+            //             self.i2c.txdr.write(|w| w.txdata().bits(*byte));
+            //         }
 
-                        *byte = self.i2c.rxdr.read().rxdata().bits();
-                    }
+            //         // Wait until the write finishes before beginning to read.
+            //         busy_wait!(self.i2c, tc, is_complete);
 
-                    // Wait for automatic stop
-                    busy_wait!(self.i2c, busy, is_not_busy);
+            //         // I2C re-start
+            //         //
+            //         // SR  SAD+R
+            //         self.master_re_start(addr, buffer.len(), Stop::Automatic);
 
-                    Ok(())
-                }
-            }
+            //         for byte in buffer {
+            //             // Wait until we have received something
+            //             busy_wait!(self.i2c, rxne, is_not_empty);
 
-            impl Read for I2c<$I2CX> {
-                type Error = Error;
+            //             *byte = self.i2c.rxdr.read().rxdata().bits();
+            //         }
 
-                fn read(
-                    &mut self,
-                    addr: u8,
-                    buffer: &mut [u8],
-                ) -> Result<(), Error> {
-                    // TODO support transfers of more than 255 bytes
-                    assert!(buffer.len() < 256 && buffer.len() > 0);
+            //         // Wait for automatic stop
+            //         busy_wait!(self.i2c, busy, is_not_busy);
 
-                    self.master_read(addr, buffer.len(), Stop::Automatic);
+            //         Ok(())
+            //     }
+            // }
 
-                    for byte in buffer {
-                        // Wait until we have received something
-                        busy_wait!(self.i2c, rxne, is_not_empty);
+            // impl Read for I2c<$I2CX> {
+            //     type Error = Error;
 
-                        *byte = self.i2c.rxdr.read().rxdata().bits();
-                    }
+            //     fn try_read(
+            //         &mut self,
+            //         addr: u8,
+            //         buffer: &mut [u8],
+            //     ) -> Result<(), Error> {
+            //         // TODO support transfers of more than 255 bytes
+            //         assert!(buffer.len() < 256 && buffer.len() > 0);
 
-                    // Wait for automatic stop
-                    busy_wait!(self.i2c, busy, is_not_busy);
+            //         // Wait for any previous address sequence to end
+            //         // automatically. This could be up to 50% of a bus
+            //         // cycle (ie. up to 0.5/freq)
+            //         while self.i2c.cr2.read().start().bit_is_set() {};
 
-                    Ok(())
-                }
-            }
+            //         // Set START and prepare to receive bytes into
+            //         // `buffer`. The START bit can be set even if the bus
+            //         // is BUSY or I2C is in slave mode.
+            //         self.i2c.cr2.write(|w| {
+            //             w.sadd()
+            //                 .bits((addr << 1 | 0) as u16)
+            //                 .rd_wrn()
+            //                 .read()
+            //                 .nbytes()
+            //                 .bits(buffer.len() as u8)
+            //                 .start()
+            //                 .set_bit()
+            //                 .autoend()
+            //                 .automatic()
+            //         });
+
+            //         for byte in buffer {
+            //             // Wait until we have received something
+            //             busy_wait!(self.i2c, rxne, is_not_empty);
+
+            //             *byte = self.i2c.rxdr.read().rxdata().bits();
+            //         }
+            //     }
+
+            //     fn read(
+            //         &mut self,
+            //         addr: u8,
+            //         buffer: &mut [u8],
+            //     ) -> Result<(), Error> {
+            //         // TODO support transfers of more than 255 bytes
+            //         assert!(buffer.len() < 256 && buffer.len() > 0);
+
+            //         self.master_read(addr, buffer.len(), Stop::Automatic);
+
+            //         for byte in buffer {
+            //             // Wait until we have received something
+            //             busy_wait!(self.i2c, rxne, is_not_empty);
+
+            //             *byte = self.i2c.rxdr.read().rxdata().bits();
+            //         }
+
+            //         // Wait for automatic stop
+            //         busy_wait!(self.i2c, busy, is_not_busy);
+
+            //         Ok(())
+            //     }
+            // }
         )+
     };
 }
diff --git a/src/lib.rs b/src/lib.rs
index 299a33db..17b83946 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -81,7 +81,7 @@ compile_error!(
 "
 );
 
-pub use embedded_hal as hal;
+pub use embedded_hal_1 as hal;
 pub mod traits;
 
 pub use nb;
diff --git a/src/prelude.rs b/src/prelude.rs
index d873702c..2d5fcac0 100644
--- a/src/prelude.rs
+++ b/src/prelude.rs
@@ -1,5 +1,4 @@
 //! Prelude
-pub use embedded_hal::prelude::*;
 
 pub use crate::adc::AdcExt as _stm32h7xx_hal_adc_AdcExt;
 #[cfg(feature = "can")]
diff --git a/src/pwm.rs b/src/pwm.rs
index ef6baae0..75a58523 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -300,6 +300,23 @@ pub trait FaultMonitor {
     fn set_fault(&mut self);
 }
 
+/// Error type for PWM
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[non_exhaustive]
+pub enum PwmError {
+    /// Error
+    Error,
+    /// Failure because the PWM channel was not enabled
+    NotEnabled,
+}
+impl hal::pwm::Error for PwmError {
+    fn kind(&self) -> hal::pwm::ErrorKind {
+        use hal::pwm::ErrorKind;
+
+        ErrorKind::Other
+    }
+}
+
 /// Exposes timer wide advanced features, such as [FaultMonitor](trait.FaultMonitor.html)
 /// or future features like trigger outputs for synchronization with ADCs and other peripherals
 pub struct PwmControl<TIM, FAULT> {
@@ -1021,8 +1038,9 @@ fn calculate_deadtime(base_freq: Hertz, deadtime: NanoSeconds) -> (u8, u8) {
     // Divide by 100000 then 10000 by multiplying and shifting
     // This can't overflow because both values being multiplied are u32
     let deadtime_ticks = deadtime.ticks() as u64 * base_freq.raw() as u64;
-    // Make sure we won't overflow when multiplying; DTG is max 1008 ticks and CKD is max prescaler of 4
-    // so deadtimes over 4032 ticks are impossible (4032*10^9 before dividing)
+    // Make sure we won't overflow when multiplying; DTG is max 1008 ticks and
+    // CKD is max prescaler of 4 so deadtimes over 4032 ticks are impossible
+    // (4032*10^9 before dividing)
     assert!(deadtime_ticks <= 4_032_000_000_000u64);
     let deadtime_ticks = deadtime_ticks * 42950;
     let deadtime_ticks = (deadtime_ticks >> 32) as u32;
@@ -1062,7 +1080,8 @@ fn calculate_deadtime(base_freq: Hertz, deadtime: NanoSeconds) -> (u8, u8) {
 pub trait PwmExt: Sized {
     type Rec: ResetEnable;
 
-    /// The requested frequency will be rounded to the nearest achievable frequency; the actual frequency may be higher or lower than requested.
+    /// The requested frequency will be rounded to the nearest achievable
+    /// frequency; the actual frequency may be higher or lower than requested.
     fn pwm<PINS, U, V>(
         self,
         _pins: PINS,
@@ -1136,10 +1155,14 @@ macro_rules! tim_hal {
                 let clk = <$TIMX>::get_clk(clocks)
                     .expect(concat!(stringify!($TIMX), ": Input clock not running!"));
 
-                let (period, prescale) = match $bits {
-                    16 => calculate_frequency_16bit(clk, freq, Alignment::Left),
-                    _ => calculate_frequency_32bit(clk, freq, Alignment::Left),
-                };
+                // let (period, prescale) = match $bits {
+                //     16 => calculate_frequency_16bit(clk, freq, Alignment::Left),
+                //     _ => calculate_frequency_32bit(clk, freq, Alignment::Left),
+                // };
+
+                // TODO(EH1): Only support ARR values up to 65535, even on
+                // 32-bit timers
+                let (period, prescale) = calculate_frequency_16bit(clk, freq, Alignment::Left);
 
                 // Write prescale
                 tim.psc.write(|w| { w.psc().bits(prescale as u16) });
@@ -1200,10 +1223,14 @@ macro_rules! tim_hal {
                     let (period, prescaler) = match self.count {
                         CountSettings::Explicit { period, prescaler } => (period as u32, prescaler),
                         CountSettings::Frequency( freq ) => {
-                            match $bits {
-                                16 => calculate_frequency_16bit(self.base_freq, freq, self.alignment),
-                                _ => calculate_frequency_32bit(self.base_freq, freq, self.alignment),
-                            }
+                            // match $bits {
+                            //     16 => calculate_frequency_16bit(self.base_freq, freq, self.alignment),
+                            //     _ => calculate_frequency_32bit(self.base_freq, freq, self.alignment),
+                            // }
+
+                            // TODO(EH1): Only support ARR values up to 65535,
+                            // even on 32-bit timers
+                            calculate_frequency_16bit(self.base_freq, freq, self.alignment)
                         },
                     };
 
@@ -1234,12 +1261,26 @@ macro_rules! tim_hal {
                             //  AOE = 0 -> after a fault, master output enable MOE can only be set by software, not automatically
                             //  BKE = 1 -> break is enabled
                             //  BKP = 0 for active low, 1 for active high
-                            // Safety: bkf is set to a constant value (1) that is a valid value for the field per the reference manual
-                            unsafe { tim.$bdtr.write(|w| w.dtg().bits(dtg).bkf().bits(1).aoe().clear_bit().bke().set_bit().bkp().bit(bkp).moe().$moe_set()); }
+                            //
+                            // Safety: bkf is set to a constant value (1) that
+                            // is a valid value for the field per the reference
+                            // manual
+                            unsafe {
+                                tim.$bdtr.write(|w| w
+                                                .dtg().bits(dtg)
+                                                .bkf().bits(1)
+                                                .aoe().clear_bit()
+                                                .bke().set_bit()
+                                                .bkp().bit(bkp)
+                                                .moe().$moe_set());
+                            }
 
                             // AF1:
                             //  BKINE = 1 -> break input enabled
-                            //  BKINP should make input active high (BDTR BKP will set polarity), bit value varies timer to timer
+                            //
+                            //  BKINP should make input active high (BDTR BKP
+                            //  will set polarity), bit value varies timer to
+                            //  timer
                             tim.$af1.write(|w| w.bkine().set_bit().bkinp().$bkinp_setting());
                         }
                         $(
@@ -1250,17 +1291,31 @@ macro_rules! tim_hal {
                                 //  AOE = 0 -> after a fault, master output enable MOE can only be set by software, not automatically
                                 //  BK2E = 1 -> break is enabled
                                 //  BK2P = 0 for active low, 1 for active high
-                                // Safety: bkf is set to a constant value (1) that is a valid value for the field per the reference manual
-                                unsafe { tim.$bdtr.write(|w| w.dtg().bits(dtg).bk2f().bits(1).aoe().clear_bit().bk2e().set_bit().bk2p().bit(bkp).moe().$moe_set()); }
+                                //
+                                // Safety: bkf is set to a constant value (1)
+                                // that is a valid value for the field per the
+                                // reference manual
+                                unsafe { tim.$bdtr.write(|w| w
+                                                         .dtg().bits(dtg)
+                                                         .bk2f().bits(1)
+                                                         .aoe().clear_bit()
+                                                         .bk2e().set_bit()
+                                                         .bk2p().bit(bkp)
+                                                         .moe().$moe_set());
+                                }
 
                                 // AF1:
                                 //  BKINE = 1 -> break input enabled
-                                //  BKINP should make input active high (BDTR BKP will set polarity), bit value varies timer to timer
+                                //
+                                //  BKINP should make input active high (BDTR
+                                //  BKP will set polarity), bit value varies
+                                //  timer to timer
                                 tim.af2.write(|w| w.bk2ine().set_bit().bk2inp().$bk2inp_setting());
                             }
                         )?
                         else {
-                            // Safety: the DTG field of BDTR allows any 8-bit deadtime value and the dtg variable is u8
+                            // Safety: the DTG field of BDTR allows any 8-bit
+                            // deadtime value and the dtg variable is u8
                             unsafe {
                                 tim.$bdtr.write(|w| w.dtg().bits(dtg).aoe().clear_bit().moe().$moe_set());
                             }
@@ -1329,8 +1384,10 @@ macro_rules! tim_hal {
                     /// Set the deadtime for complementary PWM channels of this timer
                     #[must_use]
                     pub fn with_deadtime<T: Into<NanoSeconds>>(mut self, deadtime: T) -> Self {
-                        // $bdtr is an Ident that only exists for timers with deadtime, so we can use it as a variable name to
-                        // only implement this method for timers that support deadtime.
+                        // $bdtr is an Ident that only exists for timers with
+                        // deadtime, so we can use it as a variable name to only
+                        // implement this method for timers that support
+                        // deadtime.
                         let $bdtr = deadtime.into();
 
                         self.deadtime = $bdtr;
@@ -1346,12 +1403,15 @@ macro_rules! tim_hal {
                     self
                 }
 
-                // Timers with advanced counting options, including center aligned and right aligned PWM
+                // Timers with advanced counting options, including center
+                // aligned and right aligned PWM
                 $(
                     #[must_use]
                     pub fn center_aligned(mut self) -> Self {
-                        // $cms is an Ident that only exists for timers with center/right aligned PWM, so we can use it as a variable name to
-                        // only implement this method for timers that support center/right aligned PWM.
+                        // $cms is an Ident that only exists for timers with
+                        // center/right aligned PWM, so we can use it as a
+                        // variable name to only implement this method for
+                        // timers that support center/right aligned PWM.
                         let $cms = Alignment::Center;
 
                         self.alignment = $cms;
@@ -1371,9 +1431,12 @@ macro_rules! tim_hal {
             // Timers with break/fault, dead time, and complimentary capabilities
             $(
                 impl<PINS, CHANNEL, COMP> PwmBuilder<$TIMX, PINS, CHANNEL, FaultDisabled, COMP, $typ> {
-                    /// Configure a break pin that will disable PWM when activated (active level based on polarity argument)
-                    /// Note: not all timers have fault inputs; `FaultPins<TIM>` is only implemented for valid pins/timers.
-                    pub fn with_break_pin<P: FaultPins<$TIMX>>(self, _pin: P, polarity: Polarity) -> PwmBuilder<$TIMX, PINS, CHANNEL, FaultEnabled, COMP, $typ> {
+                    /// Configure a break pin that will disable PWM when
+                    /// activated (active level based on polarity argument)
+                    /// Note: not all timers have fault inputs; `FaultPins<TIM>`
+                    /// is only implemented for valid pins/timers.
+                    pub fn with_break_pin<P: FaultPins<$TIMX>>(self, _pin: P, polarity: Polarity)
+                                                               -> PwmBuilder<$TIMX, PINS, CHANNEL, FaultEnabled, COMP, $typ> {
                         PwmBuilder {
                             _markers: PhantomData,
                             alignment: self.alignment,
@@ -1440,53 +1503,52 @@ pub trait PwmPinEnable {
     fn ccer_disable(&mut self);
 }
 
-// Implement PwmPin for timer channels
+// Implement SetDutyCycle for timer channels
 macro_rules! tim_pin_hal {
     // Standard pins (no complementary functionality)
     ($TIMX:ty, $typ:ty: $(
        ($CH:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident),)+
     ) => {
         $(
-            impl<COMP> hal::PwmPin for Pwm<$TIMX, $CH, COMP>
+            impl<COMP> hal::pwm::ErrorType for Pwm<$TIMX, $CH, COMP>
+                where Pwm<$TIMX, $CH, COMP>: PwmPinEnable
+            {
+                type Error = PwmError;
+            }
+
+             impl<COMP> hal::pwm::SetDutyCycle for Pwm<$TIMX, $CH, COMP>
                 where Pwm<$TIMX, $CH, COMP>: PwmPinEnable {
-                type Duty = $typ;
 
-                // You may not access self in the following methods!
-                // See unsafe above
+                // type Duty = $typ;
+                // type Error = Infallible;
 
-                fn disable(&mut self) {
-                    self.ccer_disable();
-                }
 
-                fn enable(&mut self) {
-                    let tim = unsafe { &*<$TIMX>::ptr() };
+                // fn try_get_max_duty(&self) -> Result<Self::Duty, Self::Error> {
+                //     let tim = unsafe { &*<$TIMX>::ptr() };
 
-                    tim.$ccmrx_output().modify(|_, w|
-                        w.$ocxpe()
-                            .enabled() // Enable preload
-                            .$ocxm()
-                            .pwm_mode1() // PWM Mode
-                    );
-
-                    self.ccer_enable();
-                }
+                //     let arr = tim.arr.read().arr().bits();
 
-                fn get_duty(&self) -> Self::Duty {
-                    let tim = unsafe { &*<$TIMX>::ptr() };
-
-                    tim.ccr[$CH as usize].read().ccr().bits()
-                }
+                //     // One PWM cycle is ARR+1 counts long
+                //     // Valid PWM duty cycles are 0 to ARR+1
+                //     // However, if ARR is 65535 on a 16-bit timer, we can't add 1
+                //     // In that case, 100% duty cycle is not possible, only 65535/65536
+                //     if arr == Self::Duty::MAX {
+                //         Ok(arr)
+                //     }
+                //     else {
+                //         Ok(arr + 1)
+                //     }
+                // }
 
-                fn get_max_duty(&self) -> Self::Duty {
+                fn max_duty_cycle(&self) -> u16 {
                     let tim = unsafe { &*<$TIMX>::ptr() };
-
-                    let arr = tim.arr.read().arr().bits();
+                    let arr = tim.arr.read().arr().bits() as u16;
 
                     // One PWM cycle is ARR+1 counts long
                     // Valid PWM duty cycles are 0 to ARR+1
                     // However, if ARR is 65535 on a 16-bit timer, we can't add 1
                     // In that case, 100% duty cycle is not possible, only 65535/65536
-                    if arr == Self::Duty::MAX {
+                    if arr == u16::MAX {
                         arr
                     }
                     else {
@@ -1494,13 +1556,46 @@ macro_rules! tim_pin_hal {
                     }
                 }
 
-                fn set_duty(&mut self, duty: Self::Duty) {
+                fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
                     let tim = unsafe { &*<$TIMX>::ptr() };
 
-                    tim.ccr[$CH as usize].write(|w| w.ccr().bits(duty));
+                    tim.ccr[$CH as usize].write(|w| w.ccr().bits(duty as $typ));
+
+                    Ok(())
                 }
             }
 
+            impl<COMP> Pwm<$TIMX, $CH, COMP>
+                where Pwm<$TIMX, $CH, COMP>: PwmPinEnable
+            {
+                /// Disable a PWM channel
+                pub fn disable(&mut self) -> Result<(), PwmError> {
+                    self.ccer_disable();
+                    Ok(())
+                }
+
+                /// Enables a PWM channel
+                pub fn enable(&mut self) -> Result<(), PwmError> {
+                    let tim = unsafe { &*<$TIMX>::ptr() };
+
+                    tim.$ccmrx_output().modify(|_, w|
+                                               w.$ocxpe()
+                                               .enabled() // Enable preload
+                                               .$ocxm()
+                                               .pwm_mode1() // PWM Mode
+                    );
+
+                    self.ccer_enable();
+                    Ok(())
+                }
+
+                /// Returns the current duty cycle
+                pub fn get_duty(&self) -> Result<$typ, PwmError> {
+                    let tim = unsafe { &*<$TIMX>::ptr() };
+
+                    Ok(tim.ccr[$CH as usize].read().ccr().bits())
+                }
+            }
         )+
 
         // Enable implementation for ComplementaryImpossible
@@ -1517,7 +1612,6 @@ macro_rules! tim_pin_hal {
             }
         }
 
-
         impl<const C: u8, COMP> Pwm<$TIMX, C, COMP> {
             pub fn set_polarity(&mut self, pol: Polarity) {
                 let tim = unsafe { &*<$TIMX>::ptr() };
@@ -1760,45 +1854,56 @@ macro_rules! lptim_hal {
                 PINS::split()
             }
 
-            impl hal::PwmPin for Pwm<$TIMX, C1, ComplementaryImpossible> {
-                type Duty = u16;
-
-                // You may not access self in the following methods!
-                // See unsafe above
+            impl hal::pwm::ErrorType for Pwm<$TIMX, C1, ComplementaryImpossible> {
+                type Error = PwmError;
+            }
 
-                fn disable(&mut self) {
+            impl hal::pwm::SetDutyCycle for Pwm<$TIMX, C1, ComplementaryImpossible> {
+                fn max_duty_cycle(&self) -> u16 {
                     let tim = unsafe { &*<$TIMX>::ptr() };
 
-                    // LPTIM only has one output, so we disable the
-                    // entire timer
-                    tim.cr.modify(|_, w| w.enable().disabled());
+                    tim.arr.read().arr().bits()
                 }
-
-                fn enable(&mut self) {
+                fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
                     let tim = unsafe { &*<$TIMX>::ptr() };
 
-                    tim.cr.modify(|_, w| w.enable().enabled());
-                    tim.cr.modify(|_, w| w.cntstrt().start());
+                    // LPTIM must be enabled to update CMP value
+                    if tim.cr.read().enable().bit_is_clear() {
+                        return Err(Self::Error::NotEnabled)
+                    }
+
+                    tim.cmp.write(|w| w.cmp().bits(duty));
+                    while !tim.isr.read().cmpok().is_set() {}
+                    tim.icr.write(|w| w.cmpokcf().clear());
+                    Ok(())
                 }
+            }
 
-                fn get_duty(&self) -> u16 {
+            impl Pwm<$TIMX, C1, ComplementaryImpossible> {
+                /// Disable a PWM channel
+                pub fn disable(&mut self) -> Result<(), PwmError>{
                     let tim = unsafe { &*<$TIMX>::ptr() };
 
-                    tim.cmp.read().cmp().bits()
+                    // LPTIM only has one output, so we disable the
+                    // entire timer. LPTIM only has one channel.
+                    tim.cr.modify(|_, w| w.enable().disabled());
+                    Ok(())
                 }
 
-                fn get_max_duty(&self) -> u16 {
+                /// Enables a PWM channel
+                pub fn enable(&mut self)->Result<(), PwmError> {
                     let tim = unsafe { &*<$TIMX>::ptr() };
 
-                    tim.arr.read().arr().bits()
+                    tim.cr.modify(|_, w| w.enable().enabled());
+                    tim.cr.modify(|_, w| w.cntstrt().start());
+                    Ok(())
                 }
 
-                fn set_duty(&mut self, duty: u16) {
+                /// Returns the current duty cycle
+                pub fn get_duty(&self) -> Result<u16, PwmError> {
                     let tim = unsafe { &*<$TIMX>::ptr() };
 
-                    tim.cmp.write(|w| w.cmp().bits(duty));
-                    while !tim.isr.read().cmpok().is_set() {}
-                    tim.icr.write(|w| w.cmpokcf().clear());
+                    Ok(tim.cmp.read().cmp().bits())
                 }
             }
         )+
diff --git a/src/qei.rs b/src/qei.rs
index 6f8f27c8..d955969e 100644
--- a/src/qei.rs
+++ b/src/qei.rs
@@ -1,5 +1,5 @@
 //! # Quadrature Encoder Interface
-use crate::hal::{self, Direction};
+
 use crate::rcc::{rec, ResetEnable};
 
 use crate::gpio::{self, Alternate};
@@ -19,6 +19,11 @@ where
 {
 }
 
+pub enum Direction {
+    Downcounting,
+    Upcounting,
+}
+
 macro_rules! pins {
     ($($TIMX:ty:
        CH1: [$($( #[ $pmeta1:meta ] )* $CH1:ty),*]
@@ -196,6 +201,20 @@ macro_rules! tim_hal {
                 pub fn release(self) -> ($TIM, rec::$Rec) {
                     (self.tim, rec::$Rec { _marker: core::marker::PhantomData })
                 }
+
+                /// Returns the current pulse count of the encoder
+                pub fn count(&self) -> $bits {
+                    self.tim.cnt.read().bits() as $bits
+                }
+
+                /// Returns the count direction
+                pub fn direction(&self) -> Direction {
+                    if self.tim.cr1.read().dir().bit_is_clear() {
+                        Direction::Upcounting
+                    } else {
+                        Direction::Downcounting
+                    }
+                }
             }
 
             impl QeiExt<$TIM> for $TIM {
@@ -209,23 +228,6 @@ macro_rules! tim_hal {
                     Qei::$tim(self, prec)
                 }
             }
-
-            impl hal::Qei for Qei<$TIM> {
-                type Count = $bits;
-
-                fn count(&self) -> $bits {
-                    self.tim.cnt.read().bits() as $bits
-                }
-
-                fn direction(&self) -> Direction {
-                    if self.tim.cr1.read().dir().bit_is_clear() {
-                        hal::Direction::Upcounting
-                    } else {
-                        hal::Direction::Downcounting
-                    }
-                }
-            }
-
         )+
     }
 }
diff --git a/src/rng.rs b/src/rng.rs
index 8db9d0c1..aceda38c 100644
--- a/src/rng.rs
+++ b/src/rng.rs
@@ -7,7 +7,6 @@
 use core::cmp;
 use core::mem;
 
-use crate::hal::blocking::rng;
 use crate::rcc::{rec, rec::RngClkSel};
 use crate::rcc::{CoreClocks, ResetEnable};
 use crate::stm32::RNG;
@@ -116,14 +115,6 @@ impl core::iter::Iterator for Rng {
     }
 }
 
-impl rng::Read for Rng {
-    type Error = ErrorKind;
-
-    fn read(&mut self, buffer: &mut [u8]) -> Result<(), Self::Error> {
-        self.fill(buffer)
-    }
-}
-
 macro_rules! rng_core {
     ($($type:ty),+) => {
         $(
diff --git a/src/serial.rs b/src/serial.rs
index 2eee59e2..36366798 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -8,14 +8,14 @@
 //! - [Inverted Signal Levels](https://github.com/stm32-rs/stm32h7xx-hal/blob/master/examples/serial-inverted-loopback.rs)
 
 use core::cell::UnsafeCell;
-use core::fmt;
+use core::convert::Infallible;
 use core::marker::PhantomData;
 use core::ptr;
 
-use embedded_hal::blocking::serial as serial_block;
-use embedded_hal::prelude::*;
-use embedded_hal::serial;
-use nb::block;
+// use embedded_hal::blocking::serial as serial_block;
+// use embedded_hal::prelude::*;
+// use embedded_hal::serial;
+use embedded_io as eio;
 
 use stm32::usart1::cr2::{
     CLKEN_A, CPHA_A, CPOL_A, LBCL_A, MSBFIRST_A, RXINV_A, TXINV_A,
@@ -44,6 +44,8 @@ use crate::time::Hertz;
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[non_exhaustive]
 pub enum Error {
+    /// An attempted write could not write any data
+    WriteZero,
     /// Framing error
     Framing,
     /// Noise error
@@ -53,6 +55,14 @@ pub enum Error {
     /// Parity check error
     Parity,
 }
+impl eio::Error for Error {
+    fn kind(&self) -> eio::ErrorKind {
+        match self {
+            Error::WriteZero => eio::ErrorKind::WriteZero,
+            _ => eio::ErrorKind::Other,
+        }
+    }
+}
 
 /// Interrupt event
 #[derive(Copy, Clone, PartialEq, Eq)]
@@ -964,22 +974,60 @@ macro_rules! usart {
                 }
             }
 
-            impl serial::Read<u8> for Serial<$USARTX> {
-                type Error = Error;
+            // Implement embedded_io::Write
 
-                fn read(&mut self) -> nb::Result<u8, Error> {
+            impl eio::ErrorType for Serial<$USARTX> {
+                type Error = Error;
+            }
+            impl eio::Read for Serial<$USARTX> {
+                fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
                     let mut rx: Rx<$USARTX> = Rx {
                         _usart: PhantomData,
                         ker_ck: self.ker_ck,
                     };
-                    rx.read()
+                    rx.read(buf)
                 }
             }
-
-            impl serial::Read<u8> for Rx<$USARTX> {
+            impl eio::ErrorType for Rx<$USARTX> {
                 type Error = Error;
+            }
+            impl eio::Read for Rx<$USARTX> {
+                fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
+                    for (i, byte) in buf.iter_mut().enumerate() {
+                        while true {
+                            match self.read_byte() {
+                                Ok(b) => {
+                                    *byte = b;
+                                    continue;
+                                },
+                                Err(nb::Error::WouldBlock) => {
+                                    if i > 0 {
+                                        return Ok(i);
+                                    }
+                                },
+                                Err(nb::Error::Other(e)) => {
+                                    return Err(e);
+                                }
+                            }
+                        }
+                    }
+                    Ok(buf.len())
+                }
+            }
 
-                fn read(&mut self) -> nb::Result<u8, Error> {
+            impl Serial<$USARTX> {
+                /// Reads a single word from the serial interface
+                pub fn read_byte(&mut self) -> nb::Result<u8, Error> {
+                    let mut rx: Rx<$USARTX> = Rx {
+                        _usart: PhantomData,
+                        ker_ck: self.ker_ck,
+                    };
+                    rx.read_byte()
+                }
+            }
+            impl Rx<$USARTX> {
+                /// Reads a single word from the serial interface
+                pub fn read_byte(&mut self) -> nb::Result<u8, Error> {
                     // NOTE(unsafe) atomic read with no side effects
                     let isr = unsafe { (*$USARTX::ptr()).isr.read() };
 
@@ -1004,9 +1052,7 @@ macro_rules! usart {
                         nb::Error::WouldBlock
                     })
                 }
-            }
 
-            impl Rx<$USARTX> {
                 /// Start listening for `Rxne` event
                 pub fn listen(&mut self) {
                     // unsafe: rxneie bit accessed by Rx part only
@@ -1064,49 +1110,66 @@ macro_rules! usart {
                 }
             }
 
-            impl serial::Write<u8> for Serial<$USARTX> {
-                type Error = core::convert::Infallible;
+            // Implement embedded_io::Write
 
-                fn flush(&mut self) -> nb::Result<(), Self::Error> {
+            impl eio::Write for Serial<$USARTX> {
+                fn flush(&mut self) -> Result<(), Error> {
                     let mut tx: Tx<$USARTX> = Tx {
                         _usart: PhantomData,
                     };
                     tx.flush()
                 }
-
-                fn write(&mut self, byte: u8) -> nb::Result<(), Self::Error> {
+                fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
                     let mut tx: Tx<$USARTX> = Tx {
                         _usart: PhantomData,
                     };
-                    tx.write(byte)
+                    tx.write(buf)
                 }
             }
+            impl eio::ErrorType for Tx<$USARTX> {
+                type Error = Error;
+            }
+            impl eio::Write for Tx<$USARTX> {
+                fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
+                    for (i, byte) in buf.iter().enumerate() {
+                        if self.write_byte(*byte).is_ok() {
+                            continue;
+                        } else if i == 0 {
+                            return Err(Error::WriteZero);
+                        } else {
+                            return Ok(i);
+                        }
+                    }
+                    Ok(buf.len())
+                }
+                fn flush(&mut self) -> Result<(), Error> {
+                    // NOTE(unsafe) atomic read with no side effects
+                    let isr = unsafe { (*$USARTX::ptr()).isr.read() };
 
-            impl serial_block::write::Default<u8> for Serial<$USARTX> {
-                //implement marker trait to opt-in to default blocking write implementation
+                    while !isr.tc().bit_is_set() {}
+                    Ok(())
+                }
             }
 
-            impl serial::Write<u8> for Tx<$USARTX> {
+            impl Serial<$USARTX> {
+                /// Writes a single word to the serial interface
+                pub fn write_byte(&mut self, byte: u8) -> nb::Result<(), Infallible> {
+                    let mut tx: Tx<$USARTX> = Tx {
+                        _usart: PhantomData,
+                    };
+                    tx.write_byte(byte)
+                }
+            }
+            impl Tx<$USARTX> {
                 // NOTE(Void) See section "29.7 USART interrupts"; the
                 // only possible errors during transmission are: clear
                 // to send (which is disabled in this case) errors and
                 // framing errors (which only occur in SmartCard
                 // mode); neither of these apply to our hardware
                 // configuration
-                type Error = core::convert::Infallible;
-
-                fn flush(&mut self) -> nb::Result<(), Self::Error> {
-                    // NOTE(unsafe) atomic read with no side effects
-                    let isr = unsafe { (*$USARTX::ptr()).isr.read() };
-
-                    if isr.tc().bit_is_set() {
-                        Ok(())
-                    } else {
-                        Err(nb::Error::WouldBlock)
-                    }
-                }
 
-                fn write(&mut self, byte: u8) -> nb::Result<(), Self::Error> {
+                /// Writes a single word to the serial interface
+                pub fn write_byte(&mut self, byte: u8) -> nb::Result<(), Infallible> {
                     // NOTE(unsafe) atomic read with no side effects
                     let isr = unsafe { (*$USARTX::ptr()).isr.read() };
 
@@ -1124,9 +1187,7 @@ macro_rules! usart {
                         Err(nb::Error::WouldBlock)
                     }
                 }
-            }
 
-            impl Tx<$USARTX> {
                 /// Start listening for `Txe` event
                 pub fn listen(&mut self) {
                     // unsafe: txeie bit accessed by Tx part only
@@ -1294,23 +1355,3 @@ usart_sel! {
     UART8: "UART8",
     UART7: "UART7",
 }
-
-impl<USART> fmt::Write for Tx<USART>
-where
-    Tx<USART>: serial::Write<u8>,
-{
-    fn write_str(&mut self, s: &str) -> fmt::Result {
-        let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last();
-        Ok(())
-    }
-}
-
-impl<USART> fmt::Write for Serial<USART>
-where
-    Serial<USART>: serial::Write<u8>,
-{
-    fn write_str(&mut self, s: &str) -> fmt::Result {
-        let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last();
-        Ok(())
-    }
-}
diff --git a/src/spi.rs b/src/spi.rs
index 9754c038..959a69dd 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -68,7 +68,6 @@ use core::ptr;
 
 use crate::gpio::{self, Alternate};
 use crate::hal;
-use crate::hal::spi::FullDuplex;
 pub use crate::hal::spi::{
     Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3,
 };
@@ -106,6 +105,17 @@ pub enum Error {
     /// the SPI master fails to receive its own clock on the CLK pin
     DuplexFailed,
 }
+impl hal::spi::Error for Error {
+    fn kind(&self) -> hal::spi::ErrorKind {
+        use hal::spi::ErrorKind;
+
+        match self {
+            Error::Overrun => ErrorKind::Overrun,
+            Error::ModeFault => ErrorKind::ModeFault,
+            _ => ErrorKind::Other,
+        }
+    }
+}
 
 /// Enabled SPI peripheral (type state)
 pub struct Enabled;
@@ -556,8 +566,7 @@ pub trait SpiExt<SPI, WORD>: Sized {
         CONFIG: Into<Config>;
 }
 
-pub trait HalEnabledSpi:
-    HalSpi + FullDuplex<Self::Word, Error = Error>
+pub trait HalEnabledSpi: HalSpi // + FullDuplex<Self::Word, Error = Error>
 {
     type Disabled: HalDisabledSpi<
         Spi = Self::Spi,
@@ -1058,10 +1067,12 @@ macro_rules! spi {
 	                }
 	            }
 
-                impl hal::spi::FullDuplex<$TY> for Spi<$SPIX, Enabled, $TY> {
-                    type Error = Error;
-
-                    fn read(&mut self) -> nb::Result<$TY, Error> {
+                impl Spi<$SPIX, Enabled, $TY> {
+                    /// Reads the word stored in the shift register.
+                    ///
+                    /// NOTE: A word must be sent to the slave before attempting
+                    /// to call this method
+                    pub fn read(&mut self) -> nb::Result<$TY, Error> {
                         check_status_error!(self.spi;
                         {    // } else if sr.rxp().is_not_empty() {
                             rxp, is_not_empty,
@@ -1076,7 +1087,8 @@ macro_rules! spi {
                         })
                     }
 
-                    fn send(&mut self, word: $TY) -> nb::Result<(), Error> {
+                    /// Sends a word to the slave
+                    pub fn send(&mut self, word: $TY) -> nb::Result<(), Error> {
                         check_status_error!(self.spi;
                         {    // } else if sr.txp().is_not_full() {
                             txp, is_not_full,
@@ -1171,10 +1183,16 @@ macro_rules! spi {
                         })
                     }
 
-                    /// Internal implementation for blocking::spi::Write
-                    fn transfer_internal_w(&mut self, write_words: &[$TY]) -> Result<(), Error> {
-                        use hal::spi::FullDuplex;
+                    /// Internal implementation for ensuring the current
+                    /// transaction is completed
+                    #[inline(always)]
+                    fn flush(&mut self) -> Result<(), Error> {
+                        while self.spi.sr.read().eot().is_completed() {}
+                        Ok(())
+                    }
 
+                    /// Internal implementation for Write-only transfers
+                    fn transfer_internal_w(&mut self, write_words: &[$TY]) -> Result<(), Error> {
                         // both buffers are the same length
                         if write_words.is_empty() {
                             return Ok(());
@@ -1229,10 +1247,67 @@ macro_rules! spi {
                         Ok(())
                     }
 
-                    /// Internal implementation for blocking::spi::Transfer
-                    fn transfer_internal_rw(&mut self, words : &mut [$TY]) -> Result<(), Error> {
-                        use hal::spi::FullDuplex;
+                    /// Internal implementation for Read Write transfers
+                    fn transfer_internal_rw(&mut self, read: &mut [$TY], write: &[$TY])
+                                            -> Result<(), Error> {
+                        if read.is_empty() | write.is_empty() {
+                            return Ok(());
+                        }
+                        let len = core::cmp::max(read.len(), write.len());
+
+                        // Are we in frame mode?
+                        if matches!(self.hardware_cs_mode, HardwareCSMode::FrameTransaction) {
+                            const MAX_WORDS: usize = 0xFFFF;
+
+                            // Can we send
+                            if len > MAX_WORDS {
+                                return Err(Error::BufferTooBig { max_size: MAX_WORDS });
+                            }
+
+                            // Setup that we're going to send this amount of bits
+                            // SAFETY: We already checked that `write_words` is not empty
+                            self.setup_transaction(unsafe {
+                                core::num::NonZeroU16::new_unchecked(len as u16)
+                            })?;
+                        }
+
+                        // Depth of FIFO to use. All current SPI implementations
+                        // have a FIFO depth of at least 8 (see RM0433 Rev 7
+                        // Table 409.) but pick 4 as a conservative value.
+                        const FIFO_WORDS: usize = 4;
+
+                        // Fill the first half of the write FIFO
+                        let mut write = write.into_iter();
+                        for _ in 0..core::cmp::min(FIFO_WORDS, len) {
+                            nb::block!(self.send(*write.next().unwrap_or(&0xFF)))?;
+                        }
+
+                        for i in FIFO_WORDS..len+FIFO_WORDS {
+                            let read_value = if i < len {
+                                // Continue filling write FIFO and emptying read FIFO
+                                nb::block!(
+                                    self.exchange_duplex_internal(*write.next().unwrap_or(&0xFF))
+                                )?
+                            } else {
+                                // Finish emptying the read FIFO
+                                nb::block!(self.read_duplex_internal())?
+                            };
+                            if i - FIFO_WORDS < read.len() {
+                                read[i - FIFO_WORDS] = read_value;
+                            }
+                        }
+
+                        // Are we in frame mode?
+                        if matches!(self.hardware_cs_mode, HardwareCSMode::FrameTransaction) {
+                            // Clean up
+                            self.end_transaction()?;
+                        }
+
+                        Ok(())
+                    }
 
+                    /// Internal implementation for in-place transfers
+                    fn transfer_internal_in_place(&mut self, words : &mut [$TY]) -> Result<(), Error> {
                         if words.is_empty() {
                             return Ok(());
                         }
@@ -1288,22 +1363,25 @@ macro_rules! spi {
                     }
                 }
 
-                impl hal::blocking::spi::Transfer<$TY> for Spi<$SPIX, Enabled, $TY> {
+                impl hal::spi::ErrorType for Spi<$SPIX, Enabled, $TY> {
                     type Error = Error;
-
-                    fn transfer<'w>(&mut self, words: &'w mut [$TY]) -> Result<&'w [$TY], Self::Error> {
-
-                        self.transfer_internal_rw(words)?;
-
-                        Ok(words)
-                    }
                 }
-                impl hal::blocking::spi::Write<$TY> for Spi<$SPIX, Enabled, $TY> {
-                    type Error = Error;
-
+                impl hal::spi::SpiBus<$TY> for Spi<$SPIX, Enabled, $TY> {
                     fn write(&mut self, words: &[$TY]) -> Result<(), Self::Error> {
                         self.transfer_internal_w(words)
                     }
+                    fn read(&mut self, words: &mut [$TY]) -> Result<(), Self::Error> {
+                        self.transfer_internal_rw(words, &[])
+                    }
+                    fn transfer(&mut self, read: &mut [$TY], write: &[$TY]) -> Result<(), Self::Error> {
+                        self.transfer_internal_rw(read, write)
+                    }
+                    fn transfer_in_place(&mut self, words: &mut [$TY]) -> Result<(), Self::Error> {
+                        self.transfer_internal_in_place(words)
+                    }
+                    fn flush(&mut self) -> Result<(), Self::Error> {
+                        self.flush()
+                    }
                 }
             )+
         )+
diff --git a/src/system_watchdog.rs b/src/system_watchdog.rs
index aec8eee0..69583413 100644
--- a/src/system_watchdog.rs
+++ b/src/system_watchdog.rs
@@ -18,7 +18,6 @@
 //!
 //! - [Example application](https://github.com/stm32-rs/stm32h7xx-hal/blob/master/examples/watchdog.rs)
 
-use crate::hal::watchdog::{Watchdog, WatchdogEnable};
 use crate::rcc::Ccdr;
 use crate::time::{Hertz, MilliSeconds};
 use cast::u8;
@@ -115,23 +114,22 @@ impl SystemWindowWatchdog {
     }
 }
 
-impl Watchdog for SystemWindowWatchdog {
+impl SystemWindowWatchdog {
     /// Feeds the watchdog in order to avoid a reset, only executes properly if the watchdog
     /// has already been started aka. the down_counter is not 0 anymore
-    fn feed(&mut self) {
+    pub fn feed(&mut self) {
         // if this value is 0 it is assumed that the watchdog has not yet been started
         assert!(self.down_counter != 0);
         self.wwdg.cr.modify(|_, w| w.t().bits(self.down_counter));
     }
 }
 
-impl WatchdogEnable for SystemWindowWatchdog {
-    type Time = MilliSeconds;
+impl SystemWindowWatchdog {
     /// Starts the watchdog with a given timeout period, if this period is out of bounds the function
     /// is going to panic
-    fn start<T>(&mut self, period: T)
+    pub fn start<T>(&mut self, period: T)
     where
-        T: Into<Self::Time>,
+        T: Into<MilliSeconds>,
     {
         let period_ms = period.into().ticks();
         let maximum =
diff --git a/src/timer.rs b/src/timer.rs
index 06d881d0..2a7903eb 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -8,10 +8,9 @@
 // TODO: on the h7x3 at least, only TIM2, TIM3, TIM4, TIM5 can support 32 bits.
 // TIM1 is 16 bit.
 
+use core::convert::Infallible;
 use core::marker::PhantomData;
 
-use crate::hal::timer::{CountDown, Periodic};
-
 use crate::stm32::{lptim1, lptim3};
 use crate::stm32::{LPTIM1, LPTIM2, LPTIM3};
 #[cfg(not(feature = "rm0455"))]
@@ -285,12 +284,9 @@ pub enum Event {
 macro_rules! hal {
     ($($TIMX:ident: ($timX:ident, $Rec:ident, $cntType:ty),)+) => {
         $(
-            impl Periodic for Timer<$TIMX> {}
-
-            impl CountDown for Timer<$TIMX> {
-                type Time = Hertz;
-
-                fn start<T>(&mut self, timeout: T)
+            impl Timer<$TIMX> {
+                /// Starts a new count down
+                pub fn start<T>(&mut self, timeout: T) -> Result<(), Infallible>
                 where
                     T: Into<Hertz>,
                 {
@@ -312,10 +308,12 @@ macro_rules! hal {
                     self.apply_freq();
 
                     // Start counter
-                    self.resume()
+                    self.resume();
+                    Ok(())
                 }
 
-                fn wait(&mut self) -> nb::Result<(), Void> {
+                /// Non-blockingly “waits” until the count down finishes
+                pub fn wait(&mut self) -> nb::Result<(), Infallible> {
                     if self.is_irq_clear() {
                         Err(nb::Error::WouldBlock)
                     } else {
@@ -332,7 +330,7 @@ macro_rules! hal {
                             prec: Self::Rec, clocks: &CoreClocks
                 ) -> Timer<$TIMX> {
                     let mut timer = Timer::$timX(self, prec, clocks);
-                    timer.start(timeout);
+                    timer.start(timeout).unwrap();
                     timer
                 }
 
@@ -606,12 +604,8 @@ hal! {
 macro_rules! lptim_hal {
     ($($TIMX:ident: ($timx:ident, $Rec:ident, $timXpac:ident),)+) => {
         $(
-            impl Periodic for LpTimer<$TIMX, Enabled> {}
-
-            impl CountDown for LpTimer<$TIMX, Enabled> {
-                type Time = Hertz;
-
-                fn start<T>(&mut self, timeout: T)
+            impl LpTimer<$TIMX, Enabled> {
+                pub fn start<T>(&mut self, timeout: T)
                 where
                     T: Into<Hertz>,
                 {
@@ -632,7 +626,7 @@ macro_rules! lptim_hal {
                     self.tim.cr.write(|w| w.cntstrt().set_bit().enable().enabled());
                 }
 
-                fn wait(&mut self) -> nb::Result<(), Void> {
+                pub fn wait(&mut self) -> nb::Result<(), Void> {
                     if self.tim.isr.read().arrm().bit_is_clear() {
                         Err(nb::Error::WouldBlock)
                     } else {