diff --git a/src/main/scala/arbiter/ArbiterTree.scala b/src/main/scala/arbiter/ArbiterTree.scala
index 6942063..311d81f 100644
--- a/src/main/scala/arbiter/ArbiterTree.scala
+++ b/src/main/scala/arbiter/ArbiterTree.scala
@@ -2,6 +2,7 @@ package arbiter
 
 import chisel3._
 import chisel3.util._
+import chisel3.experimental.ChiselEnum
 
 
 // Only one will be ready, as we cannot take two values
diff --git a/src/main/scala/debug/UartDebug.scala b/src/main/scala/debug/UartDebug.scala
index bf1eb8b..fff97f9 100644
--- a/src/main/scala/debug/UartDebug.scala
+++ b/src/main/scala/debug/UartDebug.scala
@@ -3,6 +3,7 @@ package debug
 import chisel.lib.uart._
 import chisel3._
 import chisel3.util._
+import chisel3.experimental.ChiselEnum
 
 /**
   * Poor mans debugger, using a UART instead of JTAG.
diff --git a/src/main/scala/spi/SpiMaster.scala b/src/main/scala/spi/SpiMaster.scala
index b6e74a7..72b125f 100644
--- a/src/main/scala/spi/SpiMaster.scala
+++ b/src/main/scala/spi/SpiMaster.scala
@@ -2,6 +2,8 @@ package spi
 
 import chisel3._
 import chisel3.util._
+import chisel3.experimental.ChiselEnum
+
 
 class SpiIO extends Bundle {
   val ncs = Output(Bool())