A limited Python/cocotb interface to the Xilinx Vivado Simulator simulator. Based on cocotb-stub-sim.
- Only top-level ports are accessible (simulator limitation).
- It supports the
Timer
trigger (simulator limitation). - Setting signal values is immediate, as one would use
setimmediatevalue
(simulator limitation). - Only
Verilog
at the top level is supported (to do). - Direct access to
XSI
interface
pip install cocotb-vivado==0.0.3 (for VIVADO <= 2022.2)
pip install cocotb-vivado (for VIVADO >= 2023.1)
See the tests
folder for examples.
source ../Vivado/202X.X/settings64.sh
export LD_LIBRARY_PATH=$XILINX_VIVADO/lib/lnx64.o
pytest -s
Extra future: One does not need to recompile the project when running/changing tests .
We'd like to thank our employer, Dectris for supporting this work.