Opensource DDR3 Controller
-
Updated
Dec 2, 2024 - Verilog
#
memory-controller
Here are 9 public repositories matching this topic...
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
-
Updated
Dec 1, 2022 - Verilog
mirror of https://git.elphel.com/Elphel/eddr3
-
Updated
Oct 16, 2017 - Verilog
This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).
linux arm kernel linux-kernel tesla armv7 samsung odroid arm64 devicetree snapdragon qualcomm armv8 exynos fsd qcom memory-controller samsung-soc gs101 gs201
-
Updated
Dec 12, 2024 - C
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
-
Updated
Jan 15, 2024 - Verilog
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
memory verilog sram memory-management vivado questasim sdram sdram-controller memory-controller verilog-project vlsi-design sram-controller sram-controller-advanced sram-features-power-security-brust verlog-hdl enhanched-sram-controller
-
Updated
Oct 21, 2024 - Verilog
Behavioral architecture of a read/write cycle controller for a DRAM chip.
-
Updated
May 26, 2023 - VHDL
🛠 A SDRAM controller in Verilog HDL
-
Updated
Mar 21, 2022 - Verilog
In this repository, I have published my knowledge gained while working on FIFO Project implementation using Verilog, System Verilog, UVM
-
Updated
Dec 3, 2024 - SystemVerilog
Improve this page
Add a description, image, and links to the memory-controller topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the memory-controller topic, visit your repo's landing page and select "manage topics."