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isa.txt
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isa.txt
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# vi: set ts=4 expandtab:
properties:
32 bit instructions
32 registers
3 address
64k control registers
r0-r31 - 32bit
r0 is zero filled
r30 is sp
r31 is lr
instruction forms
33222222222211111111110000000000
10987654321098765432109876543210
--------------------------------
00ppppDDDDDaaaaaiiiiiiiiiiiiiiii
00ppppDDDDDaaaaaiiiiiiiiiiiipppp - ldr/str form
01ppppDDDDDaaaaabbbbbxxxxxxxxxxx
01ppppDDDDDaaaaabbbbbxxxxxxxpppp - ldr/str form
10ppppDDDDDiiiiiiiiiixxxxxxxxxxx
11xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
all immediates are sign extended
all don't cares should be zero
00 -- immediate version (16bit signed, 12bit signed for ldr/str)
01 -- register,register
alu ops
0 2 6 11 16
add 0? 0000 d<5> a<5> b<5>,imm<16> a + b
sub 0? 0001 d<5> a<5> b<5>,imm<16> a - b
and 0? 0010 d<5> a<5> b<5>,imm<16> a & b
or 0? 0011 d<5> a<5> b<5>,imm<16> a | b
xor 0? 0100 d<5> a<5> b<5>,imm<16> a ^ b
lsl 0? 0101 d<5> a<5> b<5>,imm<16> a << b
lsr 0? 0110 d<5> a<5> b<5>,imm<16> a >> b
asr 0? 0111 d<5> a<5> b<5>,imm<16> a >>> b (sign extend)
mvb 0? 1000 d<5> a<5> b<5>,imm<16> a | (b & 0xffff) (unsigned 16 bit b load)
mvt 0? 1001 d<5> a<5> b<5>,imm<16> a | (b << 16)
seq 0? 1010 d<5> a<5> b<5>,imm<16> a == b
slt 0? 1011 d<5> a<5> b<5>,imm<16> a < b
slte 0? 1100 d<5> a<5> b<5>,imm<16> a <= b
unused
0x 1101 xxxxx xxxxx xxxxxxxxxxxxxxxx
load/store
ldrb 0? 1110 d<5> a<5> b<5>,imm<12> 00 0! ldrb Rd, [Ra + b]
strb 0? 1111 d<5> a<5> b<5>,imm<12> 00 0! strb Rd, [Ra + b]
ldrh 0? 1110 d<5> a<5> b<5>,imm<12> 01 0! ldrh Rd, [Ra + b]
strh 0? 1111 d<5> a<5> b<5>,imm<12> 01 0! strh Rd, [Ra + b]
ldr 0? 1110 d<5> a<5> b<5>,imm<12> 10 0! ldr Rd, [Ra + b]
str 0? 1111 d<5> a<5> b<5>,imm<12> 10 0! str Rd, [Ra + b]
unused
0x 1110 xxxx... 11 xx
0x 1111 xxxx... 11 xx
if Ra == r0, use PC as base
! = writeback to base reg
ldr/str future expansion:
multireg save
branch
b<l><z,nz> #imm 10 00Lz d<5> imm<21>
L = save old PC+4 into link register
z = test for zero or !zero in register Rd
zero test against r0 for branch always
imm<21> is shifted left 2, sign extended, added to PC
b<l><z,nz> r 10 01Lz d<5> a<5> xxxxxxxxxxx
branch future expansion:
interrupt return
larger unconditional branch space?
unused
10 1xxx xxxxx xxxxx xxxxxxxxxxxxxxxx
11 xxxx xxxxx xxxxx xxxxxxxxxxxxxxxx
pseudo instructions:
mov a, b - add a, r0, b
neg a, b - sub a, r0, b
not a, b - xor a, b, #-1
li a, #imm - mvb a, #(imm & 0xffff); mvt a, #(imm >> 16)
common algorithms:
a < b and branch - blt
slt cr, a, b
bnz cr
a > b and branch - bgt
slte cr, a, b
bz cr
a <= b and branch - blte
slte cr, a, b
bnz cr
a >= b and branch - bgte
slt cr, a, b
bz cr
a == b and branch - bge
seq cr, a, b
bnz cr
a != b and branch - bne
seq cr, a, b
bz cr
test for negative
slt a, #0
64bit add c = a + b
add cl, al, bl
slt cr, cl, al
add ch, ah, bh
add ch, ch, cr