From 054d31eca88f383954b4952bdf1c8d22b3999d7c Mon Sep 17 00:00:00 2001 From: Travis Haroldsen Date: Wed, 11 Oct 2023 11:59:58 -0400 Subject: [PATCH] Fix name of attached wire of PLLDATO output pin of PLL primitive to JPLLDATO (was JPLLDATI). --- libtrellis/src/Bels.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libtrellis/src/Bels.cpp b/libtrellis/src/Bels.cpp index 3e1f60be..ea661793 100644 --- a/libtrellis/src/Bels.cpp +++ b/libtrellis/src/Bels.cpp @@ -1042,7 +1042,7 @@ namespace MachXO2Bels { graph.add_bel_output(bel, graph.ident("CLKINTFB"), x, y, graph.ident("CLKINTFB_PLL")); add_output("DPHSRC"); for (int i=0;i<8;i++) - graph.add_bel_output(bel, graph.ident(fmt("PLLDATO" << i )), x, y, graph.ident(fmt("JPLLDATI" << i << "_PLL"))); + graph.add_bel_output(bel, graph.ident(fmt("PLLDATO" << i )), x, y, graph.ident(fmt("JPLLDATO" << i << "_PLL"))); add_output("PLLACK");