RV32I.core_desc

import "RISCVBase.core_desc"

InstructionSet RV32I extends RISCVBase {
    architectural_state {
        XLEN = 32;
    }

    instructions {
        LUI {
            encoding: imm[31:12] :: rd[4:0] :: 7'b0110111;
            assembly: "{name(rd)}, {imm:#05x}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>) ((signed) imm);
        }

        AUIPC {
            encoding: imm[31:12] :: rd[4:0] :: 7'b0010111;
            assembly: "{name(rd)}, {imm:#08x}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = PC + (signed)imm;
        }

        JAL [[no_cont]] {
            encoding: imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 7'b1101111;
            assembly: "{name(rd)}, {imm:#0x}";
            behavior: {
                if (imm % INSTR_ALIGNMENT) {
                    raise(0, RV_CAUSE_MISALIGNED_FETCH);
                } else {
                    if ((rd % RFS) != 0) X[rd % RFS] = PC + 4;
                    PC = PC + (signed)imm;
                }
            }
        }

        JALR [[no_cont]] {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1100111;
            assembly: "{name(rd)}, {name(rs1)}, {imm:#0x}";
            behavior: {
                unsigned<XLEN> new_pc = (X[rs1 % RFS] + (signed)imm) & ~0x1;
                if (new_pc % INSTR_ALIGNMENT) {
                    raise(0, RV_CAUSE_MISALIGNED_FETCH);
                } else {
                    if ((rd % RFS) != 0) X[rd % RFS] = PC + 4;
                    PC = new_pc & ~0x1;
                }
            }
        }

        BEQ [[no_cont]] [[cond]] {
            encoding: imm[12:12] ::imm[10:5] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: imm[4:1] :: imm[11:11] :: 7'b1100011;
            assembly:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
            behavior: {
                if (X[rs1 % RFS] == X[rs2 % RFS]) {
                    if(imm % INSTR_ALIGNMENT) {
                        raise(0, RV_CAUSE_MISALIGNED_FETCH);
                    } else {
                        PC = PC + (signed)imm;
                    }
                }
            }
        }

        BNE [[no_cont]] [[cond]] {
            encoding: imm[12:12] ::imm[10:5] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: imm[4:1] :: imm[11:11] :: 7'b1100011;
            assembly:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
            behavior: {
                if (X[rs1 % RFS] != X[rs2 % RFS]) {
                    if (imm % INSTR_ALIGNMENT) {
                        raise(0, RV_CAUSE_MISALIGNED_FETCH);
                    } else {
                        PC = PC + (signed)imm;
                    }
                }
            }
        }

        BLT [[no_cont]] [[cond]] {
            encoding: imm[12:12] ::imm[10:5] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: imm[4:1] :: imm[11:11] :: 7'b1100011;
            assembly:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
            behavior: {
                if ((signed<XLEN>)X[rs1 % RFS] < (signed<XLEN>)X[rs2 % RFS]) {
                    if (imm % INSTR_ALIGNMENT) {
                        raise(0, RV_CAUSE_MISALIGNED_FETCH);
                    } else {
                        PC = PC + (signed)imm;
                    }
                }
            }
        }

        BGE [[no_cont]] [[cond]] {
            encoding: imm[12:12] ::imm[10:5] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: imm[4:1] :: imm[11:11] :: 7'b1100011;
            assembly:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
            behavior: {
                if ((signed<XLEN>)X[rs1 % RFS] >= (signed<XLEN>)X[rs2 % RFS]) {
                    if (imm % INSTR_ALIGNMENT) {
                        raise(0, RV_CAUSE_MISALIGNED_FETCH);
                    } else {
                        PC = PC + (signed)imm;
                    }
                }
            }
        }

        BLTU [[no_cont]] [[cond]] {
            encoding: imm[12:12] ::imm[10:5] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: imm[4:1] :: imm[11:11] :: 7'b1100011;
            assembly:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
            behavior: {
                if (X[rs1 % RFS] < X[rs2 % RFS]) {
                    if (imm % INSTR_ALIGNMENT) {
                        raise(0, RV_CAUSE_MISALIGNED_FETCH);
                    } else {
                        PC = PC + (signed)imm;
                    }
                }
            }
        }

        BGEU [[no_cont]] [[cond]] {
            encoding: imm[12:12] ::imm[10:5] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: imm[4:1] :: imm[11:11] :: 7'b1100011;
            assembly:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
            behavior: {
                if (X[rs1 % RFS] >= X[rs2 % RFS]) {
                    if (imm % INSTR_ALIGNMENT) {
                        raise(0, RV_CAUSE_MISALIGNED_FETCH);
                    } else {
                        PC = PC + (signed)imm;
                    }
                }
            }
        }

        LB {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0000011;
            assembly:"{name(rd)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> load_address = X[rs1 % RFS] + (signed)imm;
                signed<8> res = (signed<8>)MEM[load_address];
                if((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)res;
            }
        }

        LH {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0000011;
            assembly:"{name(rd)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> load_address = X[rs1 % RFS] + (signed)imm;
                signed<16> res = (signed<16>)MEM[load_address];
                if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)res;
             }
        }

        LW {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
            assembly:"{name(rd)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> load_address = X[rs1 % RFS] + (signed)imm;
                signed<32> res = (signed<32>)MEM[load_address];
                if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)res;
            }
        }

        LBU {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0000011;
            assembly:"{name(rd)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> load_address = X[rs1 % RFS] + (signed)imm;
                unsigned<8> res = (unsigned<8>)MEM[load_address];
                if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)res;
            }
        }

        LHU {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0000011;
            assembly:"{name(rd)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> load_address = X[rs1 % RFS] + (signed)imm;
                unsigned<16> res = (unsigned<16>)MEM[load_address];
                if((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)res;
            }
        }

        SB {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: imm[4:0] :: 7'b0100011;
            assembly:"{name(rs2)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> store_address = X[rs1 % RFS] + (signed)imm;
                MEM[store_address] = (signed<8>)X[rs2 % RFS];
            }
        }

        SH {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: imm[4:0] :: 7'b0100011;
            assembly:"{name(rs2)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> store_address = X[rs1 % RFS] + (signed)imm;
                MEM[store_address] = (signed<16>)X[rs2 % RFS];
            }
        }

        SW {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0100011;
            assembly:"{name(rs2)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> store_address = X[rs1 % RFS] + (signed)imm;
                MEM[store_address] = (signed<32>)X[rs2 % RFS];
            }
        }

        ADDI {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {imm}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] + (signed)imm;
        }

        SLTI {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {imm}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = ((signed)X[rs1 % RFS] < (signed)imm) ? 1 : 0;
        }

        SLTIU {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {imm}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = (X[rs1 % RFS] < (unsigned<XLEN>)((signed)imm)) ? 1 : 0;
        }

        XORI {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {imm}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] ^ (unsigned<XLEN>)((signed)imm);
        }

        ORI {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {imm}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] | (unsigned<XLEN>)((signed)imm);
        }

        ANDI {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {imm}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] & (unsigned<XLEN>)((signed)imm);
        }

        SLLI {
            encoding: 7'b0000000 :: shamt[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] << shamt;
        }

        SRLI {
            encoding: 7'b0000000 :: shamt[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] >> shamt;
        }

        SRAI {
            encoding: 7'b0100000 :: shamt[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0010011;
            assembly:"{name(rd)}, {name(rs1)}, {shamt}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = (signed<XLEN>)X[rs1 % RFS] >> shamt;
        }

        ADD {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] + X[rs2 % RFS];
        }

        SUB {
            encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] - X[rs2 % RFS];
        }

        SLL {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] << (X[rs2 % RFS] & (XLEN - 1));
        }

        SLT {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = (signed)X[rs1 % RFS] < (signed)X[rs2 % RFS] ? 1 : 0;
        }

        SLTU {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
               behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] < X[rs2 % RFS] ? 1 : 0;
        }

        XOR {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] ^ X[rs2 % RFS];
        }

        SRL {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] >> (X[rs2 % RFS] & (XLEN - 1));
        }

        SRA {
            encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = (signed)X[rs1 % RFS] >> (X[rs2 % RFS] & (XLEN - 1));
        }

        OR {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] | X[rs2 % RFS];
        }

        AND {
            encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b0110011;
            assembly:"{name(rd)}, {name(rs1)}, {name(rs2)}";
            behavior: if ((rd % RFS) != 0) X[rd % RFS] = X[rs1 % RFS] & X[rs2 % RFS];
        }

        FENCE {
            encoding: fm[3:0] :: pred[3:0] :: succ[3:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001111;
            assembly:"{pred}, {succ} ({fm} , {name(rs1)}, {name(rd)})";
            behavior: FENCE[fence] = pred << 4 | succ;
        }

        ECALL [[no_cont]] {
            encoding: 0b000000000000 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b1110011;
            behavior: raise(0, 11);
        }

        EBREAK [[no_cont]] {
            encoding: 0b000000000001 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b1110011;
            behavior: raise(0, RV_CAUSE_BREAKPOINT);
        }
        MRET[[no_cont]] {
            encoding: 7'b0011000 :: 5'b00010 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b1110011;
            behavior: leave(3);
        }

        WFI {
            encoding: 7'b0001000 :: 5'b00101 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b1110011;
            behavior: wait(1);
        }
    }
}

InstructionSet Zicsr extends RISCVBase {
    architectural_state {
        unsigned int CSR_SIZE = 4096;
        extern unsigned<XLEN> CSR[CSR_SIZE];
    }

    functions {
        bool extension_enabled(char extension) {
            return (CSR[RV_CSR_MISA] >> (extension - 'A')) & 1;
        }
    }

    instructions {
        CSRRW {
            encoding: csr[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1110011;
            assembly:"{name(rd)}, {csr}, {name(rs1)}";
            behavior: {
                unsigned<XLEN> xrs1 = X[rs1 % RFS];
                if ((rd % RFS) != 0) {
                    unsigned<XLEN> xrd = CSR[csr];
                    CSR[csr] = xrs1;
                    // make sure Xrd is updated once CSR write succeeds
                    X[rd % RFS] = xrd;
                } else {
                    CSR[csr] = xrs1;
                }
            }
        }

        CSRRS {
            encoding: csr[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1110011;
            assembly:"{name(rd)}, {csr}, {name(rs1)}";
            behavior: {
                unsigned<XLEN> xrd = CSR[csr];
                unsigned<XLEN> xrs1 = X[rs1 % RFS];
                if (rs1 != 0) CSR[csr] = xrd | xrs1;
                if ((rd % RFS) != 0) X[rd % RFS] = xrd;
            }
        }

        CSRRC {
            encoding: csr[11:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1110011;
            assembly:"{name(rd)}, {csr}, {name(rs1)}";
            behavior: {
                unsigned<XLEN> xrd = CSR[csr];
                unsigned<XLEN> xrs1 = X[rs1 % RFS];
                if (rs1 != 0) CSR[csr] = xrd & ~xrs1;
                if ((rd % RFS) != 0) X[rd % RFS] = xrd;
            }
        }

        CSRRWI {
            encoding: csr[11:0] :: zimm[4:0] :: 3'b101 :: rd[4:0] :: 7'b1110011;
            assembly:"{name(rd)}, {csr}, {zimm:#0x}";
            behavior: {
                unsigned<XLEN> xrd = CSR[csr];
                CSR[csr] = (unsigned<XLEN>)zimm;
                if ((rd % RFS) != 0) X[rd % RFS] = xrd;
            }
        }

        CSRRSI {
            encoding: csr[11:0] :: zimm[4:0] :: 3'b110 :: rd[4:0] :: 7'b1110011;
            assembly:"{name(rd)}, {csr}, {zimm:#0x}";
            behavior: {
                unsigned<XLEN> xrd = CSR[csr];
                if (zimm != 0) CSR[csr] = xrd | (unsigned<XLEN>)zimm;
                if ((rd % RFS) != 0) X[rd % RFS] = xrd;
            }
        }

        CSRRCI {
            encoding: csr[11:0] :: zimm[4:0] :: 3'b111 :: rd[4:0] :: 7'b1110011;
            assembly:"{name(rd)}, {csr}, {zimm:#0x}";
            behavior: {
                unsigned<XLEN> xrd = CSR[csr];
                if (zimm != 0) CSR[csr] = xrd & ~((unsigned<XLEN>)zimm);
                if ((rd % RFS) != 0) X[rd % RFS] = xrd;
            }
        }
    }
}

InstructionSet Zifencei extends RISCVBase {
    instructions {
        FENCE_I [[flush]] {
            encoding: imm[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0001111 ;
            assembly:"{name(rs1)}, {name(rd)}, {imm}";
            behavior: FENCE[fencei] = imm;
        }
    }
}

InstructionSet RVNMode extends RISCVBase {
    instructions {
        URET[[no_cont]] {
            encoding: 7'b0000000 :: 5'b00010 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b1110011;
            behavior: leave(0);
        }
    }
}

InstructionSet RVSMode extends RISCVBase {
    instructions {
        SRET[[no_cont]]  {
            encoding: 7'b0001000 :: 5'b00010 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b1110011;
            behavior: leave(1);
        }
    }
}

InstructionSet RVDebug extends RISCVBase {
    instructions {
        DRET {
            encoding: 7'b0111101 :: 5'b10010 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b1110011;
            behavior: {
                if(PRIV<4)
                    raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION);
                else {
                    PC=DPC;
                    PRIV &= 0x3;
                }
            }
        }
    }
}