From 08e5f282d230f269fad0f6a077ae0cf5b5c1e440 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 25 Nov 2021 17:01:22 +0100 Subject: [PATCH 1/2] RISCV/RISCV64: Initialize cpuCycleTime_ps with arch.cpu_cycle_time_ps INI option Resolves Issue #98 Default/Fallback value: 32MHZ as this was used before. However `base.ini` and `ETISS.ini` default to 100MHZ. --- ArchImpl/RISCV/RISCVArch.cpp | 3 ++- ArchImpl/RISCV64/RISCV64Arch.cpp | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/ArchImpl/RISCV/RISCVArch.cpp b/ArchImpl/RISCV/RISCVArch.cpp index cb90326ebf..f359d3394c 100644 --- a/ArchImpl/RISCV/RISCVArch.cpp +++ b/ArchImpl/RISCV/RISCVArch.cpp @@ -67,7 +67,8 @@ void RISCVArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) else cpu->instructionPointer = 0x0; // reference to manual cpu->mode = 1; cpu->cpuTime_ps = 0; - cpu->cpuCycleTime_ps = 31250; + cpu->cpuCycleTime_ps = etiss::cfg(getLastAssignedCoreName()) + .get("arch.cpu_cycle_time_ps", 31250); // original: 31250; // 32MHz #if RISCV_Pipeline1 || RISCV_Pipeline2 //Initialize resources measurements cpu->resources[0] = "I_RAM"; diff --git a/ArchImpl/RISCV64/RISCV64Arch.cpp b/ArchImpl/RISCV64/RISCV64Arch.cpp index 2b4f67b62c..66864a3021 100644 --- a/ArchImpl/RISCV64/RISCV64Arch.cpp +++ b/ArchImpl/RISCV64/RISCV64Arch.cpp @@ -73,7 +73,8 @@ void RISCV64Arch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) else cpu->instructionPointer = 0x0; // reference to manual cpu->mode = 1; cpu->cpuTime_ps = 0; - cpu->cpuCycleTime_ps = 31250; + cpu->cpuCycleTime_ps = etiss::cfg(getLastAssignedCoreName()) + .get("arch.cpu_cycle_time_ps", 31250); // original: 31250; // 32MHz #if RISCV64_Pipeline1 || RISCV64_Pipeline2 //Initialize resources measurements cpu->resources[0] = "I_RAM"; From f77994d92c80e9cd67a99da30b94b6565bacc466 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 10 Jan 2022 11:53:04 +0100 Subject: [PATCH 2/2] update default for arch.cpu_cycle_time_ps to 31250 --- examples/bare_etiss_processor/ETISS.ini | 4 ++-- examples/bare_etiss_processor/base.ini | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/bare_etiss_processor/ETISS.ini b/examples/bare_etiss_processor/ETISS.ini index 14219ed61c..42feed3115 100644 --- a/examples/bare_etiss_processor/ETISS.ini +++ b/examples/bare_etiss_processor/ETISS.ini @@ -122,9 +122,9 @@ ; Set CPU freuquency in pico seconds ; (or1k) default=10000 - ; (ARMv6M) default=31250 + ; (RISCV) default=31250 - arch.cpu_cycle_time_ps=10000 + arch.cpu_cycle_time_ps=31250 ; Set the memory configuration of bare_etiss_processor ; Up to 99 segments are supported diff --git a/examples/bare_etiss_processor/base.ini b/examples/bare_etiss_processor/base.ini index d05da02ef1..fb6f11666a 100644 --- a/examples/bare_etiss_processor/base.ini +++ b/examples/bare_etiss_processor/base.ini @@ -16,7 +16,7 @@ testing = false arch.or1k.if_stall_cycles=0 etiss.max_block_size=100 -arch.cpu_cycle_time_ps=10000 +arch.cpu_cycle_time_ps=31250 ETISS::CPU_quantum_ps=100000 ETISS::write_pc_trace_from_time_us=0 ETISS::write_pc_trace_until_time_us=3000000