From f77994d92c80e9cd67a99da30b94b6565bacc466 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 10 Jan 2022 11:53:04 +0100 Subject: [PATCH] update default for arch.cpu_cycle_time_ps to 31250 --- examples/bare_etiss_processor/ETISS.ini | 4 ++-- examples/bare_etiss_processor/base.ini | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/bare_etiss_processor/ETISS.ini b/examples/bare_etiss_processor/ETISS.ini index 14219ed61c..42feed3115 100644 --- a/examples/bare_etiss_processor/ETISS.ini +++ b/examples/bare_etiss_processor/ETISS.ini @@ -122,9 +122,9 @@ ; Set CPU freuquency in pico seconds ; (or1k) default=10000 - ; (ARMv6M) default=31250 + ; (RISCV) default=31250 - arch.cpu_cycle_time_ps=10000 + arch.cpu_cycle_time_ps=31250 ; Set the memory configuration of bare_etiss_processor ; Up to 99 segments are supported diff --git a/examples/bare_etiss_processor/base.ini b/examples/bare_etiss_processor/base.ini index d05da02ef1..fb6f11666a 100644 --- a/examples/bare_etiss_processor/base.ini +++ b/examples/bare_etiss_processor/base.ini @@ -16,7 +16,7 @@ testing = false arch.or1k.if_stall_cycles=0 etiss.max_block_size=100 -arch.cpu_cycle_time_ps=10000 +arch.cpu_cycle_time_ps=31250 ETISS::CPU_quantum_ps=100000 ETISS::write_pc_trace_from_time_us=0 ETISS::write_pc_trace_until_time_us=3000000