Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Merge artifacts (properties, status, tests) in single table #136

Open
Tracked by #116
kebi-be opened this issue Oct 30, 2024 · 10 comments
Open
Tracked by #116

Merge artifacts (properties, status, tests) in single table #136

kebi-be opened this issue Oct 30, 2024 · 10 comments

Comments

@kebi-be
Copy link
Collaborator

kebi-be commented Oct 30, 2024

No description provided.

@kebi-be kebi-be mentioned this issue Oct 30, 2024
Open
29 tasks
@kebi-be
Copy link
Collaborator Author

kebi-be commented Nov 5, 2024 •
edited
Loading

Used Pandas to merge the tables (Status, Properties and Results)

CVS:

Markdown:

model set xlen instr stage pass status is_rv32 is_rv64 num_operands num_inputs num_outputs num_inouts num_regs num_gprs num_imms imm_types is_multi_in is_single_in is_multi_out is_single_out is_mimo is_miso is_siso is_simo has_side_effects may_load may_store is_terminator is_branch uses_custom_reg defs_custom_reg test_kind test_file test_fmt result
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.c c FAIL
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False cg openasip_base_max.test-cg.ll ll PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False inline-asm openasip_base_max.test-inline-asm.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False intrin openasip_base_max.test-intrin.c c PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False mc openasip_base_max.test-mc.s s PASS
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ transform transform_passes.detect_behavior_constraints failed True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR transform transform_passes.detect_behavior_constraints failed True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU transform transform_passes.detect_behavior_constraints failed True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU transform transform_passes.detect_behavior_constraints failed True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU transform transform_passes.detect_behavior_constraints failed True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC transform transform_passes.simplify_trivial_slices success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC transform transform_passes.explicit_truncations success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC transform transform_passes.detect_behavior_constraints success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC transform transform_passes.collect_register_operands success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC transform transform_passes.collect_immediate_operands success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC transform transform_passes.detect_side_effects success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC transform transform_passes.detect_inouts success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC generate generate_passes.riscv_instr_info success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC generate generate_passes.pattern_gen.behav_to_llvmir success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC generate generate_passes.pattern_gen.behav_to_pat success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU transform transform_passes.simplify_trivial_slices success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU transform transform_passes.explicit_truncations success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU transform transform_passes.detect_behavior_constraints success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU transform transform_passes.collect_register_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU transform transform_passes.collect_immediate_operands success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU transform transform_passes.detect_side_effects success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU transform transform_passes.detect_inouts success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU generate generate_passes.riscv_instr_info success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU generate generate_passes.pattern_gen.behav_to_llvmir success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU generate generate_passes.pattern_gen.behav_to_pat success True False 3 2 1 0 3 3 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD transform transform_passes.simplify_trivial_slices failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD transform transform_passes.explicit_truncations failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD transform transform_passes.detect_behavior_constraints failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD transform transform_passes.collect_register_operands failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD transform transform_passes.collect_immediate_operands failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD transform transform_passes.detect_side_effects failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD transform transform_passes.detect_inouts failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD generate generate_passes.riscv_instr_info failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD generate generate_passes.pattern_gen.behav_to_llvmir failed True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LMBD generate generate_passes.pattern_gen.behav_to_pat skipped True False 3 0 0 0 2 2 0 set() False False False False False False False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT transform transform_passes.detect_behavior_constraints failed True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT generate generate_passes.pattern_gen.behav_to_pat failed True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT transform transform_passes.simplify_trivial_slices success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT transform transform_passes.explicit_truncations success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT transform transform_passes.collect_register_operands success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT transform transform_passes.collect_immediate_operands success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT transform transform_passes.detect_side_effects success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT transform transform_passes.detect_inouts success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT generate generate_passes.riscv_instr_info success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT generate generate_passes.pattern_gen.behav_to_llvmir success True False 4 3 1 0 4 4 0 set() True False False True False True False False False False False False False False False N/A N/A N/A N/A

@PhilippvK
Copy link
Member

PhilippvK commented Nov 5, 2024 •
edited
Loading

@kebi-be The contents are missing here? (I saw them in the mail)

Could you make sure to drop the rendundant model,set,xlen cols in the merged df?

How do you handle instructions which do not have tests available? (an inner-join would drop those but we should have information about the non-existent tests in the table)

I do not understand how you combine the status and test results in the same row? For each instruction there are multiple test and multiple status rows.

@kebi-be
Copy link
Collaborator Author

kebi-be commented Nov 5, 2024

I deleted the files as I noticed the redundant columns in the df. Instructions without tests will simple have an NaN value. I will update this. I will add NaN in the empty fields of the non-existing tests.

I first merge the status and properties tables (inner join) and then merge the results to the status_prop_table. Since for the OpenASIP_base_MAX tests results there are 5 different tests and for this instruction there are 10 different passes from the status table. So combining these will results to the multiple rows (5x10). What are your expectations. Otherwise I donot see any other way of combining these.

@PhilippvK
Copy link
Member

I think we have to aggregate the data to display it in a meaningful way. Of course we will loose some information (i.e. names of failing passes/tests) but should get some overall (per instruction, per-class, per-set, total) metrics on how good Seal5 peforms.

In the following comments I will post some ideas on how the aggregations could be done.

@PhilippvK
Copy link
Member

For the Status Data (last row aggregates over a instructions in the set)

set instr n_success n_skipped n_failed Summary
(pass/skip/fail)
[%]		 Status
(good/ok/bad)
[%]
OpenASIP_base OpenASIP_base_SHL1ADD 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_SHL2ADD 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_ADD 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_SUB 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_EQ 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_GT 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_GTU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_LT 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_LTU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_NE 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_GE 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_GEU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_LE 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_LEU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_SHL 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_SHR 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_SHRU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_AND 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_IOR 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_XOR 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MIN 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MAX 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MINU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MAXU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MUL 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MULHI 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MULHIU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MULHISU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_DIV 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_DIVU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MAC 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_ROTL 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_ROTR 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MOD 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_REM 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_MODU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_REMU 10 0 0 10 / 0 / 0
[100%/0%/0%]		 good
OpenASIP_base OpenASIP_base_LMBD 9 1 0 9 / 1 / 0
[90%/10%/0%]		 ok
OpenASIP_base OpenASIP_base_SELECT 8 0 2 8 / 0 / 2
[80%/0%/20%]		 bad
OpenASIP_base * 387 1 2 387 / 1 / 2
[99.2%/0.3%/0.5%]		 36 / 1 / 1
[92.3%/2.6%/2.6%]

@PhilippvK
Copy link
Member

Same idea for the test results data (added dummy test data for MAXU):

set instr n_pass n_failed n_tests Summary
(pass/fail)
[%]		 Status
(good/bad/unknown)
OpenASIP_base OpenASIP_base_MAX 4 4 8 4 / 4
[50%/50%]		 good
OpenASIP_base OpenASIP_base_MAXU 0 6 6 0 / 6
[0%/100%]		 bad
OpenASIP_base_MUL OpenASIP_base_MUL 0 0 0 0 / 6
[-%/-%]		 unknown
... ... ... ... ... ...
OpenASIP_base * 4 10 14 4 / 4
[50%/50%]		 1 / 1 / 1
[33.3%/33.3%/33.3%]

@PhilippvK
Copy link
Member

I also had the idea to give a metric for the test coverage of each instruction. Here is an example of what I mean:

A Test Coverage of 100% means the following tests (kind+fmt) are being executed for the instruction:

  • mc+s
  • inline-asm+s
  • cg+c (if pattern-gen is not skipped)
  • cg+mir (if pattern-gen is not skipped)
  • cg+ll (if pattern-gen is not skipped)
  • legalizer+mir (if legalizer setting exists for instruction)
  • intrin+c (if intrinsic exists for instruction)
  • builtin+ll (if intrinsic exists for instruction)

Here is a table with some manually entered coverage data:

set instr Coverage
(existing/missing/goal)
[%]		 Status
(good/ok/unknown)
OpenASIP_base OpenASIP_base_MAX 8 / 0 / 8
[100%]		 good
OpenASIP_base OpenASIP_base_MAXU 6 / 2 / 8
[75%]		 ok
OpenASIP_base_MUL OpenASIP_base_MUL 0 / 8 / 8
[0%]		 unknown
... ... ... ...
OpenASIP_base * 14 / 10 / 24
[58%]		 1 / 1 / 1
[33.3%/33.3%/33.3%]

@PhilippvK
Copy link
Member

@kebi-be If you think the coverage information would be nice-to-have, then I will add it to the Tracking issue #116 and implement a report backend which can emit this data.

@PhilippvK
Copy link
Member

@kebi-be As requested, I have added a --compact mode for the test results and status (passes) reports. The resulting tables only have a single row per instruction.

All artifacts can be found here:

Minimal Example:

Passes

model set xlen instr n_success n_skipped n_failed n_total status
Example XExample 32 CV_SUBINCACC 12 0 0 12 good 🟢

Test Results

model set xlen instr n_pass n_fail n_tests state
Example XExample 32 CV_SUBINCACC 7 0 7 good 🟢

@PhilippvK
Copy link
Member

An initial test coverage analysis is also available using the new --coverage flag of the seal5.backends.report.test_results.writer backend.

Example Output:

test_coverage_compact.md

model set xlen instr n_exists n_required n_optional n_extra n_required_exists n_optional_exists coverage
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX 9 4 5 1 4 5 good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU 7 4 5 0 4 3 ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB 0 4 5 0 0 0 bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 0 4 5 0 0 0 bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B 0 4 5 0 0 0 bad 🔴

test_coverage.md

model set xlen instr test_kind test_fmt required extra exists coverage
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL1ADD builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL2ADD builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ADD builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SUB builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_EQ builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GT builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GTU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LT builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LTU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_NE builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GE builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_GEU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LE builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_LEU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHL builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHR builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SHRU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_AND builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_IOR builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_XOR builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MIN builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX mc s True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX inline-asm c False False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX cg ll True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX cg c True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX cg mir True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX legalizer mir False False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX intrin ll False False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX builtin c False False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAX invalid s False True True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MINU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU mc s True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU inline-asm c False False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU cg ll True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU cg c True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU cg mir True False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU intrin ll False False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAXU builtin c False False True good 🟢
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MUL builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHI builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHIU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MULHISU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIV builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_DIVU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MAC builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTL builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_ROTR builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MOD builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REM builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_MODU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_REMU builtin c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT mc s True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT mc-invalid s False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT inline-asm c False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT cg ll True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT cg c True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT cg mir True False False bad 🔴
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT legalizer mir False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT intrin ll False False False ok 🟠
OpenASIP_base OpenASIP_base 32 OpenASIP_base_SELECT builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XOR builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_AES283XORB builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0 builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1 builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0 builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1 builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG0B builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SIG1B builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM0B builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_SHA256SUM1B builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTL32 builtin c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 mc s True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 mc-invalid s False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 inline-asm c False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 cg ll True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 cg c True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 cg mir True False False bad 🔴
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 legalizer mir False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 intrin ll False False False ok 🟠
OpenASIP_paper OpenASIP_paper 32 SEAL5_ROTR32 builtin c False False False ok 🟠

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@PhilippvK @kebi-be