Intrinsics/Builtins: Support for custom argument names/order

[PhilippvK]

As far as I can tell the order and/or names of arguments used when defining and intrinsics (in the YAML settings) should match the assembly operands of the instruction definition.

The spec of the Core-V Extension builtins uses custom argument names (i.e. i,j instead of rs1,rs2) and places the "destination & accumulator" registers not at the front. Here is a concrete Examples:

• int32_t __builtin_riscv_cv_mac_mac (int32_t x, int32_t y, int32_t z) (Source)

  Argument/result mapping:

  • result, z: rD
  • x: rs1
  • y: rs2

  Generated assembler:

  cv.mac  rD,rs1,rs2

We should...

• Provide (optional) YAML syntax to define how the builtins' argument names map to the instructions' operands
• Make sure that the order of arguments is generated as expected
• Clarify (docstring/readme) how argument names of intrinsics are specified implicitly/explicitly

[thomasgoodfellow]

Agreed - as it happens the previous (phase 1) implementation for the assembler faced a similar problem for instructions with unconventional argument ordering. That solution was a hack; something neater needed here.