diff --git a/core/src/bus/mod.rs b/core/src/bus/mod.rs
index 6aa03e0..3c1b677 100644
--- a/core/src/bus/mod.rs
+++ b/core/src/bus/mod.rs
@@ -2,6 +2,7 @@ pub mod testbus;
 
 use crate::tickable::Tickable;
 
+use anyhow::Result;
 use num_traits::{PrimInt, WrappingAdd};
 
 /// Main CPU address data type (actually 24-bit)
@@ -34,6 +35,9 @@ pub trait Bus<TA: PrimInt + WrappingAdd, TD: PrimInt>: Tickable {
     fn read(&mut self, addr: TA) -> BusResult<TD>;
     fn write(&mut self, addr: TA, val: TD) -> BusResult<TD>;
     fn get_mask(&self) -> TA;
+
+    /// RESET line triggered by 68k RESET instruction
+    fn reset(&mut self) -> Result<()>;
 }
 
 /// Inspectable provides an interface to debugging/memory views.
diff --git a/core/src/bus/testbus.rs b/core/src/bus/testbus.rs
index 404e609..4e03d60 100644
--- a/core/src/bus/testbus.rs
+++ b/core/src/bus/testbus.rs
@@ -102,6 +102,10 @@ where
         self.mem.insert(addr, val);
         BusResult::Ok(val)
     }
+
+    fn reset(&mut self) -> Result<()> {
+        Ok(())
+    }
 }
 
 impl<TA, TD> Tickable for Testbus<TA, TD>
diff --git a/core/src/cpu_m68k/cpu.rs b/core/src/cpu_m68k/cpu.rs
index c990cff..9a6e2c0 100644
--- a/core/src/cpu_m68k/cpu.rs
+++ b/core/src/cpu_m68k/cpu.rs
@@ -2046,6 +2046,8 @@ where
             return self.raise_exception(ExceptionGroup::Group2, VECTOR_PRIVILEGE_VIOLATION, None);
         }
 
+        debug!("RESET instruction");
+        self.bus.reset()?;
         self.advance_cycles(128)?;
         Ok(())
     }
diff --git a/core/src/mac/bus.rs b/core/src/mac/bus.rs
index 2bf525b..79f4b86 100644
--- a/core/src/mac/bus.rs
+++ b/core/src/mac/bus.rs
@@ -443,6 +443,13 @@ where
         }
         BusResult::Ok(val)
     }
+
+    fn reset(&mut self) -> Result<()> {
+        self.via = Via::new(self.model);
+        self.scc = Scc::new();
+        self.overlay = true;
+        Ok(())
+    }
 }
 
 impl<TRenderer> Tickable for MacBus<TRenderer>