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vectorfp16e.h
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vectorfp16e.h
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/**************************** vectorfp16e.h *******************************
* Author: Agner Fog
* Date created: 2022-05-03
* Last modified: 2023-10-19
* Version: 2.02.01
* Project: vector class library
* Description:
* Header file emulating half precision floating point vector classes
* when instruction set AVX512_FP16 is not defined
*
* Instructions: see vcl_manual.pdf
*
* The following vector classes are defined here:
* Vec8h Vector of 8 half precision floating point numbers in 128 bit vector
* Vec16h Vector of 16 half precision floating point numbers in 256 bit vector
* Vec32h Vector of 32 half precision floating point numbers in 512 bit vector
*
* This header file defines operators and functions for these vectors.
*
* (c) Copyright 2012-2023 Agner Fog.
* Apache License version 2.0 or later.
*****************************************************************************/
#ifndef VECTORFP16E_H
#define VECTORFP16E_H
#ifndef VECTORCLASS_H
#include "vectorclass.h"
#endif
#if VECTORCLASS_H < 20200
#error Incompatible versions of vector class library mixed
#endif
#if MAX_VECTOR_SIZE < 256
#error Emulation of half precision floating point not supported for MAX_VECTOR_SIZE < 256
#endif
#ifdef VCL_NAMESPACE
namespace VCL_NAMESPACE {
#endif
/*****************************************************************************
*
* Float16: Use _Float16 if it is defined, or emulate it if not
*
*****************************************************************************/
// test if _Float16 is defined
#if defined(FLT16_MAX) || defined(__FLT16_MAX__)
// _Float16 is defined.
typedef _Float16 Float16;
// Define bit-casting between uint16_t <-> Float16
static inline uint16_t castfp162s(Float16 x) {
union {
Float16 f;
uint16_t i;
} u;
u.f = x;
return u.i;
}
static inline Float16 casts2fp16(uint16_t x) {
union {
uint16_t i;
Float16 f;
} u;
u.i = x;
return u.f;
}
#else
// _Float16 is not defined
// define Float16 as a class with constructor, operators, etc. to avoid operators like + from treating Float16 like integer
class Float16 {
protected:
uint16_t x;
public:
// Default constructor:
Float16() = default;
#ifdef __F16C__ // F16C instruction set includes conversion instructions
Float16(float f) { // Constructor to convert float to fp16
//x = uint16_t(_mm_cvtsi128_si32(_mm_cvtps_ph(_mm_set1_ps(f), _MM_FROUND_NO_EXC))); // requires __AVX512FP16__
x = uint16_t(_mm_cvtsi128_si32(_mm_cvtps_ph(_mm_set1_ps(f), 0)));
}
operator float() const { // Type cast operator to convert fp16 to float
return _mm_cvtss_f32(_mm_cvtph_ps(_mm_set1_epi32(x)));
}
#else // F16C instruction set not supported. Make conversion functions
Float16(float f) { // Constructor to convert float to fp16
union { // single precision float as bitfield
float f;
struct {
uint32_t mant : 23;
uint32_t expo : 8;
uint32_t sign : 1;
};
} u;
union { // half precision float as bitfield
uint16_t h;
struct {
uint16_t mant : 10;
uint16_t expo : 5;
uint16_t sign : 1;
};
} v;
u.f = f;
v.expo = u.expo - 0x70; // convert exponent
v.mant = u.mant >> 13; // get upper part of mantissa
if (u.mant & (1 << 12)) { // round to nearest or even
if ((u.mant & ((1 << 12) - 1)) || (v.mant & 1)) { // round up if odd or remaining bits are nonzero
v.h++; // overflow here will give infinity
}
}
v.sign = u.sign; // copy sign bit
if (u.expo == 0xFF) { // infinity or nan
v.expo = 0x1F;
if (u.mant != 0) { // Nan
v.mant = u.mant >> 13; // NAN payload is left-justified
}
}
else if (u.expo > 0x8E) {
v.expo = 0x1F; v.mant = 0; // overflow -> inf
}
else if (u.expo < 0x71) {
v.expo = 0; // subnormals are always supported
u.expo += 24;
u.sign = 0;
//v.mant = int(u.f) & 0x3FF;
int mants = _mm_cvt_ss2si(_mm_load_ss(&u.f));
v.mant = mants & 0x3FF; // proper rounding of subnormal
if (mants == 0x400) v.expo = 1;
}
x = v.h; // store result
}
operator float() const { // Type cast operator to convert fp16 to float
union {
uint32_t hhh;
float fff;
struct {
uint32_t mant : 23;
uint32_t expo : 8;
uint32_t sign : 1;
};
} u;
u.hhh = (x & 0x7fff) << 13; // Exponent and mantissa
u.hhh += 0x38000000; // Adjust exponent bias
if ((x & 0x7C00) == 0) { // Subnormal or zero
u.hhh = 0x3F800000 - (24 << 23); // 2^-24
u.fff *= int(x & 0x3FF); // subnormal value = mantissa * 2^-24
}
if ((x & 0x7C00) == 0x7C00) { // infinity or nan
u.expo = 0xFF;
if (x & 0x3FF) { // nan
u.mant = (x & 0x3FF) << 13; // NAN payload is left-justified
}
}
u.hhh |= (x & 0x8000) << 16; // copy sign bit
return u.fff;
}
#endif // F16C supported
void setBits(uint16_t a) {
x = a;
}
uint16_t getBits() const {
return x;
}
};
static inline int16_t castfp162s(Float16 a) {
return a.getBits();
}
static inline Float16 casts2fp16(int16_t a) {
Float16 f;
f.setBits(a);
return f;
}
// Define operators for Float16 emulation class
static inline Float16 operator + (Float16 const a, Float16 const b) {
return Float16(float(a) + float(b));
}
static inline Float16 operator - (Float16 const a, Float16 const b) {
return Float16(float(a) - float(b));
}
static inline Float16 operator * (Float16 const a, Float16 const b) {
return Float16(float(a) * float(b));
}
static inline Float16 operator / (Float16 const a, Float16 const b) {
return Float16(float(a) / float(b));
}
static inline Float16 operator - (Float16 const a) {
return casts2fp16(castfp162s(a) ^ 0x8000);
}
static inline bool operator == (Float16 const a, Float16 const b) {
return float(a) == float(b);
}
static inline bool operator != (Float16 const a, Float16 const b) {
return float(a) != float(b);
}
static inline bool operator < (Float16 const a, Float16 const b) {
return float(a) < float(b);
}
static inline bool operator <= (Float16 const a, Float16 const b) {
return float(a) <= float(b);
}
static inline bool operator > (Float16 const a, Float16 const b) {
return float(a) > float(b);
}
static inline bool operator >= (Float16 const a, Float16 const b) {
return float(a) >= float(b);
}
#endif // Float16 defined
/*****************************************************************************
*
* Vec8hb: Vector of 8 Booleans for use with Vec8h
*
*****************************************************************************/
#if INSTRSET >= 10
typedef Vec8b Vec8hb; // compact boolean vector
static inline Vec8hb Vec8fb2hb (Vec8fb const a) {
return a;
}
#else
typedef Vec8sb Vec8hb; // broad boolean vector
static inline Vec8hb Vec8fb2hb (Vec8fb const a) {
// boolean vector needs compression from 32 bits to 16 bits per element
Vec4ib lo = reinterpret_i(a.get_low());
Vec4ib hi = reinterpret_i(a.get_high());
return _mm_packs_epi32(lo, hi);
}
#endif
/*****************************************************************************
*
* Vec8h: Vector of 8 half precision floating point values
*
*****************************************************************************/
class Vec8h {
protected:
__m128i xmm; // Float vector
public:
// Default constructor:
Vec8h() = default;
// Constructor to broadcast the same value into all elements:
Vec8h(Float16 f) {
xmm = _mm_set1_epi16 (castfp162s(f));
}
// Constructor to build from all elements:
Vec8h(Float16 f0, Float16 f1, Float16 f2, Float16 f3, Float16 f4, Float16 f5, Float16 f6, Float16 f7) {
xmm = _mm_setr_epi16 (castfp162s(f0), castfp162s(f1), castfp162s(f2), castfp162s(f3), castfp162s(f4), castfp162s(f5), castfp162s(f6), castfp162s(f7));
}
// Constructor to convert from type __m128i used in intrinsics:
Vec8h(__m128i const x) {
xmm = x;
}
// Assignment operator to convert from type __m128i used in intrinsics:
Vec8h & operator = (__m128i const x) {
xmm = x;
return *this;
}
// Type cast operator to convert to __m128i used in intrinsics
operator __m128i() const {
return xmm;
}
// Member function to load from array (unaligned)
Vec8h & load(void const * p) {
xmm = _mm_loadu_si128 ((const __m128i *)p);
return *this;
}
// Member function to load from array, aligned by 16
// You may use load_a instead of load if you are certain that p points to an address
// divisible by 16. In most cases there is no difference in speed between load and load_a
Vec8h & load_a(void const * p) {
xmm = _mm_load_si128 ((const __m128i *)p);
return *this;
}
// Member function to store into array (unaligned)
void store(void * p) const {
_mm_storeu_si128 ((__m128i *)p, xmm);
}
// Member function storing into array, aligned by 16
// You may use store_a instead of store if you are certain that p points to an address
// divisible by 16.
void store_a(void * p) const {
_mm_store_si128 ((__m128i *)p, xmm);
}
// Member function storing to aligned uncached memory (non-temporal store).
// This may be more efficient than store_a when storing large blocks of memory if it
// is unlikely that the data will stay in the cache until it is read again.
// Note: Will generate runtime error if p is not aligned by 16
void store_nt(void * p) const {
_mm_stream_si128((__m128i*)p, xmm);
}
// Partial load. Load n elements and set the rest to 0
Vec8h & load_partial(int n, void const * p) {
xmm = Vec8s().load_partial(n, p);
return *this;
}
// Partial store. Store n elements
void store_partial(int n, void * p) const {
Vec8s(xmm).store_partial(n, p);
}
// cut off vector to n elements. The last 8-n elements are set to zero
Vec8h & cutoff(int n) {
xmm = Vec8s(xmm).cutoff(n);
return *this;
}
// Member function to change a single element in vector
Vec8h const insert(int index, Float16 a) {
xmm = Vec8s(xmm).insert(index, castfp162s(a));
return *this;
}
// Member function extract a single element from vector
Float16 extract(int index) const {
Float16 y;
y = casts2fp16(Vec8s(xmm).extract(index));
return y;
}
// Extract a single element. Use store function if extracting more than one element.
// Operator [] can only read an element, not write.
Float16 operator [] (int index) const {
return extract(index);
}
static constexpr int size() {
return 8;
}
static constexpr int elementtype() {
return 15;
}
typedef __m128i registertype;
};
/*****************************************************************************
*
* conversions Vec8h <-> Vec4f
*
*****************************************************************************/
#ifdef __F16C__ // F16C instruction set has conversion instructions
// extend precision: Vec8h -> Vec4f. upper half ignored
static inline Vec4f convert8h_4f (Vec8h h) {
return _mm_cvtph_ps(h);
}
// reduce precision: Vec4f -> Vec8h. upper half zero
static inline Vec8h convert4f_8h (Vec4f f) {
return _mm_cvtps_ph(f, 0);
}
#else
// extend precision: Vec8h -> Vec4f. upper half ignored
static Vec4f convert8h_4f (Vec8h x) {
// __m128i a = _mm_cvtepu16_epi32(x); // SSE4.1
__m128i a = _mm_unpacklo_epi16(x, _mm_setzero_si128 ()); // zero extend
__m128i b = _mm_slli_epi32(a, 16); // left-justify
__m128i c = _mm_and_si128(b, _mm_set1_epi32(0x80000000)); // isolate sign bit
__m128i d = _mm_andnot_si128(_mm_set1_epi32(0x80000000),b); // remove sign bit
__m128i e = _mm_srli_epi32(d, 3); // put exponent and mantissa in place
__m128i f = _mm_add_epi32(e, _mm_set1_epi32(0x38000000)); // adjust exponent bias
// check for subnormal, INF, and NAN
__m128i xx = _mm_set1_epi32(0x7C00); // exponent field in fp16
__m128i g = _mm_and_si128(a, xx); // isolate exponent (low position)
__m128i zd = _mm_cmpeq_epi32(g, _mm_setzero_si128()); // -1 if x is zero or subnormal
__m128i in = _mm_cmpeq_epi32(g, xx); // -1 if x is INF or NAN
__m128i ma = _mm_and_si128(a, _mm_set1_epi32(0x3FF)); // isolate mantissa
__m128 sn = _mm_mul_ps(_mm_cvtepi32_ps(ma), _mm_set1_ps(1.f/16777216.f)); // converted subnormal = mantissa * 2^-24
__m128i snm = _mm_and_si128(_mm_castps_si128(sn), zd); // converted subnormal, masked
__m128i inm = _mm_and_si128(in,_mm_set1_epi32(0x7F800000)); // INF or NAN exponent field, masked off if not INF or NAN
__m128i fm = _mm_andnot_si128(zd, f); // normal result, masked off if zero or subnormal
__m128i r = _mm_or_si128(fm, c); // insert sign bit
__m128i s = _mm_or_si128(snm, inm); // combine branches
__m128i t = _mm_or_si128(r, s); // combine branches
return _mm_castsi128_ps(t); // cast result to float
}
// reduce precision: Vec4f -> Vec8h. upper half zero
static Vec8h convert4f_8h (Vec4f x) {
__m128i a = _mm_castps_si128(x); // bit-cast to integer
// 23 bit mantissa rounded to 10 bits - nearest or even
__m128i r = _mm_srli_epi32(a, 12); // get first discarded mantissa bit
__m128i s = _mm_and_si128(a, _mm_set1_epi32(0x2FFF)); // 0x2000 indicates if odd, 0x0FFF if remaining bits are nonzero
__m128i u = _mm_cmpeq_epi32(s, _mm_setzero_si128()); // false if odd or remaining bits nonzero
__m128i v = _mm_andnot_si128(u, r); // bit 0 = 1 if we have to round up
__m128i w = _mm_and_si128(v, _mm_set1_epi32(1)); // = 1 if we need to round up
__m128i m = _mm_srli_epi32(a, 13); // get mantissa in place
__m128i n = _mm_and_si128(m, _mm_set1_epi32(0x3FF)); // mantissa isolated
__m128i e = _mm_and_si128(a, _mm_set1_epi32(0x7FFFFFFF)); // remove sign bit
__m128i f = _mm_sub_epi32(e, _mm_set1_epi32(0x70 << 23)); // adjust exponent bias (underflow will be caught by uu below)
__m128i g = _mm_srli_epi32(f, 13); // shift exponent into new place
__m128i h = _mm_and_si128(g, _mm_set1_epi32(0x3FC00)); // isolate exponent
__m128i i = _mm_or_si128(n, h); // combine exponent and mantissa
Vec4i j = _mm_add_epi32(i, w); // round mantissa. Overflow will carry into exponent
// check for overflow and underflow
Vec4ib k = j > 0x7BFF; // overflow
Vec4i ee = _mm_srli_epi32(e, 23); // exponent at position 0
Vec4ib ii = ee == 0xFF; // check for INF and NAN
Vec4ib uu = ee < 0x71; // check for exponent underflow
__m128i pp = _mm_or_si128(j, _mm_set1_epi32(0x7C00)); // insert exponent if INF or NAN
// compute potential subnormal result
__m128i ss = _mm_add_epi32(e, _mm_set1_epi32(24 << 23)); // add 24 to exponent
__m128i tt = _mm_cvtps_epi32(_mm_castsi128_ps(ss)); // convert float to int with rounding
__m128i vv = _mm_and_si128(tt, _mm_set1_epi32(0x3FF)); // mantissa of subnormal number
// combine results
Vec4i bb = select(k, 0x7C00, j); // select INF if overflow
Vec4i dd = select(ii, pp, bb); // select INF or NAN
Vec4i cc = select(uu, vv, dd); // select if subnormal or zero or exponent underflow
// get sign bit
Vec4i sa = Vec4i(a) >> 16; // extend sign bit to avoid saturation in pack instruction below
Vec4i const smask = 0xFFFF8000; // extended sign mask
Vec4i sb = sa & smask; // isolate sign
Vec4i sc = _mm_andnot_si128(smask, cc); // isolate exponent and mantissa
Vec4i rr = sb | sc; // combine with sign
Vec4i rc = _mm_packs_epi32(rr, _mm_setzero_si128()); // pack into 16-bit words (words are sign extended so they will not saturate)
return (__m128i)rc; // return as Vec8h
}
#endif
/*****************************************************************************
*
* conversions Vec8h <-> Vec8f
*
*****************************************************************************/
#if defined (__F16C__) && INSTRSET >= 8 // F16C instruction set has conversion instructions
// extend precision: Vec8h -> Vec8f
static inline Vec8f to_float (Vec8h h) {
return _mm256_cvtph_ps(h);
}
// reduce precision: Vec8f -> Vec8h
static inline Vec8h to_float16 (Vec8f f) {
return _mm256_cvtps_ph(f, 0);
}
#elif INSTRSET >= 8 // __F16C__ not defined, AVX2 supported
// extend precision: Vec8h -> Vec8f
static Vec8f to_float (Vec8h x) {
__m256i a = _mm256_cvtepu16_epi32(x); // zero-extend each element to 32 bits
__m256i b = _mm256_slli_epi32(a, 16); // left-justify
__m256i c = _mm256_and_si256(b, _mm256_set1_epi32(0x80000000)); // isolate sign bit
__m256i d = _mm256_andnot_si256(_mm256_set1_epi32(0x80000000),b);// remove sign bit
__m256i e = _mm256_srli_epi32(d, 3); // put exponent and mantissa in place
__m256i f = _mm256_add_epi32(e, _mm256_set1_epi32(0x38000000)); // adjust exponent bias
// check for subnormal, INF, and NAN
__m256i xx = _mm256_set1_epi32(0x7C00); // exponent field in fp16
__m256i g = _mm256_and_si256(a, xx); // isolate exponent (low position)
__m256i zd = _mm256_cmpeq_epi32(g, _mm256_setzero_si256()); // -1 if x is zero or subnormal
__m256i in = _mm256_cmpeq_epi32(g, xx); // -1 if x is INF or NAN
__m256i ma = _mm256_and_si256(a, _mm256_set1_epi32(0x3FF)); // isolate mantissa
__m256 sn = _mm256_mul_ps(_mm256_cvtepi32_ps(ma), _mm256_set1_ps(1.f/16777216.f)); // converted subnormal = mantissa * 2^-24
__m256i snm = _mm256_and_si256(_mm256_castps_si256(sn), zd); // converted subnormal, masked
__m256i inm = _mm256_and_si256(in,_mm256_set1_epi32(0x7F800000));// INF or NAN exponent field, masked off if not INF or NAN
__m256i fm = _mm256_andnot_si256(zd, f); // normal result, masked off if zero or subnormal
__m256i r = _mm256_or_si256(fm, c); // insert sign bit
__m256i s = _mm256_or_si256(snm, inm); // combine branches
__m256i t = _mm256_or_si256(r, s); // combine branches
return _mm256_castsi256_ps(t); // cast result to float
}
// reduce precision: Vec8f -> Vec8h
static Vec8h to_float16 (Vec8f x) {
__m256i a = _mm256_castps_si256(x); // bit-cast to integer
// 23 bit mantissa rounded to 10 bits - nearest or even
__m256i r = _mm256_srli_epi32(a, 12); // get first discarded mantissa bit
__m256i s = _mm256_and_si256(a, _mm256_set1_epi32(0x2FFF)); // 0x2000 indicates if odd, 0x0FFF if remaining bits are nonzero
__m256i u = _mm256_cmpeq_epi32(s, _mm256_setzero_si256()); // false if odd or remaining bits nonzero
__m256i v = _mm256_andnot_si256(u, r); // bit 0 = 1 if we have to round up
__m256i w = _mm256_and_si256(v, _mm256_set1_epi32(1)); // = 1 if we need to round up
__m256i m = _mm256_srli_epi32(a, 13); // get mantissa in place
__m256i n = _mm256_and_si256(m, _mm256_set1_epi32(0x3FF)); // mantissa isolated
__m256i e = _mm256_and_si256(a, _mm256_set1_epi32(0x7FFFFFFF)); // remove sign bit
__m256i f = _mm256_sub_epi32(e, _mm256_set1_epi32(0x70 << 23)); // adjust exponent bias (underflow will be caught by uu below)
__m256i g = _mm256_srli_epi32(f, 13); // shift exponent into new place
__m256i h = _mm256_and_si256(g, _mm256_set1_epi32(0x3FC00)); // isolate exponent
__m256i i = _mm256_or_si256(n, h); // combine exponent and mantissa
__m256i j = _mm256_add_epi32(i, w); // round mantissa. Overflow will carry into exponent
// check for overflow and underflow
__m256i k = _mm256_cmpgt_epi32(j, _mm256_set1_epi32(0x7BFF)); // overflow
__m256i ee = _mm256_srli_epi32(e, 23); // exponent at position 0
__m256i ii = _mm256_cmpeq_epi32(ee, _mm256_set1_epi32(0xFF)); // check for INF and NAN
__m256i uu = _mm256_cmpgt_epi32(_mm256_set1_epi32(0x71), ee); // check for exponent underflow
__m256i pp = _mm256_or_si256(j, _mm256_set1_epi32(0x7C00)); // insert exponent if INF or NAN
// compute potential subnormal result
__m256i ss = _mm256_add_epi32(e, _mm256_set1_epi32(24 << 23)); // add 24 to exponent
__m256i tt = _mm256_cvtps_epi32(_mm256_castsi256_ps(ss)); // convert float to int with rounding
__m256i vv = _mm256_and_si256(tt, _mm256_set1_epi32(0x7FF)); // mantissa of subnormal number (possible overflow to normal)
// combine results
__m256i bb = _mm256_blendv_epi8(j, _mm256_set1_epi32(0x7C00), k);// select INF if overflow
__m256i dd = _mm256_blendv_epi8(bb, pp, ii); // select INF or NAN
__m256i cc = _mm256_blendv_epi8(dd, vv, uu); // select if subnormal or zero or exponent underflow
__m256i sa = _mm256_srai_epi32(a, 16); // extend sign bit to avoid saturation in pack instruction below
__m256i sb = _mm256_and_si256(sa, _mm256_set1_epi32(0xFFFF8000));// isolate sign
__m256i sc = _mm256_andnot_si256(_mm256_set1_epi32(0xFFFF8000), cc);// isolate exponent and mantissa
__m256i rr = _mm256_or_si256(sb, sc); // combine with sign
__m128i rl = _mm256_castsi256_si128(rr); // low half of results
__m128i rh = _mm256_extractf128_si256(rr, 1); // high half of results
__m128i rc = _mm_packs_epi32(rl, rh); // pack into 16-bit words (words are sign extended so they will not saturate)
return rc; // return as Vec8h
}
#else // __F16C__ not defined, AVX2 not supported
// extend precision: Vec8h -> Vec8f
static Vec8f to_float (Vec8h x) {
Vec8s xx = __m128i(x);
Vec4ui a1 = _mm_unpacklo_epi16(xx, _mm_setzero_si128 ());
Vec4ui a2 = _mm_unpackhi_epi16(xx, _mm_setzero_si128 ());
Vec4ui b1 = a1 << 16; // left-justify
Vec4ui b2 = a2 << 16;
Vec4ui c1 = b1 & 0x80000000; // isolate sign bit
Vec4ui c2 = b2 & 0x80000000;
Vec4ui d1 = _mm_andnot_si128(Vec4ui(0x80000000), b1); // remove sign bit
Vec4ui d2 = _mm_andnot_si128(Vec4ui(0x80000000), b2);
Vec4ui e1 = d1 >> 3; // put exponent and mantissa in place
Vec4ui e2 = d2 >> 3;
Vec4ui f1 = e1 + 0x38000000; // adjust exponent bias
Vec4ui f2 = e2 + 0x38000000;
Vec4ui g1 = a1 & 0x7C00; // isolate exponent (low position)
Vec4ui g2 = a2 & 0x7C00;
Vec4ib z1 = g1 == 0; // true if x is zero or subnormal (broad boolean vector)
Vec4ib z2 = g2 == 0;
Vec4ib i1 = g1 == 0x7C00; // true if x is INF or NAN
Vec4ib i2 = g2 == 0x7C00;
Vec4ui m1 = a1 & 0x3FF; // isolate mantissa (low position)
Vec4ui m2 = a2 & 0x3FF;
Vec4f s1 = to_float(m1) * (1.f/16777216.f); // converted subnormal = mantissa * 2^-24
Vec4f s2 = to_float(m2) * (1.f/16777216.f);
Vec4ui sm1 = Vec4ui(reinterpret_i(s1)) & Vec4ui(z1); // converted subnormal, masked
Vec4ui sm2 = Vec4ui(reinterpret_i(s2)) & Vec4ui(z2);
Vec4ui inm1 = Vec4ui(i1) & Vec4ui(0x7F800000); // INF or NAN exponent field, masked off if not INF or NAN
Vec4ui inm2 = Vec4ui(i2) & Vec4ui(0x7F800000);
Vec4ui fm1 = _mm_andnot_si128(Vec4ui(z1), f1); // normal result, masked off if zero or subnormal
Vec4ui fm2 = _mm_andnot_si128(Vec4ui(z2), f2);
Vec4ui r1 = fm1 | c1; // insert sign bit
Vec4ui r2 = fm2 | c2;
Vec4ui q1 = sm1 | inm1; // combine branches
Vec4ui q2 = sm2 | inm2;
Vec4ui t1 = r1 | q1; // combine branches
Vec4ui t2 = r2 | q2;
Vec4f u1 = reinterpret_f(t1); // bit-cast to float
Vec4f u2 = reinterpret_f(t2);
return Vec8f(u1, u2); // combine low and high part
}
// reduce precision: Vec8f -> Vec8h
static Vec8h to_float16 (Vec8f x) {
Vec4ui a1 = _mm_castps_si128(x.get_low()); // low half
Vec4ui a2 = _mm_castps_si128(x.get_high()); // high half
Vec4ui r1 = a1 >> 12; // get first discarded mantissa bit
Vec4ui r2 = a2 >> 12;
Vec4ui s1 = a1 & 0x2FFF; // 0x2000 indicates if odd, 0x0FFF if remaining bits are nonzero
Vec4ui s2 = a2 & 0x2FFF;
Vec4ib u1 = s1 == 0; // false if odd or remaining bits nonzero
Vec4ib u2 = s2 == 0;
Vec4ui v1 = _mm_andnot_si128(u1, r1); // bit 0 = 1 if we have to round up
Vec4ui v2 = _mm_andnot_si128(u2, r2);
Vec4ui w1 = v1 & 1; // = 1 if we need to round up
Vec4ui w2 = v2 & 1;
Vec4ui m1 = a1 >> 13; // get mantissa in place
Vec4ui m2 = a2 >> 13;
Vec4ui n1 = m1 & 0x3FF; // mantissa isolated
Vec4ui n2 = m2 & 0x3FF;
Vec4ui e1 = a1 & 0x7FFFFFFF; // remove sign bit
Vec4ui e2 = a2 & 0x7FFFFFFF;
Vec4ui f1 = e1 - (0x70 << 23); // adjust exponent bias
Vec4ui f2 = e2 - (0x70 << 23);
Vec4ui g1 = f1 >> 13; // shift exponent into new place
Vec4ui g2 = f2 >> 13;
Vec4ui h1 = g1 & 0x3FC00; // isolate exponent
Vec4ui h2 = g2 & 0x3FC00;
Vec4ui i1 = n1 | h1; // combine exponent and mantissa
Vec4ui i2 = n2 | h2;
Vec4ui j1 = i1 + w1; // round mantissa. Overflow will carry into exponent
Vec4ui j2 = i2 + w2;
// check for overflow and underflow
Vec4ib k1 = j1 > 0x7BFF; // overflow
Vec4ib k2 = j2 > 0x7BFF;
Vec4ui ee1 = e1 >> 23; // exponent at position 0
Vec4ui ee2 = e2 >> 23;
Vec4ib ii1 = ee1 == 0xFF; // check for INF and NAN
Vec4ib ii2 = ee2 == 0xFF;
Vec4ib uu1 = ee1 < 0x71; // exponent underflow
Vec4ib uu2 = ee2 < 0x71;
Vec4i pp1 = Vec4i(0x7C00) | j1; // insert exponent if INF or NAN
Vec4i pp2 = Vec4i(0x7C00) | j2;
// compute potential subnormal result
Vec4ui ss1 = e1 + (24 << 23); // add 24 to exponent
Vec4ui ss2 = e2 + (24 << 23);
Vec4ui tt1 = _mm_cvtps_epi32(_mm_castsi128_ps(ss1)); // convert float to int with rounding
Vec4ui tt2 = _mm_cvtps_epi32(_mm_castsi128_ps(ss2));
Vec4ui vv1 = tt1 & 0x7FF; // mantissa of subnormal number (possible overflow to normal)
Vec4ui vv2 = tt2 & 0x7FF;
// combine results
Vec4i bb1 = select(k1, 0x7C00, j1); // select INF if overflow
Vec4i bb2 = select(k2, 0x7C00, j2);
Vec4i dd1 = select(ii1, pp1, bb1); // select INF or NAN
Vec4i dd2 = select(ii2, pp2, bb2);
Vec4i cc1 = select(uu1, vv1, dd1); // select if subnormal or zero or exponent underflow
Vec4i cc2 = select(uu2, vv2, dd2);
// get sign bit
Vec4i sa1 = Vec4i(a1) >> 16; // extend sign bit to avoid saturation in pack instruction below
Vec4i sa2 = Vec4i(a2) >> 16;
Vec4i const smask = 0xFFFF8000; // extended sign mask
Vec4i sb1 = sa1 & smask; // isolate sign
Vec4i sb2 = sa2 & smask;
Vec4i sc1 = _mm_andnot_si128(smask, cc1); // isolate exponent and mantissa
Vec4i sc2 = _mm_andnot_si128(smask, cc2);
Vec4i rr1 = sb1 | sc1; // combine with sign
Vec4i rr2 = sb2 | sc2;
Vec4i rc = _mm_packs_epi32(rr1, rr2); // pack into 16-bit words (words are sign extended so they will not saturate)
return (__m128i)rc; // return as Vec8h
}
#endif // __F16C__
/*****************************************************************************
*
* Operators for Vec8h
*
*****************************************************************************/
// vector operator + : add element by element
static inline Vec8h operator + (Vec8h const a, Vec8h const b) {
return to_float16(to_float(a) + to_float(b));
}
// vector operator + : add vector and scalar
static inline Vec8h operator + (Vec8h const a, Float16 b) {
return a + Vec8h(b);
}
static inline Vec8h operator + (Float16 a, Vec8h const b) {
return Vec8h(a) + b;
}
// vector operator += : add
static inline Vec8h & operator += (Vec8h & a, Vec8h const b) {
a = a + b;
return a;
}
// postfix operator ++
static inline Vec8h operator ++ (Vec8h & a, int) {
Vec8h a0 = a;
a = a + Float16(1.f); // 1.0f16 not supported by g++ version 12.1
return a0;
}
// prefix operator ++
static inline Vec8h & operator ++ (Vec8h & a) {
a = a + Float16(1.f);
return a;
}
// vector operator - : subtract element by element
static inline Vec8h operator - (Vec8h const a, Vec8h const b) {
return to_float16(to_float(a) - to_float(b));
}
// vector operator - : subtract vector and scalar
static inline Vec8h operator - (Vec8h const a, Float16 b) {
return a - Vec8h(b);
}
static inline Vec8h operator - (Float16 a, Vec8h const b) {
return Vec8h(a) - b;
}
// vector operator - : unary minus
// Change sign bit, even for 0, INF and NAN
static inline Vec8h operator - (Vec8h const a) {
return _mm_xor_si128(__m128i(a), _mm_set1_epi32(0x80008000));
}
// vector operator -= : subtract
static inline Vec8h & operator -= (Vec8h & a, Vec8h const b) {
a = a - b;
return a;
}
// postfix operator --
static inline Vec8h operator -- (Vec8h & a, int) {
Vec8h a0 = a;
a = a - Vec8h(Float16(1.f));
return a0;
}
// prefix operator --
static inline Vec8h & operator -- (Vec8h & a) {
a = a - Vec8h(Float16(1.f));
return a;
}
// vector operator * : multiply element by element
static inline Vec8h operator * (Vec8h const a, Vec8h const b) {
return to_float16(to_float(a) * to_float(b));
}
// vector operator * : multiply vector and scalar
static inline Vec8h operator * (Vec8h const a, Float16 b) {
return a * Vec8h(b);
}
static inline Vec8h operator * (Float16 a, Vec8h const b) {
return Vec8h(a) * b;
}
// vector operator *= : multiply
static inline Vec8h & operator *= (Vec8h & a, Vec8h const b) {
a = a * b;
return a;
}
// vector operator / : divide all elements by same integer
static inline Vec8h operator / (Vec8h const a, Vec8h const b) {
return to_float16(to_float(a) / to_float(b));
}
// vector operator / : divide vector and scalar
static inline Vec8h operator / (Vec8h const a, Float16 b) {
return a / Vec8h(b);
}
static inline Vec8h operator / (Float16 a, Vec8h const b) {
return Vec8h(a) / b;
}
// vector operator /= : divide
static inline Vec8h & operator /= (Vec8h & a, Vec8h const b) {
a = a / b;
return a;
}
// vector operator == : returns true for elements for which a == b
static inline Vec8hb operator == (Vec8h const a, Vec8h const b) {
return Vec8fb2hb(to_float(a) == to_float(b));
}
// vector operator != : returns true for elements for which a != b
static inline Vec8hb operator != (Vec8h const a, Vec8h const b) {
return Vec8fb2hb(to_float(a) != to_float(b));
}
// vector operator < : returns true for elements for which a < b
static inline Vec8hb operator < (Vec8h const a, Vec8h const b) {
return Vec8fb2hb(to_float(a) < to_float(b));
}
// vector operator <= : returns true for elements for which a <= b
static inline Vec8hb operator <= (Vec8h const a, Vec8h const b) {
return Vec8fb2hb(to_float(a) <= to_float(b));
}
// vector operator > : returns true for elements for which a > b
static inline Vec8hb operator > (Vec8h const a, Vec8h const b) {
return Vec8fb2hb(to_float(a) > to_float(b));
}
// vector operator >= : returns true for elements for which a >= b
static inline Vec8hb operator >= (Vec8h const a, Vec8h const b) {
return Vec8fb2hb(to_float(a) >= to_float(b));
}
// Bitwise logical operators
// vector operator & : bitwise and
static inline Vec8h operator & (Vec8h const a, Vec8h const b) {
return _mm_and_si128(__m128i(a), __m128i(b));
}
// vector operator &= : bitwise and
static inline Vec8h & operator &= (Vec8h & a, Vec8h const b) {
a = a & b;
return a;
}
// vector operator & : bitwise and of Vec8h and Vec8hb
static inline Vec8h operator & (Vec8h const a, Vec8hb const b) {
#if INSTRSET >= 10 // compact boolean vector
return _mm_maskz_mov_epi16(b, a);
#else // broad boolean vector
return _mm_and_si128(__m128i(a), __m128i(b));
#endif
}
static inline Vec8h operator & (Vec8hb const a, Vec8h const b) {
return b & a;
}
// vector operator | : bitwise or
static inline Vec8h operator | (Vec8h const a, Vec8h const b) {
return _mm_or_si128(__m128i(a), __m128i(b));
}
// vector operator |= : bitwise or
static inline Vec8h & operator |= (Vec8h & a, Vec8h const b) {
a = a | b;
return a;
}
// vector operator ^ : bitwise xor
static inline Vec8h operator ^ (Vec8h const a, Vec8h const b) {
return _mm_xor_si128(__m128i(a), __m128i(b));
}
// vector operator ^= : bitwise xor
static inline Vec8h & operator ^= (Vec8h & a, Vec8h const b) {
a = a ^ b;
return a;
}
// vector operator ! : logical not. Returns Boolean vector
static inline Vec8hb operator ! (Vec8h const a) {
return a == Vec8h(0.0);
}
/*****************************************************************************
*
* Functions for Vec8h
*
*****************************************************************************/
// Select between two operands. Corresponds to this pseudocode:
// for (int i = 0; i < 4; i++) result[i] = s[i] ? a[i] : b[i];
static inline Vec8h select(Vec8hb const s, Vec8h const a, Vec8h const b) {
return __m128i(select(Vec8sb(s), Vec8s(__m128i(a)), Vec8s(__m128i(b))));
}
// Conditional add: For all vector elements i: result[i] = f[i] ? (a[i] + b[i]) : a[i]
static inline Vec8h if_add(Vec8hb const f, Vec8h const a, Vec8h const b) {
return a + (b & f);
}
// Conditional subtract: For all vector elements i: result[i] = f[i] ? (a[i] - b[i]) : a[i]
static inline Vec8h if_sub(Vec8hb const f, Vec8h const a, Vec8h const b) {
return a - (b & f);
}
// Conditional multiply: For all vector elements i: result[i] = f[i] ? (a[i] * b[i]) : a[i]
static inline Vec8h if_mul(Vec8hb const f, Vec8h const a, Vec8h const b) {
return select(f, a*b, a);
}
// Conditional divide: For all vector elements i: result[i] = f[i] ? (a[i] / b[i]) : a[i]
static inline Vec8h if_div(Vec8hb const f, Vec8h const a, Vec8h const b) {
return select(f, a/b, a);
}
// Sign functions
// Function sign_bit: gives true for elements that have the sign bit set
// even for -0.0f, -INF and -NAN
// Note that sign_bit(Vec8h(-0.0f16)) gives true, while Vec8h(-0.0f16) < Vec8h(0.0f16) gives false
// (the underscore in the name avoids a conflict with a macro in Intel's mathimf.h)
static inline Vec8hb sign_bit(Vec8h const a) {
Vec8s t1 = __m128i(a); // reinterpret as 16-bit integer
Vec8s t2 = t1 >> 15; // extend sign bit
return t2 != 0;
}
// Function sign_combine: changes the sign of a when b has the sign bit set
// same as select(sign_bit(b), -a, a)
static inline Vec8h sign_combine(Vec8h const a, Vec8h const b) {
return a ^ (b & Vec8h(Float16(-0.0)));
}
// Categorization functions
// Function is_finite: gives true for elements that are normal, subnormal or zero,
// false for INF and NAN
// (the underscore in the name avoids a conflict with a macro in Intel's mathimf.h)
static inline Vec8hb is_finite(Vec8h const a) {
Vec8s b = __m128i(a);
return (b & 0x7C00) != 0x7C00;
}
// Function is_inf: gives true for elements that are +INF or -INF
// false for finite numbers and NAN
// (the underscore in the name avoids a conflict with a macro in Intel's mathimf.h)
static inline Vec8hb is_inf(Vec8h const a) {
Vec8s b = __m128i(a);
return (b & 0x7FFF) == 0x7C00;
}
// Function is_nan: gives true for elements that are +NAN or -NAN
// false for finite numbers and +/-INF
// (the underscore in the name avoids a conflict with a macro in Intel's mathimf.h)
static inline Vec8hb is_nan(Vec8h const a) {
Vec8s b = __m128i(a);
return (b & 0x7FFF) > 0x7C00;
}
// Function is_subnormal: gives true for elements that are subnormal
// false for finite numbers, zero, NAN and INF
static inline Vec8hb is_subnormal(Vec8h const a) {
Vec8s b = __m128i(a);
return (b & 0x7C00) == 0 && (b & 0x3FF) != 0;
}
// Function is_zero_or_subnormal: gives true for elements that are zero or subnormal
// false for finite numbers, NAN and INF
static inline Vec8hb is_zero_or_subnormal(Vec8h const a) {
Vec8s b = __m128i(a);
return (b & 0x7C00) == 0;
}
// Function infinite8h: returns a vector where all elements are +INF
static inline Vec8h infinite8h() {
return Vec8h(_mm_set1_epi16(0x7C00));
}
// template for producing quiet NAN
template <>
Vec8h nan_vec<Vec8h>(uint32_t payload) {
if constexpr (Vec8h::elementtype() == 15) { // Float16
return Vec8h(_mm_set1_epi16(0x7E00 | (payload & 0x01FF)));
}
}
// Function nan8h: returns a vector where all elements are NAN (quiet)
static inline Vec8h nan8h(int n = 0x10) {
return nan_vec<Vec8h>(n);
}
// This function returns the code hidden in a NAN. The sign bit is ignored
static inline Vec8us nan_code(Vec8h const x) {
Vec8us a = Vec8us(reinterpret_i(x));
Vec8us const n = 0x3FF;
return select(is_nan(x), a & n, Vec8us(0));
}
// General arithmetic functions, etc.
// Horizontal add: Calculates the sum of all vector elements.
static inline Float16 horizontal_add(Vec8h const a) {
return Float16(horizontal_add(to_float(a)));
}
// same, with high precision
static inline float horizontal_add_x(Vec8h const a) {
return horizontal_add(to_float(a));
}
// function max: a > b ? a : b
static inline Vec8h max(Vec8h const a, Vec8h const b) {
return to_float16(max(to_float(a), to_float(b)));
}
// function min: a < b ? a : b
static inline Vec8h min(Vec8h const a, Vec8h const b) {
return to_float16(min(to_float(a), to_float(b)));
}
// NAN-safe versions of maximum and minimum are in vector_convert.h
// function abs: absolute value
static inline Vec8h abs(Vec8h const a) {
return _mm_and_si128(a, _mm_set1_epi16(0x7FFF));
}
// function sqrt: square root
static inline Vec8h sqrt(Vec8h const a) {
return to_float16(sqrt(to_float(a)));
}
// function square: a * a
static inline Vec8h square(Vec8h const a) {
return a * a;
}
// The purpose of this template is to prevent implicit conversion of a float
// exponent to int when calling pow(vector, float) and vectormath_exp.h is not included
template <typename TT> static Vec8h pow(Vec8h const a, TT const n); // = delete
// Raise floating point numbers to integer power n
// To do: Optimize pow<int>(Vec8h/Vec16h/Vec32h, n) to do calculations with float precision
template <>
inline Vec8h pow<int>(Vec8h const x0, int const n) {
return to_float16(pow_template_i<Vec8f>(to_float(x0), n));
}
// allow conversion from unsigned int
template <>
inline Vec8h pow<uint32_t>(Vec8h const x0, uint32_t const n) {
return to_float16(pow_template_i<Vec8f>(to_float(x0), (int)n));
}
// Raise floating point numbers to integer power n, where n is a compile-time constant:
// Template in vectorf128.h is used
//template <typename V, int n>