diff --git a/book/src/05_language_reference/13_integrated_test.md b/book/src/05_language_reference/13_integrated_test.md
index e3e1b1e3..3a374b90 100644
--- a/book/src/05_language_reference/13_integrated_test.md
+++ b/book/src/05_language_reference/13_integrated_test.md
@@ -4,6 +4,9 @@ Integrated test can be marked by `#[test(test_name)]` attribute.
 The marked block will be identified as test, and executed through `veryl test` command.
 The top level module of the block must have the same name as the test name.
 
+The messages through `$info`, `$warning`, `$error` and `$fatal` system function are handled by Veryl compiler, and shown as exectution log.
+The calls of `$error` and `$fatal` are treated as test failure.
+
 The following example, a SystemVerilog source code embeded by `embed` declaration are marked as test.
 
 ```veryl,playground