From 988ac6c1c735166d26b919e99c2a8e69fe2c1c99 Mon Sep 17 00:00:00 2001 From: dalance Date: Fri, 19 Apr 2024 11:42:30 +0900 Subject: [PATCH] Move tests to embed block in Veryl code --- Veryl.toml | 6 ++ src/binary_enc_dec/binary_decoder.veryl | 25 ++++++ src/binary_enc_dec/binary_encoder.veryl | 24 ++++++ src/delay/delay.veryl | 2 +- src/gray/bin2gray.veryl | 32 +++++++ src/lfsr/lfsr_galois.veryl | 86 +++++++++++++++++++ .../binary_enc_dec/binary_decoder_test.sv | 24 ------ .../binary_enc_dec/binary_encoder_test.sv | 23 ----- testbench/gray/gray_bench.sv | 28 ------ testbench/lfsr_galois_bench.sv | 83 ------------------ 10 files changed, 174 insertions(+), 159 deletions(-) delete mode 100644 testbench/binary_enc_dec/binary_decoder_test.sv delete mode 100644 testbench/binary_enc_dec/binary_encoder_test.sv delete mode 100644 testbench/gray/gray_bench.sv delete mode 100644 testbench/lfsr_galois_bench.sv diff --git a/Veryl.toml b/Veryl.toml index cd9747c..b90322a 100644 --- a/Veryl.toml +++ b/Veryl.toml @@ -11,3 +11,9 @@ target = {type = "directory", path = "target/src"} [doc] path = "target/doc" + +[test.vcs] +compile_args = ["-full64"] + +[test.verilator] +compile_args = ["-Wno-MULTIDRIVEN", "-Wno-WIDTHTRUNC", "-Wno-WIDTHEXPAND"] diff --git a/src/binary_enc_dec/binary_decoder.veryl b/src/binary_enc_dec/binary_decoder.veryl index 5ec6c85..fc0f22d 100644 --- a/src/binary_enc_dec/binary_decoder.veryl +++ b/src/binary_enc_dec/binary_decoder.veryl @@ -63,3 +63,28 @@ module _bin_decoder #( assign o_unary = {r_unary, r_unary} & {mask_top, mask_bot}; } } + +#[test(test_binary_decoder)] +embed (inline) sv{{{ +module test_binary_decoder; + + parameter BIN_WIDTH = 8; + parameter UNARY_WIDTH = 1 << BIN_WIDTH; + + logic i_en; + logic [BIN_WIDTH-1:0] i_bin; + logic [UNARY_WIDTH-1:0] o_unary; + + std_binary_decoder #(BIN_WIDTH) dut (.*); + + initial begin + i_en = 1'b1; + + for (longint i = 0; i < UNARY_WIDTH; ++i) begin + i_bin = i; + #1 assert($onehot(o_unary)); + assert(o_unary[i_bin] == 1'b1) else $error("error detected"); + end + end +endmodule +}}} diff --git a/src/binary_enc_dec/binary_encoder.veryl b/src/binary_enc_dec/binary_encoder.veryl index b4bdb58..6ed4c29 100644 --- a/src/binary_enc_dec/binary_encoder.veryl +++ b/src/binary_enc_dec/binary_encoder.veryl @@ -86,3 +86,27 @@ module _binary_encoder #( } } + +#[test(test_binary_encoder)] +embed (inline) sv{{{ +module test_binary_encoder; + + parameter BIN_WIDTH = 8; + parameter UNARY_WIDTH = 1 << BIN_WIDTH; + + logic i_en; + logic [BIN_WIDTH-1:0] o_bin; + logic [UNARY_WIDTH-1:0] i_unary; + + std_binary_encoder #(UNARY_WIDTH) dut (.*); + + initial begin + i_en = 1'b1; + + for (longint i = 0; i < UNARY_WIDTH; ++i) begin + #1 i_unary = 1 << i; + #1 assert(i_unary[o_bin] == 1'b1) else $error("error detected"); + end + end +endmodule +}}} diff --git a/src/delay/delay.veryl b/src/delay/delay.veryl index bd11f9b..7d3eb50 100644 --- a/src/delay/delay.veryl +++ b/src/delay/delay.veryl @@ -22,7 +22,7 @@ pub module delay #( assign o_d = delay[DELAY - 1]; always_ff (i_clk, i_rst) { if_reset { - delay = '0; + delay = '{0}; } else { delay[0] = i_d; for i: u32 in 1..DELAY { diff --git a/src/gray/bin2gray.veryl b/src/gray/bin2gray.veryl index 7b1b267..148a157 100644 --- a/src/gray/bin2gray.veryl +++ b/src/gray/bin2gray.veryl @@ -12,3 +12,35 @@ pub module bin2gray #( ) { assign o_gray = i_bin ^ (i_bin >> 1); } + +#[test(test_gray)] +embed (inline) sv{{{ +module test_gray; + localparam WIDTH = 16; + logic [WIDTH-1:0] i_bin; + logic [WIDTH-1:0] o_gray; + logic [WIDTH-1:0] o_bin; + logic [WIDTH-1:0] g_bin; + + always_comb begin + g_bin = '0; + for (int i = 0; i < WIDTH; ++i) begin + g_bin ^= o_gray >> i; + end + end + + std_bin2gray #(WIDTH) dut2(.i_bin, .o_gray); + std_gray2bin #(WIDTH) dut1(.i_gray(o_gray), .o_bin); + + initial begin + for (longint i = 0; i < (1 << WIDTH); ++i) begin + i_bin = i; + #1; + assert(o_bin == g_bin) else $error("error detected"); + assert(i_bin == o_bin) else $error("error detected"); + #1; + end + end + +endmodule +}}} diff --git a/src/lfsr/lfsr_galois.veryl b/src/lfsr/lfsr_galois.veryl index 80d35fb..225789e 100644 --- a/src/lfsr/lfsr_galois.veryl +++ b/src/lfsr/lfsr_galois.veryl @@ -110,3 +110,89 @@ pub module lfsr_galois #( } } } + +#[test(test_lfsr_galois)] +embed (inline) sv{{{ +module test_lfsr_galois; + parameter MAXSIZE = 24; + parameter MINSIZE = 2; + + logic [MAXSIZE-1:MINSIZE] done; + logic [MAXSIZE-1:MINSIZE] working; + logic i_clk; + + for (genvar i = MINSIZE; i < MAXSIZE; ++i) begin + initial $info("Spawning LFSR of Size %d", i); + lfsr_galois_bench #(.SIZE(i)) u_lfsr(.i_clk, .done(done[i]), .working(working[i])); + end + default clocking + @(posedge i_clk); + endclocking + + initial forever begin + ##4 + if (&done) begin + if (|working) begin + $info("Finishing Simulations with \033[32m100%% Success\033[0m"); + end else begin + $error("Finishing Simulations with \033[31mErrors\033[0m"); + end + $finish; + end + end + + initial begin + i_clk = 1'b0; + forever #5 i_clk = ~i_clk; + end +endmodule + +module lfsr_galois_bench #(parameter SIZE=64) (input i_clk, output logic done, output logic working); + logic [SIZE:0] limit; + + + logic i_en, i_set; + logic [SIZE-1:0] i_setval; + logic [SIZE-1:0] o_val; + + std_lfsr_galois #(.SIZE(SIZE)) dut (.*); + + + default clocking + @(posedge i_clk); + endclocking + + + initial begin + int outvecs [logic[SIZE-1:0]]; + working = 1'b1; + $info("Begining LFSR of Size %d", SIZE); + done = 1'b0; + i_en = 1'b1; + i_set = 1'b1; + i_setval = 16'h0001; + + ##2; + + i_set = 1'b0; + limit = '1; + limit[0] = 1'b0; + limit[SIZE] = 1'b0; + + for (int i = 0; i < limit; i += 1) begin + ##1; + assert(0 == outvecs.exists(o_val)); + working &= !outvecs.exists(o_val); + outvecs[o_val] = 1'b1; + end + + done = 1'b1; + + if (working) + $info("Succesfully Ending LFSR of Size %0d", SIZE); + else + $error("Failure Detecing in LFSR of size %0d", SIZE); + end + +endmodule +}}} diff --git a/testbench/binary_enc_dec/binary_decoder_test.sv b/testbench/binary_enc_dec/binary_decoder_test.sv deleted file mode 100644 index 1f459b7..0000000 --- a/testbench/binary_enc_dec/binary_decoder_test.sv +++ /dev/null @@ -1,24 +0,0 @@ -module binary_decoder_test; - - parameter BIN_WIDTH = 8; - parameter UNARY_WIDTH = 1 << BIN_WIDTH; - - logic i_en; - logic [BIN_WIDTH-1:0] i_bin; - logic [UNARY_WIDTH-1:0] o_unary; - - std_binary_decoder #(BIN_WIDTH) (.*); - - initial begin - i_en = 1'b1; - - for (longint i = 0; i < UNARY_WIDTH; ++i) begin - i_bin = i; - #1 assert($onehot(o_unary)); - assert(o_unary[i_bin] == 1'b1); - end - - end - -endmodule - diff --git a/testbench/binary_enc_dec/binary_encoder_test.sv b/testbench/binary_enc_dec/binary_encoder_test.sv deleted file mode 100644 index 9c0b59a..0000000 --- a/testbench/binary_enc_dec/binary_encoder_test.sv +++ /dev/null @@ -1,23 +0,0 @@ -module binary_encoder_test; - - parameter BIN_WIDTH = 8; - parameter UNARY_WIDTH = 1 << BIN_WIDTH; - - logic i_en; - logic [BIN_WIDTH-1:0] o_bin; - logic [UNARY_WIDTH-1:0] i_unary; - - std_binary_encoder #(UNARY_WIDTH) (.*); - - initial begin - i_en = 1'b1; - - for (longint i = 0; i < UNARY_WIDTH; ++i) begin - #1 i_unary = 1 << i; - #1 assert(i_unary[o_bin] == 1'b1); - end - - end - -endmodule - diff --git a/testbench/gray/gray_bench.sv b/testbench/gray/gray_bench.sv deleted file mode 100644 index 82ec0c2..0000000 --- a/testbench/gray/gray_bench.sv +++ /dev/null @@ -1,28 +0,0 @@ -module gray_bench; - localparam WIDTH = 32; - logic [WIDTH-1:0] i_bin; - logic [WIDTH-1:0] o_gray; - logic [WIDTH-1:0] o_bin; - logic [WIDTH-1:0] g_bin; - - always_comb begin - g_bin = '0; - for (int i = 0; i < WIDTH; ++i) begin - g_bin ^= o_gray >> i; - end - end - - std_bin2gray #(WIDTH) dut2(.i_bin, .o_gray); - std_gray2bin #(WIDTH) dut1(.i_gray(o_gray), .o_bin); - - initial begin - for (longint i = 0; i < (1 << WIDTH); ++i) begin - i_bin = i; - #1; - assert(o_bin == g_bin); - assert(i_bin == o_bin); - #1; - end - end - -endmodule diff --git a/testbench/lfsr_galois_bench.sv b/testbench/lfsr_galois_bench.sv deleted file mode 100644 index bf6ad21..0000000 --- a/testbench/lfsr_galois_bench.sv +++ /dev/null @@ -1,83 +0,0 @@ -module testbench; - parameter MAXSIZE = 24; - parameter MINSIZE = 2; - - logic [MAXSIZE-1:MINSIZE] done; - logic [MAXSIZE-1:MINSIZE] working; - logic i_clk; - - for (genvar i = MINSIZE; i < MAXSIZE; ++i) begin - initial $display ("Spawning LFSR of Size %d", i); - lfsr_galois_bench #(.SIZE(i)) u_lfsr(.i_clk, .done(done[i]), .working(working[i])); - end - default clocking - @(posedge i_clk); - endclocking - - initial forever begin - ##4 - if (&done) begin - if (|working) begin - $display("Finishing Simulations with \033[32m100%% Success\033[0m"); - end else begin - $display("Finishing Simulations with \033[31mErrors\033[0m"); - end - $finish; - end - end - - initial begin - i_clk = 1'b0; - forever #5 i_clk = ~i_clk; - end -endmodule - -module lfsr_galois_bench #(parameter SIZE=64) (input i_clk, output logic done, output logic working); - logic [SIZE:0] limit; - - - logic i_en, i_set; - logic [SIZE-1:0] i_setval; - logic [SIZE-1:0] o_val; - - std_lfsr_galois #(.SIZE(SIZE)) dut (.*); - - - default clocking - @(posedge i_clk); - endclocking - - - initial begin - int outvecs [logic[SIZE-1:0]]; - working = 1'b1; - $display("Begining LFSR of Size %d", SIZE); - done = 1'b0; - i_en = 1'b1; - i_set = 1'b1; - i_setval = 16'h0001; - - ##2; - - i_set = 1'b0; - limit = '1; - limit[0] = 1'b0; - limit[SIZE] = 1'b0; - - for (int i = 0; i < limit; i += 1) begin - ##1; - assert(0 == outvecs.exists(o_val)); - working &= !outvecs.exists(o_val); - outvecs[o_val] = 1'b1; - end - - done = 1'b1; - - if (working) - $display("Succesfully Ending LFSR of Size %0d", SIZE); - else - $display("Failure Detecing in LFSR of size %0d", SIZE); - - end - -endmodule