Testbenches are an essential part of validating digital design systems. In this lecture we will discuss the purpose of testbenches and the general structure of a simple testbench.
Reading
- Chapter 1 of System Verilog for Verification. Download this pdf from the library as we will use it later in the semester.
- Stephen Edwards Verilog Slides (48-56)
Key Concepts
- Difference between tcl scripts and Verilog behavioral testbenches
- Discrete time simulation model in Verilog (use of
#operator) - Essential components of a testbench
- initial block and how it differs from always block
- How to use basic system functions:
$display,$time,$random,$timeformat, etc. - How to create a basic testbench
Resources
- ECEN 220 Testbench Review
- ChipVerify summary of display,
- Verilog 95 Testbench Lecture Slides